Silicon

https://doi.org/10.1007/s12633-019-00321-3

ORIGINAL PAPER

A Novel Extended Source TFET with δp+- SiGe Layer

Jagritee Talukdar 2 & Gopal Rawat 1 & Kavicharan Mummaneni 3

Received: 6 June 2019 / Accepted: 7 November 2019

# Springer Nature B.V. 2020

Abstract
Tunnel FET (TFET) is a significant discovery in the field of low power application, which has the ability to sustain short channel
effects arising due to scaling. But the disadvantage of TFET is low ON current, and it is a challenge to maintain a high ON current
with very low OFF current, hence it is tough to obtain a higher switching ratio maintaining a low SS. In this paper, to investigate
the influence of dimensionality and other electrical parameters on TFET with simulation, a device based on an extended source
TFET (ES-TFET) with SiGe pocket layer at the edge of source channel junction is proposed. It shows excellent performance
improvement over standard TFET. In this paper, for the first time the effect of increase in length of the extended source has been
studied while SS degrades but threshold voltage remains unchanged, also extended source distance from surface degraded effect
on SS has been improved with the introduction of SiGe layer. Various scaling parameters have been investigated to study its
impact on electrical parameters showing an ON-current of 0.01 mA/μm and OFF-current of 6.48 × 10−17 A/μm neglecting gate
leakage for 1 V gate and drain voltage. The Remarkable value of SS of 16 mV/decade and ON-OFF current ratio of more than
1011 for a threshold voltage of 0.4 V is obtained. Scalability of the proposed device according to ITRS is well maintained, and it is
validated by its improved performance over the wide range of channel length.

Keywords Tunnel FET . ES-TFET . SiGe TFET . Subthreshold swing . ON-OFF current ratio

1 Introduction voltage which limits the scaling of supply voltage. In addition,

CMOS is the unbeaten evolution of the last few decades.
However, as downscaling of the devices comes into existence,
CMOS has become insufficient for modern needs. As the need
for curbing power dissipation, leakage current, subthreshold
swing (SS), etc., becoming the essential part of modern tech-
nology, CMOS somewhere lagged to achieve them all. It’s
because of the limited subthreshold swing of kT/q ln(10)
=60 mV/decade leading to a non-scalability of the threshold
* Jagritee Talukdar
jagriteetalukdar5@gmail.com
Gopal Rawat
gopal.rawat.ece11@iitbhu.ac.in
Kavicharan Mummaneni
kavicharan.mummaneni@gmail.com
1
ECE Department, NIT Hamirpur, Hamirpur, Himachal Pradesh,
India
2
ECE Department, NIT Silchar, Silchar, Assam, India
3
ECE Department, NIT Silchar, Silchar, Assam, India
fixed supply voltage and growing leakage current degrades
the switching ratio (ION/IOFF ratio). The SS is limited due to
thermally broadened Fermi distribution function [1–7]. Many
new inventions have taken place to meet these needs, and
Tunnel FET stands out to be one of them.
The Tunnel FET is a gated p-i-n structured FET which
works on the principle of band to band tunneling (BTBT)
rather than thermionic emission in MOSFET, which makes
Tunnel FET capable of achieving low leakage current and a
lower SS [8]. However, it is still struggling to achieve high
ON-current in large band gap materials [1]. Hence, different
structures of TFET have been proposed such as Double gate
TFET, Group III–V-semiconductor-based TFETs, Carbon-
based TFETs [7], use of High K- dielectric based TFET [9],
Hetero-Junction TFET [10], SOI-TFET [11], stacked source
TFET [12] are remarkable ones. Among them, one of the
remarkable Tunnel FET devices has a delta-layer of SiGe at
the source-channel junction, which improves the SS and ON-
current by reducing the barrier width [13]. Another similar
work in [14], where source junction is varied to enhance the
BTBT, hence provides a high ON-current and minimized SS
but its performance is limited for channel length below
100 nm. In this paper, an architecture of TFET considering

the advantages of extended source and a δp + SiGe layer at the
source channel junction is proposed. Study of different elec-
trical parameters have been carried out for different oxide
thickness, oxide material, channel length, different Ge mole
fraction of the SiGe layer, and various structural variation
have taken into account. Section II of this work focuses on
the device architecture, and the section III discusses the out-
comes of the work, and finally section IV presents the
conclusion.
2 Device Structure and Physics
The TFET has been studied with different architectures for
performance improvement. Extended-Source TFET among
all provides an effective improvement on SS and ON-current
because this architecture creates a large contribution to drain
current introducing vertical BTBT. Another architecture [13]
has introduced a SiGe layer at the source-channel junction of a
standard TFET which reduced the barrier width and hence
improved the subthreshold-swing and ON-current. It’s be-
cause SiGe is a low band gap material so it helps to reduce
the tunnelling width only at the source channel junction. In
this paper, a structure with p + source and n + drain containing
the benefit of extended source and incorporation of SiGe layer
at the edge of p + source region is proposed. The structure
shown in Fig. 1(a) has been simulated with 1 × 1020 cm−3
source, 1 × 1018 cm−3 drain, and 1 × 1016 cm−3 intrinsic chan-
nel doping concentration. Drain doping is set less than the
source doping to reduce ambipolar current. The device is
100 nm in length and 40 nm in depth. It can be grown on
insulator, keeping BOX is of 20 nm thickness, and Si layer
can be patterned into mesa structures to define the device area.
An oxidation process has to be carried out for gate oxidation,
after that by chemical vapour deposition method gate material
can be deposited, in the proposed structure oxide thickness is
1 nm, and gate metal used is Aluminum with work function
4.2 eV. After gate is defined by optical lithography process
Source and Drain regions can be implanted, where Source and
Drain regions are 30 nm × 20 nm in area without considering
Fig. 1 (a) Schematic view of proposed TFET structure (b) Band diagram of the proposed structure
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the extended part of the source. For SiGe deposition the area
near source is etched away, and SiGe can be deposited to fill
the gap, here SiGe layer thickness is kept fixed at 1 nm [11, 13,
15].
Figure 1(b) shows the band diagram of the proposed struc-
ture. The band to band tunneling is due to the potential into-
nation provided by the gate field. Because of the application of
the gate voltage the tunneling width gets narrowed and charge
carriers are inserted to the channel via band to band tunneling.
It can be observed from Fig. 1 (b), as the tunneling width is
very narrow and the position of the electron quasi Fermi level
at source causes the tunneling current of 0.01 mA/μm in the
proposed TFET structure.
The structure has been simulated using Sentaurus TCAD.
Fermi-Dirac statistic transport model and doping dependent
mobility model is used for high doping concentration. Band
gap narrowing model is enabled for the reduction of band gap
energy of semiconductor materials. Shockley-Read-Hall
Recombination models and Band to Band tunneling models
are used for accounting the basic operation of TFET [16].
3 Results and Discussion
The linear and logarithmic plot of Drain current (Id) vs. Gate to
Source voltage (Vgs) is shown in Fig.2 where it is plotted for
different drain voltages. In general, the ON state drain current
in TFET is directly proportional to the tunneling probability
expressed in Eq. (1) [17]. It is observed that the ambipolar
current is reduced highly because of the dielectric material
over the source and SiGe layer responsible for reducing the
energy band gap [13]. It can be observed from Fig. 2 that as
drain voltage increases ambipolar current increases, because
the applied drain voltage should be less than the band gap
voltage (Eg/q) of the material [18]. The increase in drain volt-
age towards band gap value opens up the OFF state tunneling
window at channel drain junction, which increases the
ambipolar current [18, 19], but OFF current and ON current
remains almost same.
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Fig. 2 Linear and logarithmic plot of Drain Current vs. Gate to source voltage for different drain voltages

important parameter for low power applications of devices,

pffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffi!
4 2m* E 3=2 g εs so recuperation of SS is necessary. It can be observed from
T ðE Þ ¼ exp −   t ox t s ΔΦ ð1Þ the Fig. 3 (a), the best SS value is observed in the range of
3jejℏ Eg þ ΔΦ εox
4 nm to 7 nm, which is much better than the SS value of TFET
proposed in [14] where SS degraded severely due to reduced
Where control over vertical BTBT, but it is improved with the intro-
e charge of an electron, duction of SiGe layer in the proposed structure. The threshold
m* effective mass of a carrier, voltage is increased by 35% of the minimum value with the
Eg energy band gap of the semiconductor at the junction increase in height, this is because of the increase in surface
where tunneling occurs, potential along with height [22] which can be seen from Fig.
εs dielectric constant of the semiconductor near to the 3(f); the minimum value is obtained at 4–5 nm.
same junction, The ON-OFF current ratio normally specifies the gate con-
εox gate dielectric constant, trol of a device, hence for higher controllable performance of a
ts depth of the device, device higher ON-OFF current ratio is needed. In the pro-
tox thickness of the dielectric, posed structure the ON-OFF current ratio a shows remarkable
ℏ reduced Planks’s constant and performance in the range of 4 nm–7 nm height which is sup-
ΔΦ energy over which tunneling occurs [16]. ported by the band diagram as shown in Fig. 3(e) and the Id-
Vgs plot of Fig. 3(d) that shows a high ON current at 3–5 nm
Equation (1) expresses the relation between tunneling and decreases with the increase in height. As shown in the
probability, energy band gap, oxide thickness, and dielectric band diagram at 4 nm the eQFL (electron quasi Fermi level)
constant. Band gap reduction, increase of dielectric constant, is at a higher position than at 9 nm, which indicates a decrease
and reduction of thickness increases the tunneling probability, in current at the next value. Hence with the decrease in height
thereby resulting in an increase in ON current and reduction of of the SiGe layer, the ON current decreases, which can be seen
SS. The Table 1 shows that, SS, ION, IOFF and ION/IOFF are from Fig. 3(d) also. Transconductance is an important param-
better in the proposed structure when compared to [13, 14], eter in TFET. It is defined as gm = ∂Id/∂Vgs, where Vgs and Id
and [20], except small rise in IOFF than [21]. are gate to source voltage and drain current respectively. It
The height between the channel surface and the extended gives the measure of how drain current changes with change
source is varied to study the effect on various electrical pa- in gate to source voltage. This is a very important parameter
rameters, which are plotted in Fig.3. As SS is the most for circuit designing. The Transconductance of the proposed

Table 1 Comparison of proposed structure results with conventional structures

Proposed structure [13] [14] [20] [21]

SS (mV/decade) 16 22.44 >60 55 >60

ION (A/μm) 0.01 × 10−3 10−5 ~10−6 ~10−8 ~1.22 × 10−6
IOFF (A/μm) 6.48 × 10−17 ~10−12 7.78 × 10−14 6.48 × 10−14 ~1.25 × 10−17
ION/IOFF ~1011 ~107 ~108 ~105 ~ 1010

Fig. 3 (a) SS and Threshold Voltage (b) ON-current (c) ON-OFF current
ratio and Transconductance (d) Id-Vgs plot (e) Energy band diagram (f)
Surface potential from Source to Drain for variation of height between
structure, as shown in Fig. 3(c) degrades with the increase in
height showing that the gate loses its control over the drain
current.
Scaling of devices leads to some fundamental issues such
as higher short channel effects and lower gate controllability.
Hence it is crucial to know the device performance over var-
iation of channel length [23]. The channel length variation for
different electrical parameters is shown in Fig. 4. From Fig.
4(a) it can be observed that in the proposed structure, SS
decreases with decrease in channel length, this is because as
channel length decreases gate capacitance decreases, as it is
directly proportional to channel area. Hence with decrease in
gate capacitance, SS decreases [24]. The threshold voltage
increases with decrease in channel length, which is due to
the reverse short channel effect until the short channel effect
takes over, which may cause because of simulated dopant
distribution [25, 26]. From Fig. 4(b) it can be seen that ON
current variation is very less with channel length scaling,
which can be seen from the Id-Vgs plot of Fig. 4(d) and the
energy band diagram of Fig. 4(e), where eQFL for both 60 nm
and 100 nm are almost at same level, which means occupancy
of carriers in both cases are almost same. This is because of the
improved tunnel junction control by the use of high-k dielec-
tric which improves the gate length scaling trend than with
SiO2 dielectric [27, 28]. Moreover, short channel effects are
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Channel surface and extended source keeping Channel Length of
40 nm,Oxide thickness of 1 nm and HfO2 as gate oxide
negligible in Si TFET [29]. It can be observed from the Fig. 4
(c), the ON-OFF current ratio reduces with the reduction of
channel length, but it is not so severe (values are in order of
1011) in comparison with the existing ES-TFET proposed in
[14]. The introduction of SiGe layer in the proposed structure
keeps the switching ratio less affected for the variation of
channel length below 100 nm also. The variation of
Transconductance with channel length is shown in Fig. 4(c)
where Transconductance reduces with increase in channel
length which is negligible (in order of 10−5).
Mole fraction put an immense control over switching speed
and velocity of carriers by controlling carrier mobility [30].
Here Mole fraction (x) of Si1-xGex layer is varied to study its
effect on various electrical parameters and it is shown in Fig.5.
It is observed that with the increase of mole fraction of Ge, the
availability of electrons on the source side increases, which
leads to increase in ON current moreover, with increase in Ge
content carrier mobility increases and lowers the tunneling
barrier thus by enhancing the ON current [31]. We know,
(ΔEg)SiGe = 0.467x where, x is the germanium mole fraction
[32]. Due to the increase in mole fraction electron affinity
increases and band gap decreases. This leads to an increase
in tunneling probability hence the ON current. At the same
time OFF current also increases. As a result ON-OFF current
ratio doesn’t shows a good improvement with the increase in
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Fig. 4 (a) SS and Threshold Voltage (b) ON-current (c) ON-OFF current ratio and Transconductance (d) Id-Vgs plot (e) Energy band diagram for
variation of Channel Length at an oxide thickness of 1 nm and HfO2 as gate oxide
mole fraction. Hence an optimized value of x is chosen for
better performance. Threshold voltage and SS shows a sharp
increase for increase of mole fraction from 12 mV/decade for
x = 0.3 to 24 mV/decade for x = 0.6 which is ascribed due to
the quantum nature of Band to Band tunneling effect [30]. A
trade off can be seen between SS and ON current with varia-
tion of mole fraction. The variation of Transconductance at
different SiGe mole fraction is very less though it increases at
x = 0.4 but starts decreasing from x = 0.5.
The length of the extended source has significant effect
on the proposed device characteristics. Figure 6 shows the
effect of variation of source extension length on various
electrical parameters. It is seen that SS degrades drastical-
ly for the increase of source extension length, the close-
ness of which towards drain causes overlapping of the
source and the drain depletion region. Threshold voltage
remains constant at 0.38 V showing independence for the
extension of source length. ON-OFF current ratio reduces
with the increase of source extension length though ON
current remains almost constant, which is supported by
the band diagram. In Fig. 6(e), the eQFL for extended
source length of 20 nm and 35 nm are at the same level
but OFF current increases due to the overlapping of
source-drain depletion region, which decreases the ON-
OFF current ratio.
It is observed that, though SS degrades with enhancement
of length, but the Threshold voltage and ON current are almost
constant and OFF current degradation is very less, hence the
proposed device has the consistency to work at low power
applications even at higher extended source lengths.
Transconductance decreases with the increase in extended
source length, showing gate loses control over the channel
current.
Gate dielectric thickness is another important parameter
whose effect is shown in Fig.7. In the proposed structure with
the decrease of oxide thickness, the coupling of the gate with
the semiconductor surface increases resulting in steeper
tunneling profile at the source-channel junction. This leads
to an enhanced control over the barrier width, which results
in a drastic reduction of SS and threshold voltage. The ON-
OFF current ratio increases with oxide thickness, but from the
band diagram it is clear that the tunneling current is more at
1 nm as eQFL is at higher value than that of 4 nm, In addition,
from Eq. (1) it is observed that with decrease in oxide thick-
ness tunneling probability increases hence the ON current as
TFET current is directly proportional to tunneling probability.
As at higher oxide thickness the gate leakage current de-
creases so OFF current shows a decreasing trend at higher
value of thickness. As a result ON-OFF current ratio increases
at higher oxide thickness. It can be observed that, reducing
oxide thickness leads to higher control of gate on tunnelling
current without sacrificing much on leakage current. Hence,
the proposed device has an improved immunity over leakage
current in terms of oxide thickness scaling. Transconductance
shows a gradual drop for the increase in oxide thickness as the
gate control over the channel reduces.
Higher ON-current and decreased subthreshold swing
can be obtained by selecting an effective gate dielectric
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Fig.5 (a) ON-OFF current ratio and Transconductance (b) ON-Current (c) SS and Threshold Voltage (d) Id-Vgs plot. (e) Band diagram for variation of
Ge Mole Fraction at anoxide thickness of 1 nm, Channel Length of 40 nm and HfO2 as gate oxide

Fig. 6 (a) SS and Threshold Voltage (b) ON-Current (c) ON-OFF current ratio and Transconductance (d) Id-Vgs plot (e) Band diagram for variation of
extended source length at an oxide thickness of1nm, Channel Length of 40 nm and HfO2 as gateoxide
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Fig. 7 (a) SS and Transconductance (b) ON-Current (c) Threshold Volage and ON-OFF current ratio (b) Band Diagram (e) Id-Vgs plot for variation of
oxide thickness at a Channel Length = 40 nm and HfO2 as gate oxide

Fig. 8 (a) SS and Threshold Voltage (b) ON-Current (c) ON-OFF current ratio and Transconcuctance (d) Band diagram (e) Id-Vgs plot for variation of
gate dielectric at an oxide thickness of 1 nm and Channel Length of 40 nm

which plays a major role in reducing the effective oxide
thickness. Figure 8 shows the effect of various gate di-
electric such as Silicon dioxide (ɛr = 3.5), Aluminum ox-
ide (ɛr = 10) and Hafnium oxide (ɛr = 22) on various elec-
trical parameters and can be observed that high-k dielec-
tric improves subthreshold swing to a very low value.
ON-current increases and threshold voltage reduces for
high-K dielectric due to improved coupling between the
gate and the surface which reduces barrier width and im-
provement of ON-current uncovers the steeper portion of
the curve resulting in an improvement of subthreshold
swing.
To support this the energy band diagram for HfO2
and SiO2 is shown in Fig. 8(e), where it can be ob-
served that the eQFL for HfO2 is at higher position than
the later one hence a higher ON current in case of
HfO2. In addition, from Eq. (1) it is observed that with
increase in oxide permittivity tunnelling probability in-
creases thus increasing the ON current. The Id-Vgs plot
also shows a better ON current in case of HfO2, indi-
cating that the proposed structure of TFET has a great
potential to be competitive with other steep slope and
high switching ratio devices for low voltage application.
4 Conclusion
In this paper, a novel TFET structure having extended
source with SiGe pocket layer at the edge of source
channel junction is proposed. The proposed device has
been simulated with respect to various scaling parame-
ters and observed remarkable ON-current of 0.01 mA/
μm, OFF-current (neglecting gate leakage) of 6.48 ×
10−17 A/μm for 1 V gate and drain voltage, SS of
16 mV/decade and ON-OFF current ratio of more than
1011 for a threshold voltage of 0.4 V is obtained. The
simulation results also show a remarkable performance
over standard TFET. We have successfully shown that
the proposed device maintains absolute scalability ac-
cording to ITRS over a wide range of channel length.
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