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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2019.2937039, IEEE
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Impedance Modeling and DC Bus Voltage
Stability Assessment of a Solid-State-
Transformer (SST) Enabled Hybrid AC/DC
Grid Considering Bidirectional Power Flow
Qing Ye, Member, IEEE, Ran Mo, Member, IEEE,
and Hui Li, Fellow, IEEE,
 decades. Various research works have been or currently are
Abstract—The solid-state-transformer (SST) is a
promising technology in the future smart grid. Compared
to the line-frequency transformer, the SST has more
control flexibilities and the plug & play ability, which allow
it to interconnect a hybrid ac/dc multi-terminal grid for
reliable and flexible power distribution. The dc bus voltage
stability of an SST-enabled hybrid ac/dc multi-terminal
grid is a critical issue due to the dynamic interactions of
power converters, which has been investigated in this
paper. The output impedance modeling method of the dual
active bridge (DAB) dc/dc converters considering both the
control schemes and bidirectional power flow effect is
proposed. Depending on the control strategy and power
flow direction, the DAB converters have three different
output impedance characteristics at the low frequency
range, which are capacitive, inductive, and resistive. It is
found that the dynamic interaction between the inductive
impedance and the capacitive impedance of DAB
converters could cause instability issue when system
damping ratio is low. A hardware-in-the-loop based
impedance measurement testbed is used to extract DAB
converters’ output impedance, which validates the
theoretical derivation. Real-time simulation results are
also provided to demonstrate the dc bus voltage
instability.
Index Terms—Solid-state-transformer, Hybrid ac/dc
grids, bidirectional power flow, impedance modeling,
stability assessment
I. INTRODUCTION
T he solid-state-transformer (SST) technology has
undergone a rapid development during the past two
Manuscript received December 21, 2018; revised March 30, 2019
and June 16, 2019; accepted August 8, 2019. This work was
supported by National Science Foundation under Grant Award ECC-
0812121. (corresponding author: Hui Li).
Q. Ye is with the Toshiba International Corporation, Houston, Texas
77041 USA (email: Qing.Ye@toshiba.com).
R. Mo is with the ABB Enterprise Software, Sugarland, Texas 77478
USA (email: Ran.Mo2@us.abb.com)
H. Li is with the Department of Electrical and Computer Engineering,
Florida State University, Tallahassee, FL 32306 USA (e-mail:
hli@caps.fsu.edu).
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conducted to develop the SST technology as a building block
for the future smart grid owing to the superiorities of the
SSTs, such as power factor correction, voltage-sag ride-
through and harmonic elimination [1]-[5]. These advantages
of SSTs are not available from the line-frequency transformer.
Moreover, the SST can serve as an energy router, which
provides interfaces for the integration of distributed renewable
energy resources (DRERs) and distributed energy storage
devices (DESDs) [6]. The multiple terminals of the SST with
above features allow it to construct hybrid ac/dc grids for
more flexible and reliable power distribution [7]-[8].
The concept of hybrid ac/dc grids was proposed to combine
the benefits of both ac and dc grids. It also helps reduce the
system loss by avoiding multiple power conversion stages and
thereby increases the system reliability [9]-[13]. By far, most
published hybrid system structures are utilizing a voltage
source converter (VSC) [14] or a back-to-back converter [15]
to interconnect the ac and dc subsystems. The stability of a
hybrid ac/dc system has been analyzed using a dq frame
modeling method in [16], where the constant power load
(CPL) feature of power electronics driven loads is addressed.
The dc bus voltage stability of a droop-controlled multiple-
source multiple load system has been discussed by means of
impedance based modeling method in [17]. The impedance
based method has also been used to address the common dc-
link instability of a hybrid ac/dc grid caused by the negative
incremental admittances of interconnecting VSCs [18].
Recently, a hybrid ac/dc multi-terminal grid enabled by the
SST is proposed which is shown in Fig. 1 [1]. The SST
interacts with three sub-grids which are the legacy grid, a dc
microgrid and an ac microgrid. Each sub-grid has the
bidirectional power flow capability and exchanges power
through the common dc bus. Therefore, it is essential to
guarantee the dc bus voltage stability.
Dual-active-bridge (DAB) dc/dc converter is the core of the
SST. It regulates its output dc bus voltage to integrate the dc
microgrid and the rear-end inverter with bidirectional power
flow capability [19]-[20]. The output terminal characteristic
of the DAB_SST converter is different from that of a VSC or a
back-to-back converter due to its control scheme and topology
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Fig. 1. An SST-enabled hybrid ac/dc multi-terminal grid.
[16], [21]. Meanwhile, the DAB converter is also used to
integrate DESDs in the dc microgrid where the input-side
current control function of DAB_DESD converter is required.
The DAB_DESD converter is able to shift from input current
control mode to droop control mode autonomously depending
on system power management, which poses a challenge on
maintaining the dc bus voltage stability. Thus, the impedance
modeling of the DAB converter with consideration of both
bidirectional power flow effect and various control strategies
needs to be analyzed. In [22]-[23], the DAB converter output
impedance has been derived, but the bidirectional power flow
effect has not been considered. The bidirectional power flow
effect on an output-voltage-controlled DAB converter has
been analyzed in [21], [24]-[26]. However, how the terminal
impedance of a DAB converter varies, depending on
employed control schemes, has not been analyzed.
To address the aforementioned challenges, the impedance
modeling method of DAB converters is conducted in Section
II. The effect of control schemes and bidirectional power flow
on DAB converters’ output impedances are thoroughly
researched. In Section III, the dc bus stability analysis is
performed under four power flow cases. The theoretical
analysis demonstrates that when DAB_DESD and DAB_SST
are both operating in droop control, they will exhibit inductive
and capacitive output impedance characteristics below 10 Hz,
respectively. Therefore, in this case, the dynamic interaction
between DAB_DESD and DAB_SST could cause dc bus
voltage oscillations. An OPAL-RT based hardware-in-the-
loop testbed is built to validate the theoretical analysis in
Section IV. Finally, this paper is concluded in Section V.
II. IMPEDANCE MODELING OF DAB CONVERTERS IN
BIDIRECTIONAL POWER FLOW CONDITIONS
A. System Description and Control Schemes
The system diagram and control schemes of an SST-
enabled hybrid ac/dc grid are shown in Fig. 2. Since the dc
bus voltage stability is of interest, the legacy grid and ac
microgrid are both treated as energy clusters which inject/
absorb power to/from the dc bus. The legacy grid is connected
to the dc bus through a front-end rectifier and a DAB_SST
converter. The front-end rectifier is decoupled from the
DAB_SST converter due to the large dc-link capacitor, so it has
negligible effect on the dc bus voltage stability [27]. The
DAB_SST converter utilizes multiple control loops to regulate
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Fig. 2. System diagram and control schemes of the SST-enabled
hybrid ac/dc grid.
Fig. 3. The DAB converter small signal model.
the dc bus voltage including a droop control loop, an output
voltage control loop, and an inner current control loop. The ac
microgrid is formed by controlling the output voltage of the
rear-end inverter. In the dc microgrid, there are a dc load and a
DESD, which both can be considered as an aggregation of
multiple dc loads and DESDs, respectively. The DRER is
always controlled to be a power source which helps stabilize
the system [25], so it is neglected here in order to investigate
the worst case. The DAB_DESD converter is either in the droop
control mode to regulate dc bus voltage coordinately with
DAB_SST converter or in the current control mode,
charging/discharging at its maximum value to meet the system
power demand [28]. Different from DAB_SST having its output
side dc current feedback in the inner current control loop, the
DAB_DESD current control loop needs to regulate the input side
dc current at battery side. The load buck converter steps down
the dc bus voltage to feed the loads. To study the dc bus
stability, the dc output impedances of all connected power
converters need to be derived with consideration of both
control schemes and power flow direction.
B. Impedance Derivation of DAB Converters
The small-signal model of a DAB converter is shown in
Fig. 3. 𝑣 and 𝑣 are the side and secondary-side voltage,
respectively. 𝚤̂ and 𝚤̂ are the primary-side and secondary-
side current, respectively. 𝑑 is the phase shift duty ratio. These
mathematical terms with hats are small-signal variables. The
coefficient terms are derived as follows,
𝑇(1 − 2|𝐷|)𝑉 𝑇𝐷(1 − |𝐷|)
𝑔 = ,𝑔 = ,
𝑛𝐿 𝑛𝐿
( | |) ( | |)
𝑔 = ,𝑔 = , (1)
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(a)

(b)

(c)
Fig. 4. Control diagram of (a) DAB_SST converter, (b) DAB_DESD converter in constant current control, and (c) DAB_DESD converter in droop
control.
where 𝐿 is the transformer leakage inductance, 𝑛 is the respectively. 𝑣 and 𝑣 ∗ are the DAB_SST converter output
transformer turns ratio, 𝑉 is DAB converter primary side voltage reference value and nominal value of DC bus voltage
voltage and 𝑉 is DAB converter secondary side voltage. The respectively.
single-phase-shift (SPS) modulation is adopted for the DAB The control diagram of the DAB_DESD converter in constant
converters. The phase shift duty ratio 𝐷 is defined as the phase current control is depicted in Fig. 4(b). In this control mode,
shift angle between the primary H-bridge square-wave the DAB_DESD converter is treated as a current source while the
modulation signal and Secondary H-bridge square-wave dc bus voltage is regulated by the DAB_SST converter. Its
modulation signal. output admittance is expressed as
With the derived DAB converter small signal model, the 𝑌 = , (3)
control diagrams of the DAB converters are illustrated in Fig.
4. For the DAB_SST converter, its control system is composed 𝐴= ,𝐵 = , (4)
sC sC
of a droop control loop, an outer voltage control loop and an 𝐸= ,𝐹 = , (5)
inner current control loop as illustrated in Fig. 4(a). It is worth sC
∗
mentioning that the values of state variables 𝑖 (𝑠) and 𝑖 (𝑠) where 𝑖 and 𝑖 are the battery discharging current and battery
are defined to be positive in the forward power flow and to be discharging current reference value, respectively; 𝐴, 𝐵, 𝐸, and
negative with the reverse power flow. Consequently, the 𝐹 are symbolic mathematical term to present the derived
control block diagram remains the same with the bidirectional impedance concisely.
power flow, so does the format of the DAB_SST converter When the DAB_DESD converter is in the droop control mode,
output impedance. The DAB_SST converter output impedance the dc bus voltage is regulated by both the DAB_SST converter
is given in (2), where 𝐺 and 𝐺 are the voltage and current and the DAB_DESD converter. Hence, the DAB_DESD converter
controller respectively, 𝑟 is the droop coefficient of the is modeled as a voltage source. In this case, the control
DAB_SST converter, 𝑇 is the sampling period, 𝐺 is the control diagram of the DAB_DESD converter is shown in Fig. 4(c), and
delay, 𝐻 and 𝐻 are the feedback coefficients, its output impedance is derived in (6), where 𝑟 is the droop

𝑍 _ = , (2)

𝑍 _
= , (6)
( )/( )

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(a)
Fig. 5. Frequency response of (a) DAB_SST converter output impedance, (b) DAB_DESD converter output admittance in constant current control,
and (c) DAB_DESD converter output impedance in droop control.
coefficient of the DAB_DESD converter; 𝐴 and 𝐵 have been
defined in (4).
The circuit and control parameters of DAB_SST converters
are given in the Appendix, and parameter tuning method can
be found in [29]-[30]. The frequency responses of the
DAB_SST converter output impedances are shown in Fig. 5(a),
which are the same when the DAB_SST converter injects or
absorbs 20 kW power. This can be explained by notifying that
the derived impedance in (2) only contains the term of 𝑔 .
This term is insensitive to the sign of 𝐷, so the converter
output impedance does not change if the total delivered power
remains the same. It is noted that when the frequency is
greater than 10 Hz, the impedance magnitude is descending at
20 dB/decade and its phase is around -900. This dominant
capacitive impedance characteristic ensures that the system
has high stability robustness beyond this frequency range. In
contrast, the frequency response of the DAB_SST converter
output impedance below 10 Hz mainly depends on the adopted
control mode, which can interact with other converters and
cause stability issues.
The circuit and control parameters of DAB_DESD converter
are also listed in the Appendix. The terminal behaviors of the
DAB_DESD converter are derived at its nominal power rating of
3 kW. When the DAB_DESD converter operates in the constant
current control mode, it exhibits a positive resistive impedance
when generating power but a negative one when absorbing
power at low frequency range below 10 Hz, as shown in Fig.
5(b). Therefore, it stabilizes system due to the constant power
source (CPS) feature when generating power but destabilizes
system by introducing a CPL feature when absorbing power.
While at the high frequency range beyond 30 Hz, the
impedance characteristics are consistent regardless of the
power flow direction, since they are mainly dependent on the
output capacitor. However, this is not the case when the
DAB_DESD converter works in the droop control. As shown in
Fig. 5(c), the output impedance of the DAB_DESD converter
under the bidirectional power flow are nearly the same. It
exhibits an inductive impedance feature below 100 Hz, then
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(b) (c)
gradually turns to capacitive impedance as frequency
increases. The slight difference under bidirectional power flow
is caused by the terms 𝑔 in (6). As given in (1), this term is
sensitive to the sign of 𝐷, i.e. the power flow direction.
However, since the mathematical terms associated with 𝑔 is
negligible, it has trivial effect on the output impedance.
The output impedance derivations of the buck load
converter and the rear-end inverter have been addressed in
[21] and [27], respectively. The load converter exhibits a CPL
feature, implying that a negative resistive impedance at low
frequency; The rear-end inverter shows a CPL feature when
power flows through the dc bus to the ac microgrid, but a CPS
feature when power flows from the ac microgrid to the dc bus.
C. System Impedance Model and Stability Analysis
Method
The system impedance model can be derived based on the
system control scheme, as depicted in Fig. 6. The DAB_SST
converter is modeled as a voltage source in series with its
output impedance, and the load buck converter is represented
by a current sink in parallel with its output admittance. The
DAB_DESD converter is modeled as a Norton circuit in droop
control mode and a Thevenin circuit in constant current
control mode. It is worth mentioning that although they are
alternative representation to each from the circuit point of
view, they cannot be treated equivalently when investigating
stability issues [31]. Therefore, there are two system
impedance models corresponding to two different control
schemes of the DAB_DESD converter. The system impedance
model is further simplified by combining all the Norton type
equivalent circuits together as shown Fig. 7. Therefore, the
stability metrics can be derived for the dc bus stability voltage
assessment.
When DAB_DESD converter operating in the constant current
control, the dc bus voltage is derived as
𝑣 = _
, (7)
_
𝑖 =𝑖 −𝑖 −𝑖 ,𝑌 =𝑌 +𝑌 +𝑌 . (8)
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(a)
Fig. 7. Combined system impedance model when (a) DAB_DESD converter in constant current control, and (b) DAB_DESD converter in droop
control.
Assuming that each unit connected to the dc bus is stable
locally, the term 𝑍 _ ∙ 𝑌 can be treated as a global
minor loop gain (GMLG), and the system is stable if and only
if the Nyquist plot of GMLG does not encircle the point of (-
1,j0) [32]-[33].
When the DAB_DESD converter operates in the droop
control, the dc bus voltage is derived as
_ _
𝑣 =
_ _ _ (9)
𝑖 = −𝑖 − 𝑖 ,𝑌 =𝑌 +𝑌 . (10)
It is noted that due to the control mode transition, the
impedance factor determining the dc bus voltage stability is
different from (1). Under the same assumption that the local
stability of each unit is guaranteed, the numerator of the right
term in (3) can be neglected when analyzing the dc bus
voltage stability. In other words, the dc bus voltage stability is
merely determined by the denominator. Thus, this
denominator can be defined as the unified stability metric
(USM), which is no longer organized in the one plus
impedance ratio type. In this case, the right-half-plane zeros
(RHZ) in the output impedance of the output-voltage-
controlled converters could be overlooked and result in
stability assessment failure. To address this issue, the
improved impedance ratio type criterion from [34] and
multiple loops stability analysis method from [35] are
proposed, which are not computationally efficient due to two
step calculations. The sum type criterion is one step
calculation, but not applicable when the stability margin in
classic control theory is required [34]. Since the RHZ of the
USM will result in stability issues, the pole-zero map of USM
is used here to analyze DC microgrid stability. The damping
ratio determined by the dominant zeros of USM can be treated
as the stability margin.
III. STABILITY ASSESSMENT OF THE SST-ENABLED HYBRID
AC/DC GRID
All the three sub-grids in the SST-enabled hybrid ac/dc grid
have the bidirectional power flow capability, thus, there are
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Fig. 6. General system impedance model.
(b)
more than one power flow possibility. As derived in Section
II, the output impedance characteristics of the power
converters are related to the power flow direction. Therefore,
it is necessary to find out all possible power flow scenarios to
address the dc bus voltage stability systematically. Given the
coordinated control strategy of DAB_SST converter and
DAB_DESD converter [27]-[28], [36], there are four power flow
_ _ possibilities in total, as depicted in Fig. 8. Correspondingly,
,
_ four power flow cases are created to evaluate and compare the
dc bus voltage stabilities, as follows:
Case 1: 𝑃 = 20 𝑘𝑊, 𝑃 = −5 𝑘𝑊,
𝑃 =𝑃 −𝑃 = 3 𝑘𝑊 − 18 𝑘𝑊 = −15 𝑘𝑊 .
Case 2: 𝑃 = 20 𝑘𝑊, 𝑃 = −22 𝑘𝑊,
𝑃 =𝑃 −𝑃 = 3 𝑘𝑊 − 1 𝑘𝑊 = 2 𝑘𝑊.
Case 3: 𝑃 = 20 𝑘𝑊, 𝑃 = 5 𝑘𝑊,
𝑃 =𝑃 −𝑃 = 3 𝑘𝑊 − 28 𝑘𝑊 = −25 𝑘𝑊.
Case 4: 𝑃 = − 20 𝑘𝑊 𝑃 = 24𝑘𝑊,
𝑃 =𝑃 −𝑃 = −3 𝑘𝑊 − 1 𝑘𝑊 = −4 𝑘𝑊.
𝑃 is defined to be positive if the power flows into the
common dc bus from one of the three sub-grids, while to be
negative if the power flows out from the common dc bus to
the sub-grids.
The global minor loop gain (GMLG) and unified stability
metric (USM) are used to assess the system stability when
DESD operates in current control and droop control,
respectively. The dc bus voltage stability analysis results of
above four cases are depicted in Fig. 9. In case 1, when the
DAB_DESD converter operates in the constant current control, it
has a resistive output impedance. The Nyquist plot of the
GMLG is given in Fig. 9(a) where the critical point (-1, j0) is
not encircled by the trajectory. Thus, the system is stable with
over 6 dB gain margin. However, when the DAB_DESD
converter operates in the droop control, it exhibits an inductive
output impedance below 10 Hz as shown in Fig. 5(c). This
inductive terminal feature of DAB_DESD could resonant with
the capacitive output impedance of DAB_SST. The dominant
zeros of the USM, shown in Fig. 9(b), has a small damping
ratio of 0.198. Such a small damping ratio cannot mitigate the
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(a) (b)

(c) (d)
Fig. 8. Power flow possibilities of the SST-enabled hybrid ac/dc microgrid.
(a) 𝑃 > 0, 𝑃 < 0, 𝑃 < 0. (b) 𝑃 > 0, 𝑃 > 0, 𝑃 < 0.
(c) 𝑃 > 0, 𝑃 < 0, 𝑃 > 0. (d) 𝑃 < 0, 𝑃 < 0, 𝑃 > 0.

(a) (b) (c) (d)

(e) (f) (g) (h)

Fig. 9. DC bus voltage stability analysis when (a) case 1: constant current control, (b) case 1: droop control, (c) case 2:
constant current control, (d) case 2: droop control, (e) case 3: constant current control, (f) case 3: droop control, (g) case 4: constant
current control, (h) case 4: droop control.

CPL effects of the dc load converter and the rear-end inverter.
Therefore, the system is prone to instability when the
DAB_DESD converter operates in the droop control in case 1.
Similar conclusions can also be drawn for the case 2 and 3 as
illustrated in Fig. 9(c)-(f). The system damping ratios in case 2
and case 3 are 0.194 and 0.208, respectively, when the
DAB_DESD converter operates in the droop control. However,
in case 4, the system has a much higher damping ratio of
0.538 when the DAB_DESD converter operates in the droop
control, as depicted in Fig. 9(h). This is because the rear-end
inverter reveals a large positive incremental impedance while
sinking 24 kW power, which compensates the CPL effect of
the DC load converter. Meanwhile, a large portion of power is
delivered to the legacy grid through the DAB_SST converter,
which does not introduce any negative incremental impedance
during the reversed power flow. The same trend has been
observed in Fig. 9(g) where the system gain margin in case 4
is greater than those in the other three cases when the
DAB_DESD converter is in constant current control. Therefore,
the system should be stable in case 4 regardless of DAB_DESD
converter control schemes.
IV. HARDWARE-IN-THE-LOOP VERIFICATION
A hardware-in-the-loop (HIL) testbed consisting of an
OPAL-RT real-time simulator (RTS) and an impedance
measurement unit is used to verify the theoretical analysis
[37]-[40]. The HIL setup is depicted in Fig. 10. The RTS

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accuracy. The output impedance of the DAB_SST converter in

Fig. 10. Hardware-in-the-loop setup.
executes the system model and transfers the simulated data to
OP5607 I/O expansion unit. An Agilent E5061B network
analyzer is used as an online impedance measurement unit,
which sends injection signals to RTS and receives perturbed
signals through the I/O expansion unit. The controllers are
discretized in the RTS in order to be consistent with the digital
controllers implemented in reality. The OPAL-RT simulation
step is 500ns. The sampling and control frequency for each
converter is the same with its switching frequency given in
Appendix. The digital system control delay is also modeled
using third-order Padé approximation.
The HIL impedance measurements are conducted for the
DAB converters. The sweeping frequency range is from 5 Hz
to 1.1 kHz with 501 measurement points to guarantee the
both forward power flow (P=20 kW) and reverse power flow
(P=-20 kW) are depicted in Fig. 11 (a) and (b) respectively.
They are almost identical to each other. The impedance
characteristic of the DAB_SST converter at the resonance
frequency is inductive. The output impedances of the
DAB_DESD converter in the droop control are shown in Fig. 11
(e) and (f), respectively, which have trivial difference. The
impedance characteristic of the DAB_DESD converter at the
resonance frequency is inductive. The output admittance of the
DAB_DESD converter in the constant current control differs
under bidirectional power flow conditions. When it is
operating in the forward power flow condition, the phase of
measured output admittance at 5 Hz is close to 0o in Fig.
11(c), meaning that the DAB_DESD converter reveals a positive
resistive impedance characteristic. Yet, in the reverse power
flow condition, the DAB_DESD converter has a negative
resistive impedance since the measured phase at 5 Hz is close
to 180o in Fig. 11(d). The HIL measurement results are
consistent with theoretical analysis results in Fig. 5.
The real-time simulation results of the four power flow
cases in Section III are depicted in Fig. 12. In case 1, the
system is stable when the DAB_DESD converter is in the
constant current control as shown in Fig. 12(a). The DC bus
voltage 𝑣 is 395V plus a negligible double line frequency
component. 𝑣 is less than its nominal value of 400 V
because the DAB_SST converter is sending power to meet load

(a) (b) (c)

(d) (e) (f)

Fig. 11. HIL impedance measurement results: (a) DAB_SST converter output impedance (P=20 kW), (b) DAB_SST converter output impedance
(P=-20 kW), (c) DAB_DESD converter output admittance in constant current control (P=3 kW), (d) DAB _DESD converter output admittance in
constant current control (P=-3 kW), (e) DAB_DESD converter output impedance in droop control mode (P=3 kW), and (f) DAB_DESD converter
output impedance in droop control mode (P=-3 kW).

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(a) (b) (c)

(d) (e) (f)

(g) (h)
Fig. 12. OPAL-RT real-time simulation results: (a) Case1: DAB_DESD converter in constant current control, (b) Case1: DAB_DESD converter in
droop control, (c) Case2: DAB_DESD converter in constant current control, (d) Case2: DAB_DESD converter in droop control, (e) Case3:
DAB_DESD converter in constant current control, (f) Case3: DAB_DESD converter in droop control, (g) Case4: DAB_DESD converter in constant
current control, and (h) Case4: DAB_DESD converter in droop control.
demand. The small signal instability occurs when the and Fig. 12(h). In this case, system is stable regardless of the
DAB_DESD converter operates in the droop control, as depicted DAB_DESD converter control mode because the damping ratio
in Fig. 12(b). The dc bus voltage is oscillating at around 8 Hz is high enough to compensate the constant power load effect,
with a 175 V peak-to-peak amplitude, and the battery output as indicated in Fig. 9 (g) and Fig. 9(h). The real-time
current 𝑖 is also oscillating with the same frequency. This simulation results are consistent with the theoretical analysis.
low frequency current ripple would degrade battery life or
even cause damages [41]. The dc load converter and rear-end V. CONCLUSION
inverter are tightly regulated. Hence, the 8 Hz oscillations In this paper, the dc bus voltage stability of an SST-
observed in their output voltage envelopes are trivial. The enabled hybrid ac/dc multi-terminal grid has been discussed.
same phenomena are observed in cases 2 and 3 where the The impedance model of the DAB converters has been
system is unstable with low frequency oscillations in Fig. developed considering both bidirectional power flow effect
12(d) and Fig. 12(f). Due to the slight differences of the and control strategies. It has been demonstrated that the
damping ratios and oscillating frequencies indicated in Fig. DAB_SST converter has the same output impedance under
9(b), (d) and (f), the peak-to-peak oscillation amplitude and
bidirectional power flow, provided that the power transferred
oscillation frequency of the 𝑣 and 𝑖 are not exactly the
is the same. The low frequency terminal behavior of the
same. The waveforms of case 4 are shown in the Fig. 12(g)
DAB_SST converter is found to be capacitive. For the

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