CMOS-Design-Flow

CMOS Design Flow : Figure below shows the CMOS IC design flow, it consists of defining
circuit inputs and outputs also called as specifications of the circuit. Once the detailed list of
inputs and outputs is developed from this the design calculations are performed and the circuit
schematic for the intended integrated circuit is designed. This developed schematic is then drawn
in CAD (Computer Aided Design) tools e.g. Tanner. Once the schematic entry is finished then
the circuit simulations are carried out and the obtained simulation results are checked with the
intended specifications this step is called as pre-layout simulation. After checking post layout
simulation results, the next step is the fabrication of the prototype board. Once the fabricated
board comes the testing of the protype is carried out and the initial specifications are checked, if
these results are not matched with the intended specifications then there are two possibilities of
error that may be either because of fabrication or initial specification problem. If the prototype
board passed all the tests then it is given for mass production. This flow is used for custom IC
design. A custom designed IC is also called as ASIC (Application Specific Integrated Circuit).
Other noncustom methods of designing chips includes FPGA (Field Programmable Gate Arrays)
and standard cell libraries. The FPGA and standard cell approach is used when low volume and
quick design turnaround are important. Most of the chips that are mass produced such as
microprocessors and memories are manufactured using the custom design approach shown in
Figure.
 Fig-CMOS-Design-Flow
CMOS lambda Design Rules
CMOS 'λ' Design Rules :
The MOSIS stands for MOS Implementation Service is the IC fabrication service available to
universities for layout, simulation, and test the completed designs. The MOSIS rules are scalable
λ rules.
The MOSIS design rules are as follows :
(1) Rules for N-well as shown in Figure below.
1. Minimum width = 10λ
2. Wells at same potential with spacing = 6λ
3. Wells at same potential = 0λ
4. Wells of different type, spacing = 8λ

(2) Rules for Active area shown in Figure below.

1. Minimum width = 3λ
2. Minimum spacing = 3λ
3. Source/Drain active to well edge = 5λ
4. Substrate/well contact active to well edge = 3λ

3) Rules for poly 1 as shown in Figure below.

1. Minimum width = 2λ
2. Minimum spacing = 2λ
3. Minimum gate extension of active = 2λ
4. Minimum field poly to active = 1λ
(4) Rules for contact to poly 1 as shown in Figure below.

1. 2 λExact contact size = 2 λ

2. Minimum poly 1 overlap = 1 λ
3. Minimum contact spacing = 2 λ

(5) Rules for contact to active as shown in Figure below. 1. 2λExact contact size = 2λ 2.
Minimum active overlap = 1λ 3. Minimum contact spacing = 2λ 4. Minimum spacing to gate of
transistor = 2λ
(6) Rules for metal 1 as shown in Figure below.
1. Minimum width = 3λ
2. Minimum spacing = 3λ
3. Minimum overlap of poly contact = 1λ
4. Minimum overlap of active contact = 1λ

(7) Rules for via 1 as shown in Figure below.

1. λMinimum size = 2λ
2. Minimum spacing = 3λ
3. Minimum overlap by metal 1 = 1λ
(8) Rules for metal 2 as shown in Figure below.
1. Minimum size = 3λ
2. Minimum spacing = 4λ

(9) Rules for metal 3 as shown in Figure below.

1. Minimum width = 6λ
2. Minimum spacing = 4λ

CMOS-Layout-Design
Design Rule Check :
In order to ensure that none of the design rules are violated CAD tools named Design Rule
Checking (DRC) is used. If DRC is not verified then it leads to the non functional design.
The layout rules are grouped in three categories that are transistor rules, contact and via rules and
well and substrate contact rules.
Transistor rules :
The transistor can be created by overlapping the the active and mpolysilicon
m polysilicon layers. The
minimum length of transistor equals 0.24 which is minimum width of polysilicon, wh
whereas the
width of the m which is the minimum width of active layer.transistor
layer. transistor is atleast 0.3
Figure below shows the layout of PMOS transistor.

Fig1-Design
Design-Rule-Check
Contact and Via rules :
A contact forms an interconnection between metal and active or polysilicon layer whereas via
forms an interconnection between two metal lines. A contact or via is formed by overlapping the
two interconnecting layers and provides a contact hole filled with metal between the two.
Figure below shows the contacts and via used in layout.

Fig1-Design
Design-Rule-Check
Well and substrate contact rules :
For digital circuit design it is important for the well and substrate regions to be connected to the
supply voltages. If this is not done then a resistive path is created between the substrate contact
of the transistors and the supply rails which leads to parasitic effects such as latch up.
CMOS-Layout-Design
Inverter Layout :
The schematic diagram of the inverter is as shown in Figure.

Fig1-Inverter-Layout
The stick diagram of the schematic shown in Figure.

Fig2-Inverter-Layout
Here, the most important point to note is that as we change the placing of the components in the
schematic the stick diagram and hence, the layout of the circuit will change accordingly. For
example, if we place the components vertically the stick diagram will be vertical and if we place
the components horizontally the stick diagram will be horizontal. Figure below shows the
physical layout of inverter which is drawn in tanner tool.
 Fig2-Inverter-Layout
Lambda-based-design-rules
Lambda based design rules :
The Mead-conway approach is to characterize the process with a single scalable parameter called
lambda, that is process-dependent and is defined as the maximum distance by which a
geometrical feature on any one layer can stray from another feature, due to overetching,
misalignment, distortion, over or under exposure etc. with a suitable safety factor included.
The purpose of defining lambda properly is to make the design itself independent of both process
and fabrication and to allow the design to be rescaled at a future date when the fabrication
tolerances are shrunk.
Scaling Theory :
The Scaling theory deals with the shrinking transistor and directs the behaviour of a device when
its dimensions are reduced.
The most commonly used scaling models are the constant field scaling and constant voltage
scaling. And another model for scaling the combination of constant field and constant voltage
scaling. The scaling parameter s is the prefactor by which dimensions are reduced. It is s < 1.
(1) The scaling factors used are, 1/s and 1/
(2) is used for supply voltage VDD and gate oxide thickness . 1/s
(3) 1/s is used for linear dimensions of chip surface.
(4) = 1 are used. = s and  For the constant field model and the constant voltage model,
Layout Design Rules :
The layout design rules provide a set of guidelines for constructing the various masks needed in
the fabrication of integrated circuits. Design rules are consisting of the minimum width and
minimum spacing requirements between objects on the different layers.
The most important parameter used in design rules is the minimum line width. This parameter
indicates the mask dimensions of the semiconductor material layers. Layout design rules are used
to translate a circuit concept into an actual geometry in silicon.
The design rules is the media between circuit engineer and the IC fabrication engineer. The
Circuit designers requires smaller designs with high performance and high circuit density
whereas the IC fabrication engineer requires high yield process.
Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred to
the semiconductor material. For the minimum dimension design rules differ from company to
company and from process to process.
To address this issue scalable design rule approach is used. In this approach rules are defined as a
function of single parameter called ' is set to a value and the design dimensions'. For an IC
process '' are converted in the form of numbers. Typically a minimum line width of a '
equalsm process technology ' e.g. for a 0.25 process is set to 2 m.0.125
Layered Representation of Layout :
The layer representation of layout converts the masks used in CMOS into a simple layout levels
that are easier to visualise by the designers. The CMOS design layouts are based on following
components :
(1) Substrates or Wells : These wells are p type for NMOS devices and n type for PMOS
devices.
(2) Diffusion regions : At these regions the transistors are formed and also called as active layer.
These are defined by n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers : These are used to form the gate electrodes of the transistors.
(4) Metal interconnects layers : These are used to form the power supply and ground rails as well
as input and output rails.
(5) Contact and Via layers : These are used to form the inter layer connections.
CMOS-Layout-Design
Layout of Logic gates:
Three Input NAND Gate :
Figure below shows, the schematic, stick diagram and layout of three input NAND gate.

Two Input NAND Gate :

Figure below shows the schematic, stick diagram and layout of two input NAND gate
implemented using complementary CMOS logic.
Two Input NOR Gate :
Figure below shows the schematic, stick diagram and layout of two input NOR gate
implemented using complementary CMOS logic.
Transmission Gate :
Figure below shows the schematic, stick diagram and layout of the transmission gate.
Micron-Design-Rules
) Design Rules :Micron ( Industry uses the micron design rules and code designs in terms of
these micron dimensions. The micron design rules are as follows :
(1) Rules for N-well as shown in Figure below.
1. Width = 3
2. Space = 9

2) Rules for active area as shown in Figure below.

1. Minimum size = 3
2. Minimum spacing = 3
2. N+ active to N-well = 7

(3) Rules for poly 1 as shown in Figure below.

1. Width = 2
2. Spacing = 3
3. Gate overlap of active = 2
4. Field poly 1 to active = 1

(4) Rules for contact to poly 1 as shown in Figure below.

1.  2 Exact contact size = 2
2. Minimum poly overlap = 1
3. Minimum contact spacing = 2
(5) Rules for contact to active as shown in Figure below.
1.  2 Exact contact size = 2
2. Minimum active overlap = 1
3. Minimum contact spacing = 2
4. Minimum spacing to gate = 2

(6) Rules for metal 1 as shown in Figure below.

1. Width = 3
2. Spacing = 3
3. Overlap of contact = 1
4. Overlap of via = 2
(7) Rules for metal 2 as shown in Figure below.
1. Width = 3
2. Space = 3
3. Metal 2 overlap of via = 2

Technology Scaling
Scaling :
In order to build the high performance CMOS circuits certain electrical design rules are taken
into account. These rules are used to develop the mathematical model of the physical
phenomenon occurring in the circuits.
As the current CMOS fabrication processes are improved and the device dimensions are
shrinking these design rules will change.

Hence as the device dimensions are changing the electrical parameters of the devices are also
has to be scaled accordingly to apply the previously developed models to the current modern
devices and circuits.
 In scaling of the MOS devices the characteristics of the device are maintained and the basic
operational characteristics are . Efforts are under waypreserved by introducing a dimensionless
factor to make transistors as small as possible to increase speed and circuit complexity per unit
of chip area.

For this purpose, we have to adjust a fabrication process and the bias voltage to allow proper
operation of reduced size devices. The adjustments aim at achieving small dimension, at the
same time, avoiding several side effects, such as the smaller dimension effects. Such a shrinking
of device without side effects is called as scaling.
Advantages of Scaling :
The reduction in lateral dimensions of the MOSFET and interconnects size is known as 'scaling'
of the geometric dimensions of the MOSFET.
The advantages of Scaling are as follows,
(1) Improved current driving capability improves the device characteristics.
(2) Due to small geometries the capacitance reduces.
(3) Improved interconnect technology reduces the RC delay.
(4) The multiple threshold devices due to scaling adjusts the active and stand by power trade-
offs.
(5) The integration density improves due to single chip devices.
(6) Enhanced performance in terms of speed and power consumption.
(7) Cost of a chip decreases by twice.
Disadvantages of Scaling :
1) The power consumption per unit area increases as devices are scaled down. That means scaled
devices run increasingly hot. This is a severe performance limitation for scaled devices.
2) The scaling leads to mistakes of having scale proportionally to zero dimension or to zero
threshold voltages.
3) Since scaling reduces the carrier mobility, gain of the device reduces.
4) Due to reduction in conductor size, the current handling capacity of the device reduce. To
solve this addition metal layers are necessary for more densely packed structure.
5) As the packing density per chip increases, due to higher power density, the device becomes
very hot and needs forced cooling at the additional cost.
6) Higher fields also cause hot electron and oxide reliability problems.
Types-of-Scaling
Types of Scaling :
There are three types of scaling as constant voltage, constant field and lateral scaling. In constant
voltage scaling, VDD is kept constant, and the process is scaled. For constant field scaling, the
device dimensions are scaled by the parameter λ.
Constant Field Scaling :
In constant field scaling the scaled devices are obtained by scaling all dimensions of transistor,
device voltages and the doping . The effect of scaling is shown inconcentration densities by
factor Table below

Types-of-Scaling
From the table it is seen that the device dimension, L, W, tox, . The most important point in this
scalingxj, NA are scaled by factor is the supply voltage is scaled but the electric field remains
constant hence the same constant field scaling is given.
Constant Voltage Scaling :
 In constant voltage scaling the supply voltage VDD is kept constant while the process is
scaled. The effect of scaling is shown in Table below.

Types-of-Scaling
 With constant voltage scaling the electric field increases which has lead to the
development of the lateral double diffused structures.
Lateral Scaling : In lateral scaling only the gate length is scaled. This is also called as the "gate
shrinking". The effect of this scaling of parameters is shown in Table below.
Types-of-Scaling