BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

FOURTH SEMESTER 2018/19

MEBAAZG628T DISSERTATION

Dissertation Title : Design and UVM based verification of UART Interface

Name of Supervisor : Maneesh Pandey

Name of Student : Shwetank Shekhar

ID No. of Student : 2016BA99541

Abstract

UART stands for Universal Asynchronous Receiver and Transmitter is one of the important interfaces
used in System on Chip(SOC) Design irrespective of domain (Wireless, Networking and
Automotive).This interface is placed on Advance Peripherals Bus (APB) and is mostly used for low
speed communication . This is why it is important for Architects to understand design of this system.
Before system is deployed it should be guaranteed by the designer that all specification of design is met
else field failure can lead to catastrophic results. The confidence of deployment is achieved by process of
Verification in pre silicon phase and by validation in post silicon.
The design of UART begins with specification and principle of operation .System designer partition
UART into several blocks. Each block is coded into the Hardware description Language (HDL). The
process of integration of blocks leads to UART module.
The process of checking the specification feature in RTL phase is done by verification that can be done
either in crude way or following the Universal verification Methodology (UVM) based on philosophy of
Coverage driven (CDV).
Once CDV gives clearance to design, the process of prototyping begins. This involves synthesis; timing
Analysis, gate level simulation and Bitmap file generation .The Bit file is used to program the FPGA and
then is used for post silicon Validation. Once proved it can be deployed in the field.

Key Words: UART, UVM, CDV, HDL

Abbreviations: UART Universal Asynchronous Receiver and Transmitter
UVM Universal Verification Methodology
CDV Coverage Driven Verification
HDL Hardware Description Language
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

IV SEMESTER 2018/19
DISSERTATION

Dissertation Outline

BITS ID No : 2016BA99541

Name of Student : Shwetank Shekhar

Name of Supervisor : Maneesh Pandey

Designation of Supervisor : Researcher, IIT Ropar & Staff, NXP semiconductor

Qualification and Experience : Doctoral candidate, MTech ASIC Design, +14 yrs industry

E- Mail ID of Supervisor : maneesh.pandey@nxp.com

Topic of Dissertation : Design and UVM based verification of UART Interface

Name of First Examiner : Dr. PREMANANDA B S

Designation of First Examiner :

Qualification and Experience : PhD

E- Mail ID of First Examiner : premanandabs@gmail.com

Name of Second Examiner :

Designation of Second Examiner :

Qualification and Experience :

E- Mail ID of Second Examiner :

(Signature of Student) (Signature of Supervisor)

Date:20-10-2018 Date: 20-10-2018

The Dissertation Outline:

 Dissertation Topic
Design and Verification

 Dissertation Title

Design and UVM based verification of UART Interface.

 Objectives

a. Design of UART block

b. Architecting test bench in UVM
c. Test plan and test case creation
d. Prototyping the design

 Scope of work
Study principle of operation of UART.
Map specification to HDL
Test plan and test bench creation
Verifying the design
Prototyping the design

Detailed Plan of Work (according to the semester calendar)

Expected Specific
Serial
Tasks or subtasks to be done(be precise and date or week Deliverable in
Number
specific) of terms of the
of Task
completion project
1
Principle of Operation of UART

2 Learning HDL (verilog)

3 Design Partioon
4 RTL Coding
5 RTL Coding & Integration
6 Integration UART
modules
design
7 Learning UVM
8 Test plan creation
 9 Test bench creation
10 Test bench creation UVM based
environment
11 Verification
12 Verification
13 Prototyping
14 Prototyping Bit Map file
15 Validation
16 Validation

Supervisor’s rating of the Technical Quality of this Dissertation Outline

EXCELLENT / GOOD / FAIR/ POOR (Please specify): Excellent

Supervisor’s suggestions and remarks about the outline (if applicable).

The specification of UART changes from project to project so need for design and verification
always exist. This project demonstrate a generic CDV environment which can be reused across the
requirement and Project .This is excellent piece of work in term of generalization

Date: 20-10-2018 ___________________

(Signature of Supervisor)