CXD1250M/N

Vertical Clock Driver for CCD Image sensor

Description
CXD1250M CXD1250N
CXD1250M/N is a clock driver developed for the
20 pin SOP (Plastic) 20 pin SSOP (Plastic)
vertical register drive of CCD Image sensor.

Features
4-channel vertical clock driver and 1 channel
substrate driver are built-in.

Application
CCD camera

Structure
CMOS

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD VL – 0.3 to VL + 35.0 V
VM VL – 0.3 to VL + 35.0 V
VH VL – 0.3 to VL + 35.0 V
VHH VL – 0.3 to VL + 35.0 V
• Input volltage VI VL – 0.3 to VDD + 0.3 V
• Output voltage MVφ (pins 13, 17) VL – 0.3 to VM + 0.3 V
• Output voltage HVφ (pins 14, 16) VL – 0.3 to VH + 0.3 V
• Output voltage HHVφ (pin 19) VL – 0.3 to VHH + 0.3 V
• Operating temperature Topr –25 to +85 °C
• Storage temperature Tstg –40 to +125 °C

Recommended Operating Conditions

• Supply voltage VDD 5.0 ± 0.5 V
VM VL + 10.0 V
VH VL + 25.0 V
VHH VL + 30.0 V
VL –10.0 V
• Operating temperature Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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80639C43-PK

This datasheet has been downloaded from http://www.digchip.com at this page

 CXD1250M/N

Block Diagram and Pin Configuration (Top View)

VHH (20V)

VL (–10V)

VH (15V)
VM (0V)
Vsub

Vφ1

N.C
Vφ2

Vφ4
Vφ3
20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10
XSG1
XV2
Xsub

N.C
XSG2
XV3
XV1
GND

VDD (5V)
XV4
Pin Description
No. Symbol I/O Description
1 GND — GND
2 Xsub I Output control (Vsub)
3 XV2 I Output control (Vφ2)
4 XV1 I Output control (Vφ1)
5 XSG1 I Output control (Vφ1)
6 XV3 I Output control (Vφ3)
7 XSG2 I Output control (Vφ3)
8 XV4 I Output control (Vφ4)
9 VDD — Power supply (5V)
10 NC —
11 NC —
12 VH — Power supply (15V)
13 Vφ4 O Output (2 level : VM, VL)
14 Vφ3 O Output (3 level : VH, VM, VL)
15 VM — Power supply (0V)
16 Vφ1 O Output (3 level : VH, VM, VL)
17 Vφ2 O Output (2 level : VM, VL)
18 VL — Power supply (–10V)
19 Vsub O Output (2 level : VHH, VL)
20 VHH — Power supply (20V)

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 CXD1250M/N

Truth Table
Input Output
XV1 · 3 XSG1 · 2 XV2 · 4 Xsub Vφ1 · 3 Vφ2 · 4 Vsub
L H X X VM X X
H H X X VL X X
X X L X X VM X
X X H X X VL X
X X X L X X VHH
X X X H X X VL
L L X X VH X X
X : Don't care
H L X X Z X X Z : High impedance

DC Characteristics (Ta = 25°C)

Test condition
Item Symbol Min. Typ. Max. Unit
Power supply
"H" level input voltage VIH 3.5 — — V
"L" level input voltage VIL — — 1.5 V
"L" level output voltage VφL IφL = 20µA — –10 –9.9 V
"M" level output voltage VφM IφM = –20µA — 0.0 0.1 V
"M" level output voltage VφM IφM = 20µA –0.1 0.0 — V
VDD = 5V
"H" level output voltage VφH IφH = –20µA VL = –10V 14.9 15 — V
VM = 0V
"HH" level output voltage VφHH IφHH = –20µA 19.9 20 — V
VH = 15V
Input current Ii VHH = 20V — 1.0 — µA
Power supply current ∗ IM — 4.5 5.0 mA
Power supply current ∗ IDD — 0.3 0.5 mA
Power supply current ∗ IH — 0.1 0.2 mA
Power supply current ∗ IHH — 0.05 0.1 mA
∗ Suuply current at operation (See the Test Circuit)

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 CXD1250M/N

Switching Characteristics (See the Test Circuit Ta = 25°C, VHH = 20V, VH = 15V, VM = 0V, VL = –10V, VDD = 5V)

Item Symbol Conditions Max. Min. Unit

Output current IL Vφ1 to 4 = –9.5V –25 mA
Output current IM1 Vφ1 to 4 = –0.5V 10 mA
Output current IM2 Vφ1, 3 = 0.5V –9 mA
Output current IH Vφ1, 3 = 14.5V 12 mA
Output current ISL Vsub = –9.5V –12 mA
Output current ISH Vsub = –19.5V 7 mA
Rise time VL → VM TTLM Vφ1 to 4 = –0.5V After input transient 1000 ns
Fall time VM → VL TTML Vφ1 to 4 = –9.5V After input transient 500 ns
Rise time VM → VH TTMH Vφ1, 3 = 14V After input transient 1000 ns
Fall time VH → VM TTHM Vφ1, 3 = 1V After input transient 1000 ns
Rise time VL → VHH TTLHH Vsub = 17V After input transient 200 ns
Fall time VHH → VL TTHHL Vsub = –7V After input transient 200 ns
Coupling amplitude (middle level) VCOM Vφ1 to 4 0.5 V
Coupling amplitude (low level) VCOL Vφ1 to 4 0.5 V

Input Waveform (Repeat Cycle 15.7kHz)

5
XV1 0
5
XV2 0
5
XV3 0
5
XV4 0
600ns

TTML TTLM
Output Waveform 0

Vφ1

–10
0 VCOM

Vφ2

–10 VCOL
0

Vφ3

–10

Vφ4

–10

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 CXD1250M/N

Switching Waveform
Input Waveform
16.6ms

5
XV1
0
5
XV3
0
5
XSG1
0
5
XSG2
0
TTMH TTHM
Output Waveform
15

Vφ1 0

–10

5
15 Xsub
0
Vφ3 0 TTLHH TTHHL

–10
20

0 Vsub
Vφ2
–10 –10

Test Circuit R1 R1; 27Ω

C1 R2; 5Ω
R1
C1; 1500pF
C2 C2; 3300pF
C2
C1 C1
C2

C2
500pF R1 R1
C1

R2

20V –10V
0V
15V
20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

5V

Timing generator
(CXD1156Q)

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 CXD1250M/N

Application Circuit

ICX026/027 CXD1250M/N CXD1156Q

+15V
11 NC NC 10

12 VH VDD 9 +5V

Vφ4 1 13 Vφ4 XV4 8 4 XV4

Vφ3 2 14 Vφ3 XSG2 7 10 VSG2

15 VM XV3 6 8 XV3

Vφ1 6 16 Vφ1 XSG1 5 11 VSG1

Vφ2 3 17 Vφ2 XV1 4 9 XV1

–10V 18 VL XV2 3 5 XV2

1µ/35
sub 4 19 Vsub Vsub 2 21 Xsub

20 VHH GND 1
+20V 0.1µ
270k
4.7µ/
37 Refer to the Caution : Rise in power supply

56k 0.1µ
15k

1M 47k

15k 39k 27k

Note:
The capacitor more than 0.1µF should be connected between the ground and each pin of VDD, VH, VHH and VL .

Caution : Rise in Power Supply

When the substrate driver is in use, be careful not to let the CCD imagesensors Sub (pin 4) turn into
negative voltage.
To this end, raise VL and VHH at the application circuit under the following conditions.

VHH (20V)
t1

20%
0V

20%

VL (–10V)
t2

t2 ≥ t1 ≥ 10msec

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 CXD1250M/N

Package Outline Unit: mm

CXD1250M

20PIN SOP (PLASTIC) 300mil

+ 0.4 + 0.4
12.45 – 0.1 1.85 – 0.15

20 11
0.15

+ 0.2

5.3 – 0.1
+ 0.3
0.1 – 0.05

7.9 ± 0.4

6.9
1 10

0.5 ± 0.2
+ 0.1
0.45 ± 0.1 1.27 0.2 – 0.05

± 0.12 M

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY / PHENOL RESIN

SONY CODE SOP-20P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE ∗SOP020-P-0300-A LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE WEIGHT 0.3g

CXD1250N

20PIN SSOP (PLASTIC)

+ 0.2
∗6.5 ± 0.1 1.25 – 0.1

0.1
20 11
A
∗4.4 ± 0.1

6.4 ± 0.2

1 10
+ 0.1 + 0.05
0.22 – 0.05 0.65 ± 0.12 0.15 – 0.02

0.1 ± 0.1
0.5 ± 0.2

0° to 10°

DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

LEAD TREATMENT SOLDER / PALLADIUM

SONY CODE SSOP-20P-L01 PLATING
EIAJ CODE SSOP020-P-0044 LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.1g

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