Welcome to the National Instruments presentation of the Spartan-3E Starter Board as an

academic learning platform.

Understanding digital logic and FPGA concepts can be daunting for some undergraduate
students, especially those not studying electrical engineering. To facilitate a long-term and
engaging learning environment, there is a need for an intermediary hardware and software
package that is cost-effective, easy to understand and to implement, and is adaptable with
existing VHDL code.
Digital Design Fundamentals
The NAND gate is the fundamental building block for digital logic. It is a combination of
an AND gate coupled with a NOT gate at its output. The truth table above describes the
output behavior of implementing a NAND gate on two bitwise inputs.
Digital Design Fundamentals
NAND gates can be used in combination to implement logic that would traditionally be
implemented with AND, OR, and NOT gates. Using NAND gates for combination logic is
cost effective due to its logical completeness and inherent compactness.

The figure to the top left shows a basic combination logic. The figure to the bottom left
shows the same logic implemented using only NAND gates. Finally, the figure to the top
right shows an equivalent combination logic after logic optimizations are performed.
Single Bit Adders: Half Adder
To create even more complex combinational logic, truth tables can be used to describe
implementation. For example, a half adder is a logic circuit that can perform an addition on
two binary digits. The half adder produces a sum and a carry value which are both binary
digits.
Although logically concise, the half-adder cannot carry bits in multi-bit addition operations
which is considered a drawback.

[1] Wikipedia, http://en.wikipedia.org/wiki/Half_adder

Single Bit Adders: Full Adder
A full adder, solving many of the short comings of the half adder, is a logical circuit that
performs an addition operation on three binary digits. The full adder produces a sum and
carry value, which are both binary digits. It can work on its own or be combined with other
full adders. As shown, the truth table simplifies logic understanding.

[2] Wikipedia, http://en.wikipedia.org/wiki/Full_adder

Using FPGAs to Replace Discrete Logic
FPGA is short for “Field Programmable Gate Array.” The FPGA is a semiconductor with
unconnected logic gates at the time of manufacture. Users can define and re-define
functionality via software and this code is later downloaded to the chip for deployment.

The FPGA offers flexible deployment options to the user since debugging at the hardware
level can still be performed after code is downloaded.

[3] http://en.wikipedia.org/wiki/FPGA
FPGA Hardware Basics
An FPGA contains programmable logic components called "logic blocks", and
programmable interconnects. Logic blocks can be programmed to perform the function of
basic logic gates such as AND, and XOR, or more complex combinational functions such as
decoders or simple mathematical functions.

The architecture of the FPGAs vary from manufacturer to manufacturer, and often are
differentiated by the number of logic cells that are available.
The typical basic FPGA architecture consists of an array of configurable logic blocks. An
application circuit must be mapped into an FPGA with adequate resources. A classic FPGA
logic block consists of a 4-input lookup table (LUT), and a flip-flop. Many FPGA vendors
use LUTs to define the number of logic gates a FPGA can represent.
VHDL Software Basics
VHDL is short for “Very High Speed Integrated Circuit Hardware Description Language.”
VHDL is generally used to program FPGAs and ASICs. Over the years, it has become the
industry standard for these hardware platforms.

The main benefit of VHDL has been its ability to model and simulate hardware behavior
prior to its synthesis into real hardware gates and interconnects.

[4] http://en.wikipedia.org/wiki/Vhdl
VHDL Framework & Syntax
VHDL description of hardware is split into two sections, entities and hardware.

Entities define the inputs and outputs of the hardware logic. Function declarations in C and
C++ are similar in behavior.

Architecture describes the hardware logic behind the entity. Essentially, this is the hardware
implementation of the circuit. Function descriptions in C and C++ are similar in behavior.
VHDL Software Example: 1-Bit Adder
The example snippet here is the VHDL implementation of the half-adder mentioned earlier.
The entity section of the code defines inputs A and B and the outputs S and C.

The architecture section describes the behavior of the inputs and outputs in relation to each
other. In this code, A XOR (exclusive or) B value is assigned to the output S and A AND B
value is assigned to the output C. With this architecture, a simple 1-bit adder is
implemented with a small amount of code.
FPGA Implementation
The figure shows the simplified diagrammatic flow of data in the FPGA. The inputs A and
B are defined in the left I/O cells, the digital gates are implemented on the hardware level,
and the data is carried to the outputs S and C through the interconnects.
LabVIEW FPGA Module
The LabVIEW FPGA module is the National Instruments software for developing FPGA
Logic and Real-Time Hardware. With LabVIEW FPGA, several different hardware
platforms can be configured and programmed including:

• Spartan-3E Starter Board

• Plug-In Reconfigurable I/O (RIO) Boards by National Instruments
• CompactRIO Modular Reconfigurable I/O System by National Instruments
• Compact Vision System by National Instruments

The LabVIEW FPGA Module provides an easy-to-use solution to programming a multitude

of platforms. In a project based learning environment, the ease of LabVIEW FPGA module
will allow students to understand the essentials of FPGA programming quickly and
interactively.
LabVIEW FPGA Tool Chain
LabVIEW FPGA integrates intuitive graphical programming techniques into the FPGA
realm through a two-step translation process.

The user develops VIs in a LabVIEW graphical programming environment. During

program compilation, the LabVIEW FPGA module translates the LabVIEW code into
VHDL code. The VHDL code is subsequently converted to a bitstream representation by
the Xilinx onboard compiler and downloaded onto the FPGA target.

Throughout this entire process, LabVIEW FPGA allows for a real-time debugging
interaction with the user.
LabVIEW- A Natural Entity Architecture Pairing
LabVIEW provides a natural transition to and from VHDL code.

The front panel and connector pane of LabVIEW provides the same functionality as the
entity of VHDL code. Within the front panel, users can define inputs and outputs, and the
connector pane defines the datatypes of these parameters.

Similarly, the block diagram provides the same functionality as the architecture of VHDL
code. Within the block diagram, users describe the implementation of the code.
Building Higher Level Logic
The LabVIEW FPGA module makes modular programming very easy to develop and
implement.

For example, the user can develop JK Flip Flops using NAND gates in the block diagram.
A single JK Flip Flop can be built into a LabVIEW sub-function, called a “SubVI”, with a
few clicks of the mouse then combined and interchanged with other SubVIs to develop
more complex integrated logic circuits such as the 74LSxxx.

Users new to modular programming will find LabVIEW’s implementation to be intuitive

and quick. Rather than spending much time learning modular programming techniques,
users will be able to concentrate on fundamental FPGA concepts.
LabVIEW FPGA- More than Logic Generation
LabVIEW’s graphical interface offers much more than mere logic generation. Users can
follow data flow during debugging, they can probe and see the data change as it moves
through segments of code, and they can stop and pause program execution. In addition, the
digital logic they would regularly need are in the user palettes for immediate
implementation.

The front panel provides graphical aids to immediately notify the user of hardware behavior
with tools such as LEDs, switches, knobs, gauges, and much more. Whereas hardware
behavior would be difficult to predict in VHDL code until actual compilation on the
hardware, with LabVIEW FPGA, users can save time by emulating their code in LabVIEW
prior to downloading.
LabVIEW FPGA – G Programming Language
LabVIEW FPGA is a “G” or Graphical Programming Language, therefore LabVIEW is
inherently capable of parallel code execution. With the LabVIEW FPGA option, single
cycle loops can be used to guarantee that the included code will run within a single cycle of
the FPGA clock.

LabVIEW FPGA allows users to program not only simple FPGA boards, but also high
performance hardware from NI. LabVIEW FPGA assists greatly in projects that require
hardware level execution, seamless integration, and fast time-to-application.
Benefits
Using the parallel nature of graphical programming and the truly parallel
implementation on the FPGA, users can separate code into different code segments
which can run in parallel and achieve faster application execution. As users develop
code, they can start thinking about logical pieces to break the code into different
segments for faster execution.

LabVIEW FPGA also provides a natural introduction to VHDL programming with

the entity/architecture pairing.

FPGA hardware is extremely reliable and customizable, allowing users to quickly

change the behavior of their hardware via software.

The flexibility of FPGA hardware combined with the ease of LabVIEW FPGA,
allows users to quickly learn and develop FPGA applications.