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  • Sai Srujana Resume 2019

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    Girisala Sai Srujana is seeking a challenging career opportunity in ASIC VLSI verification where she can use her skills and experience. She has experience with Verilog, SystemVerilog, functional verification, simulation, and synthesis using tools like QuestaSim and ModelSim. Her projects include functional verification of a memory controller using SystemVerilog and developing an AXI VIP with monitors, generators, and coverage models. She has a B.Tech in ECE and training in VLSI design and verification.

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    Girisala Sai Srujana is seeking a challenging career opportunity in ASIC VLSI verification where she can use her skills and experience. She has experience with Verilog, SystemVerilog, functional verification, simulation, and synthesis using tools like QuestaSim and ModelSim. Her projects include functional verification of a memory controller using SystemVerilog and developing an AXI VIP with monitors, generators, and coverage models. She has a B.Tech in ECE and training in VLSI design and verification.

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    94 views2 pages

    Sai Srujana Resume 2019

    Uploaded by

    Sai srujana
    Girisala Sai Srujana is seeking a challenging career opportunity in ASIC VLSI verification where she can use her skills and experience. She has experience with Verilog, SystemVerilog, functional verification, simulation, and synthesis using tools like QuestaSim and ModelSim. Her projects include functional verification of a memory controller using SystemVerilog and developing an AXI VIP with monitors, generators, and coverage models. She has a B.Tech in ECE and training in VLSI design and verification.

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    of 2

    GIRISALA SAI SRUJANA

    Permanent address:
    HOUSE NO-7/140
    KONAPURAM(village),
    KANAGANAPALLI(mandal), Email: saisrujana.girisala@gmail.com
    ANANTAPUR(dist). Mobile : +91-7287969768

    CAREER OBJECTIVE
    Looking forward for a challenging career opportunity to excel and grow in ASIC VLSI
    verification domain where I can use my knowledge,experience and potential at maximum for mutual
    benefits.
    VLSI DOMAIN SKILL SET
    HDLs: Verilog
    HVLs: System Verilog
    Knowledge: Functional Verification, Synthesisable RTL,FSMbased
    design,Simulation,Synthesis.
    EDA Tools: QuestaSim,ModelSim,Quartus Prime
    Bus Protocol: AMBA AXI,APB
    OS: Windows
    ACADEMIC PROFILE
    YEAR DEGREE INSTITUTE PERCENTAGE/CGPA
    2013 SSC Priyadarsini Vidyamandir 9.7
    2015 Intermediate Narayana Junior College 9.57
    2019 B.Tech(ECE) Sanskrithi School Of Engineering 8.4

    PROJECT PROFILE
     Functional Verification of Memory Controller using System Verilog

    Design supports SRAM,SDRAM,FLASH&Synchronous Chip Select Devices.As part of


    this design verification,we created testbench using sv to generate scenarios targeting all
    types of supported memories for different possible combinations & different sizes
    supported. We also developed monitor, reference model , checker as part of self checking
    testbench implementation.
    Below is my responsibilities:
     Listing down design features
     Setting up testbench and tetbench component coding
     Testplan development

     Verification of AXI Protocol using System Verilog


    VIP Component Development for AXI3.0 protocol with support for various features.As part of
    this project I developed BFM,Generator,Monitor,Coverage Models and scenarios targeting
    validating features of AXI3.0 Protocol.
    Below is my responsibilities:
     Developing VIP Architecture.
     Coding VIP Components
     Validating AXI VIP using AXI Slave Model.

     Design and Verification of Interrupt controller.


     Design and verification of Synchronous FIFO& Asynchronous FIFO using Verilog

    EXPERIENCE
     Done online course on VLSI Design Methodology from MAVEN SILICON
     Six months classroom training on VLSI Design&Verification atVLSIGURU,Banglore.

    CO- CURRICULAR ACTIVITIES


     Attended one day workshop on “IOT USING RASPBERRY PI” .
     Attended one day workshop on “TELECOM GEN TECHNOLOGIES”
     Attended Webinar on “RTL DESIGN & FUNCTIONAL VERIFICATION”.
    Presented a Paper in National Level Technical Symposium on the topic “LIFI TECHNOLOGY”.
     Published a paper on “COMPARITIVE STUDY OF IOT AND EMBEDDED IN
    AGRICULTURAL FIELD” in AEPCIS 2K18.

    ACADEMIC PROJECT PROFILE

     Main project on “BIOMETRIC VOTING SYSTEM USING IOT” with ARDUINO controller.
     Mini project on “AUTOMATIC IRRIGATION SYSTEM”.

    PERSONAL INFORMATION
     Name : GIRISALA SAI SRUJANA
     Gender : Female
     Date of Birth : 12 July 1998
     Father’s Name : Mr.G.Honnurappa
     Mother’s Name : Mrs.G.Nagamani
     Marital status : Single
     Languages Known : English, Hindi and Telugu
     Nationality : Indian

    DECLARATION
    I hereby declare that the information furnished above are true to the best of my knowledge.
    Place: ANANTAPUR. Yours truly,
    Date: G.SAI SRUJANA.

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