ELE 3230

Microprocessors and Computer

Systems

Chapter 3
Operation of Stored Program
computer
(*Hall:ch2; Brey:ch1; Triebel:ch2)

ELE 3230 - Chapter 3 1

 A Simple Microcomputer

Data Bus
INPUT
DEVICE Control
Bus
Bus MEMORY
I/O CENTRAL
PROCESSING (RAM AND
PORTS
UNIT (CPU) ROM)
OUTPUT
DEVICE

Address Bus

Major parts: CPU, Memory, I/O

Buses: address bus, data bus, and control bus.

ELE 3230 - Chapter 3 2

 CPU
❚ The central processing unit (CPU) controls the operation
of the computer.
❚ Operation of the CPU
❙ fetches the instruction from memory
❙ decodes the instruction into a series of simple actions
(Performed in the Instruction decoder)
❙ executes the instruction by carrying out these actions
in a sequential manner (performed in the logic control
unit)

ELE 3230 - Chapter 3 3

 CPU
❚ A typical CPU consists of
❙ arithmetic-logic unit (ALU) which executes the instructions.
❙ logic control unit which interprets and sequences
instructions and generates the bus control signals.
❙ special purpose registers such as program counter (PC)
that holds the address of the next instruction or data item
to be fetched from memory.
❙ general purpose registers which are used for temporary
storage of binary data- such as accumulator A, status
register, etc.

ELE 3230 - Chapter 3 4

 Memory
❚ Two purposes :
(1). to store the binary codes for the sequences of
instructions that you want the computer to execute
(2). to store the binary-coded data with which the
computer is going to work with.

❚ Types:
Usually it consists of a mixture of RAM, ROM and
sometimes bulk storage devices such as floppy disks,
magnetic hard disks or optical disks.

ELE 3230 - Chapter 3 5

 Input/Output
❚ Allows the computer to take data from or to the outside world,
through the interface. Peripherals such as keyboards, video
display terminals, printers, and modems are connected to the I/O
sections.
❚ The actual physical devices used to interface the computer buses
to external systems are often called ports.
❚ The simplest type of I/O port is a set of D flip-flops.
❙ If they are being used as an input port, the D inputs are connected to
the external device, and the Q outputs are connected to the data bus.
❙ Data will then be transferred through the latches when they are
enabled by a control signal from the CPU.
❙ The same concept applies when using the D flip-flop for output.

ELE 3230 - Chapter 3 6

 Buses
❚ Address bus
❙ Unidirectional parallel signal lines connecting CPU and the
memory
❙ Bus width; number of lines (wires), can be 16, 20, 24, 32,
or 64 parallel signal lines.
❙ On these lines the CPU sends out the address of the
memory location that is to be written to or read from.
❙ A CPU with n address lines can address 2n memory
locations. For example, a CPU with 16 address lines can
address 216 or 65,536 (64K) memory locations.

ELE 3230 - Chapter 3 7

 Buses
❚ Data bus
❙ bus width: 4, 8, 16, 32 or 64 bits
❙ Bidirectional parallel signal lines (wires)
❙ many devices can be connected to the data bus; but only
one at a time can have its output enabled.
❙ Any device that is connected to the data bus must have
three-state outputs, so it can be disabled if not being used.

ELE 3230 - Chapter 3 8

 Buses
❚ Control bus
❙ consists of 4 to 10 parallel signal lines.
❙ CPU sends out signal on the control bus to enable the
outputs of addressed memory or port devices
❙ typical control bus signals: memory read, memory write,
I/O read and I/O write.

ELE 3230 - Chapter 3 9

 Buses
❚ To read a byte of data from memory location, for
example, consists the following activities:
❙ CPU sends out the memory address of the desired byte
on the address bus.
❙ CPU sends out a Memory Read signal on the control bus.
❙ The Memory Read signal enables the addressed memory
device to output a data word onto the data bus.
❙ The data word from the memory travels along the data bus
to the CPU.

ELE 3230 - Chapter 3 10

 Hardware, Software, and Firmware

❚ Hardware is the physical devices and circuitry of the

computers.
❚ Software is referred to the program written for the
computer.
❚ Firmware is the term given to programs stored in
ROMs or in other devices which permanently keep
their stored information.

ELE 3230 - Chapter 3 11

Example of a Stored Program
Execution

❚ Homework Assignment

❚ Movie Ticket Sales

ELE 3230 - Chapter 3 12

 Execution of a Three-step
Computer Program
PROGRAM (D. Hall - Figure 2-6 )
Memory 1. Input a value form port 05.
2. Add 7 to this value.
3. Output the result to port 02.
6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B 1C 2C3C 4C 5C 6C

CONTROL BUS
ADDRESS BUS

SEQUENCE
DATA BUS

CPU 1A CPU sends out address of first instruction to memory.

1B CPU sends out memory read control signal to enable memory.
CONTROL BUS
1C Instruction byte (E4H) sent from memory to CPU on data bus.
6D 2D 2E 6F 2F 6E 2A Address next memory location to get rest of instruction.
I/O 2B Send memory read control signal to enable memory.
2C Port address byte (05H) sent from memory to CPU on data bus.
2D CPU sends out port address on address bus.
PORT 05 PORT 02
2E CPU sends out port read control signal to enable I/O port.
0 1 2 3 2F Data from port sent to CPU on data bus and store in an internal
4 5 6 7
8 9 + - register.
Keyboard Display ---------------------------------
(Complete the fetch and execution of 1st instruction)
ELE 3230 - Chapter 3 13
 Execution of a Three-step
Computer Program
3A CPU sends address of next instruction to memory.
Memory
3B CPU sends memory read control signal to enable memory.
3C Instruction byte (04H) from memory sent to CPU on data bus.
4A CPU sends next address to memory to get rest of
6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B 1C 2C3C 4C 5C 6C
instruction.
CONTROL BUS
4B CPU sends memory read control signal to enable memory.
ADDRESS BUS

DATA BUS

CPU 4C Number 07H sent form memory to CPU on data bus.

5A CPU sends address of next instruction to memory.
CONTROL BUS 5B CPU sends memory read control signal to enable memory.
6D 2D 2E 6F 2F 6E 5C Instruction byte (E6H) from memory sent to CPU on data bus.
6A CPU sends out next address to get rest of instruction.
I/O
6B CPU sends out memory read control signal to enable
memory.
PORT 05 PORT 02
6C Port address byte (02) sent from memory to CPU on data bus.
0 1 2 3 6D CPU sends out port address on address bus.
4 5 6 7
8 9 + -
6E CPU sends out data to port on data bus.
Display 6F CPU sends out output write signal to enable port.

ELE 3230 - Chapter 3 14

 Memory Address and Memory
Contents for a three-step Program

MEMORY CONTENTS CONTENTS OPERATION

ADDRESS (BINARY) (HEX)

00100H 11100100 E4 INPUT FROM

00101H 00000101 05 PORT 05H
00102H 00000100 04 ADD
00103H 00000111 07 07H
00104H 11100110 E6 OUTPUT TO
00105H 00000010 02 PORT 02

ELE 3230 - Chapter 3 15

 A Typical PC Motherboard
Disk Controller

Video Card

Expansion
Slots

Processor Processor DMA Interrupt Expansion

(8088 up (8087 up controller logic logic
to 80486) to 80487) (8237) (8259)

System
bus
640KB Timer Keyboard
System
Dynamic logic logic
ROM
RAM (8253) (8255)

Speaker Keyboard
ELE 3230 - Chapter 3 16