Lab Record-Me Vlsi

EXP NO: MODELLING OF SEQUENTIAL DIGITAL SYSTEM USING
DATE: VHDL
Aim:
To model sequential digital system using VHDL.
Tools Required:
Xilinx software
Program:
SR FLIPFLOP – Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srr is
Port ( clk,s,r,rst : in STD_LOGIC;
q,qb : inout STD_LOGIC);
end srr;
architecture Behavioral of srr is
begin
process(s,r,clk,rst)
begin
if(rst='0')then
q<='0';
qb<='1';
elsif(clk'event and clk='1')then
if(s='0' and r='0')then
q<='0';
qb<='1';
elsif s='0' and r='1' then
q<='0';
qb<='1';
elsif s='1' and r='0' then
q<='1';
qb<='0';
else
q<='Z';
qb<='Z';
end if;
end if;
end process;
end Behavioral;
Output Waveform:
T FLIPFLOP – Behavioral Modeling:
library IEEE;
entity tpp is
Port ( t,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end tpp;
architecture Behavioral of tpp is
begin
process(clk)
begin
if(clk='1')then
if(t='0') then
q<='0';
qb<='1';
else
q<='0';
qb<='1';
end if;
end if;
end process;
end Behavioral;
Output Waveform:
D FLIPFLOP – Behavioral Modeling:
library IEEE;
entity dff is
Port ( d,clk,rst : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(d,clk,rst)
begin
if(rst='1')then
q<=0;
q<=d;
end if;
end process;
qbar<=not(q);
end behavioral;
Output Waveform:
JK FLIPFLOP – Behavioral Modeling:
library IEEE;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rr is
Port ( j,k,clk,rst: in STD_LOGIC;
q,qb : inout STD_LOGIC);
end rr;
architecture Behavioral of rr is
begin
process (j,k,clk)
begin
if (rst='1') then
q<='0';
qb<='1';
if (clk'event and clk='1')then
if (j='0' and k='0')then
q<=q;
qb<=qb;
elsif(j='0' and k='1')then
q<='0';
qb<=not q;
q<='1';
qb<=not q;
q<=not q;
qb<=q;
end if;
end if;
end if;
end process;
end Behavioral;
Output Waveform:
RIPPLECARRY ADDER - Structural modeling:
library IEEE;
--library UNISIM;
entity ripplecarryaddr is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end ripplecarryaddr;
architecture Behavioral of ripplecarryaddr is
component fulladd
port(a,b:in std_logic;
s,cout:out std_logic);
end component;
signal x0,x1,x2:std_logic;
begin
f1:fulladd port map(a(0),b(0),cin,s(0),x0);
f2:fulladd port map(a(1),b(1),x0,s(1),x1);
f3:fulladd port map(a(2),b(2),x1,s(2),x2);
f4:fulladd port map(a(3),b(3),x2,s(3),cout);
end Behavioral;
FULL ADEER
entity fulladd is
Port ( a,b,c : in STD_LOGIC;
s,cout : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
s<=(a xor b xor c);
cout<=((a and b)or (b and c) or (c and a));
end Behavioral;
Output Waveform:
SHIFT REGISTER _Behavioral Modeling:
library IEEE;
--library UNISIM;
entity shftregstr is
Port ( clk,rst,load : in STD_LOGIC;
in1 : in STD_LOGIC_VECTOR (3 downto 0);
out1 : inout STD_LOGIC_VECTOR (3 downto 0));
end shftregstr;
architecture Behavioral of shftregstr is
begin
process(clk,rst,load)
begin
if(rst='1')then
out1<=in1;
elsif(load='1')then
out1<=(out1(0)&out1(3 downto 1));
else
out1<=(out1(2 downto 0)&out1(3));
end if;
end process;
end Behavioral;
Output Waveform:
UPDOWN COUNTER_ Behavioral Modeling:
library IEEE;
--library UNISIM;
entity updowncounter is
Port ( clk,rst,sel : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end updowncounter;
architecture Behavioral of updowncounter is
begin
process(clk,rst,sel)
variable temp:std_logic_vector(3 downto 0):="0000";
begin
if(rst='1')then
temp:="0000";
if(sel='1')then
temp:=temp+1;
temp:=temp-1;
end if;
end if;
count<=temp;
end process;
end Behavioral;
Output Waveform:
‘
Result:
The program for the sequential digital system using VHDL is written and the output
waveforms are observed.
EXP.NO: TEST BENCHES USING VHDL
DATE:
Aim:
To design the sequential circuits test bench using the VHDL coding.
Tools Required:
Xilinx Software
Program:
D-FLIPFLOP:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testdff_vhd IS
END testdff_vhd;
ARCHITECTURE behavior OF testdff_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dff PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
clk<=not clk after 50ns;
tb : PROCESS
BEGIN
rst<='0';
d<='0' after 100ns;
d<='1' after 100ns;
-- Wait 100 ns for global reset to finish
-- Place stimulus here
wait; -- will wait forever
END PROCESS;END;
Output Waveform:
SR FLIPFLOP:
LIBRARY ieee;
ENTITY testsr_vhd IS
END testsr_vhd;
ARCHITECTURE behavior OF testsr_vhd IS
COMPONENT srff
PORT(
sr : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL sr : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
BEGIN
uut: srff PORT MAP(
sr => sr,
clk => clk,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
sr<="00";wait for 50ns;
wait for 100ns;
END PROCESS;
END;
Output Waveform:
T FLIPFLOP:
LIBRARY ieee;
ENTITY testtff_vhd IS
END testtff_vhd;
ARCHITECTURE behavior OF testtff_vhd IS
COMPONENT tff
PORT(
t : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic;
qb : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL t : std_logic := '0';
--Outputs
SIGNAL qb : std_logic;
BEGIN
uut: tff PORT MAP(
t => t,
clk => clk,
rst => rst,
q => q,
qb => qb
);
clk<=not(clk) after 50ns;
tb : PROCESS
BEGIN
rst<='1';
t<='0';wait for 50ns;
rst<='0';
t<='1';wait for 50ns;
wait for 50ns;
END PROCESS;END;
Output Waveform:
JK FLIPFLOP:
LIBRARY ieee;
ENTITY jkff3_vhd IS
END jkff3_vhd;
ARCHITECTURE behavior OF jkff3_vhd IS
COMPONENT jkflipflop
PORT(
jk : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL jk : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
BEGIN
uut: jkflipflop PORT MAP(
jk => jk,
clk => clk,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
clk<='1';jk<="00";wait for 100 ns;
clk<='0';wait for 100 ns;
END PROCESS;
END;
Output Waveform:
SHIFT REGISTER:
LIBRARY ieee;
ENTITY testshiftv_vhd IS
END testshiftv_vhd;
ARCHITECTURE behavior OF testshiftv_vhd IS
COMPONENT shift
PORT(
in1 : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
rst : IN std_logic;
load : IN std_logic;
out1 : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL load : std_logic := '0';
SIGNAL in1 : std_logic_vector(3 downto 0) := (others=>'0');
--BiDirs
SIGNAL out1 : std_logic_vector(3 downto 0);
BEGIN
uut: shift PORT MAP(
in1 => in1,
out1 => out1,
clk => clk,
rst => rst,
load => load
);
tb : PROCESS
BEGIN
in1<="1110";
rst<='1';load<='1';wait for 200ns;
rst<='0';load<='0';wait for 400ns;
END PROCESS;
END;
Output Waveform:
UP DOWN COUNTER:
LIBRARY ieee;
ENTITY testupdown_vhd IS
END testupdown_vhd;
ARCHITECTURE behavior OF testupdown_vhd IS
COMPONENT updown
PORT(
clk : IN std_logic;
rst : IN std_logic;
sel : IN std_logic;
count : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL sel : std_logic := '0';
--Outputs
SIGNAL count : std_logic_vector(3 downto 0);
BEGIN
uut: updown PORT MAP(
clk => clk,
rst => rst,
sel => sel,
count => count
);
tb : PROCESS
BEGIN
rst<='0';sel<='0';wait for 400ns;
rst<='0';sel<='1';wait for 400ns;
END PROCESS;
END;
Output Waveform:
RIPPLE CARRY ADDER:
LIBRARY ieee;
ENTITY ripple_vhdl_tb_vhd IS
END ripple_vhdl_tb_vhd;
ARCHITECTURE behavior OF ripple_vhdl_tb_vhd IS
COMPONENT ripple
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL cin : std_logic := '0';
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL s : std_logic_vector(3 downto 0);
SIGNAL cout : std_logic;
BEGIN
uut: ripple PORT MAP(
a => a,
b => b,
cin => cin,
s => s,
cout => cout
);
-- clk pulse
tb : PROCESS
BEGIN
wait for 100 ns;
a<= "0001";
b<= "0010";
wait for 100 ns;
a<= "0001";
b<= "0110";
wait for 100 ns;
a<= "0011";
b<= "0110";
cin <= '1';
wait for 100 ns;
a<= "1011";
b<= "0110";
END PROCESS;
END;
Output Waveform:
Result:
The test bench for various sequential systems are written using VHDL and its output
waves are obtained.
EXP NO: MODELLING OF SEQUENTIAL DIGITAL SYSTEM USING
DATE: VERILOG
Aim:
To model sequential digital system using VERILOG.
Tools Required:
Xilinx software
Program:
D FLIPFLOP- Behavioral modeling:
Module dfff(d,clk,q);
Input d,clk;
Output reg q;
Always @(posedge clk)
q=d;
endmodule
Output Waveform:
T FLIPFLOP-Behavioral Modeling:
Module tff1(q,qb,t clk,rst);

output reg q,qb;
input t,clk,rst;
always@(posedge clk or negedge rst)
begin
if(rst)
begin
q<=1’b0;
qb<=1’b1;
end
else
q<=t^q;
qb<=~q;
end
endmodule
Output Waveform:
JK FLIPFLOP – Behavioral modeling:
Module jkfff(j,k,rst,q,qb);
input j,k,clk,rst;
output reg q,qb;
always@(posedge clk or negedge rst)
begin
q<=1’b0;
qb<=1’b1;
end
else
begin
case({j,k})
2’b00 : begin q<=q;qb<=~q;end;
2’b01 : begin q<=1’b0; qb<=~q; end
2’b10 : begin q<=1’b1; qb<=~q; end
2’b11 : begin q<=~q; qb<=q; end
endcase
end
end
endmodule
Output Waveform:
SR-FLIPFLOP - Gate level Modeling:
module srff(s,r,clk,q,qb);
input s,r,clk;
output reg q,qb;
wire p1,p2;
nand n0(p1,s,clk),n1(p2,r,clk),n2(q,p1,qb),n3(qb,q,p2);
endmodule
Output Waveform:
RIPPLE CARRY ADDER- Gate level Modeling:
module ripverilog(sum, cout, a, b, cin);

output [3:0] sum;
output cout;
input [3:0] a;
input [3:0] b;
input cin;
wire c0,c1,c2;
fa ff0(sum[0],c0,a[0],b[0],cin);
fa ff1(sum[1],c1,a[1],b[1],c0);
fa ff2(sum[2],c2,a[2],b[2],c1);
fa ff3(sum[3],cout,a[3],b[3],c2);
endmodule
module fa(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
assign sum=a^b^cin;
assign cout =(a*b)|(b*cin)|(cin*a);
endmodule
Output Waveform:
SHIFT REGISTER-Behavioral Modeling:
module shiftverilog(y, i, s, clk);

input [3:0] i;
input [1:0] s;
input clk;
output reg [3:0] y;
always @ (posedge clk)
case (s)
2'b00:y=4'b0000;
2'b01:y=i;
2'b10:y=i<<1;
2'b11:y=i>>1;
endcase
endmodule
Output Waveform:
When s=01
When s=10
UPDOWN COUNTER- Behavioral Modeling:
module up(clk, rst, mode, count);

input clk;
input rst;
input mode;
output [3:0]count;
reg [3:0] count;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
count=4'b0000;
end
else
if(mode==1'b1)
begin
count=count+1;
end
else
begin
count=count-1;
end
end
endmodule
Output Waveform:
mode 0:
Mode 1:
Result:
The programs for the sequential digital system using VERILOG are written and the
output waveforms are observed.
EXP.NO: TEST BENCHES USING VERILOG
DATE:
Aim:
To design the sequential circuits test bench using the VERILOG coding.
Tools Required:
Xilinx Software
Program:
SR FLIPFLOP:
module srftest_v;
// Inputs
reg s;
reg r;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
srflip uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
s = 0;
r = 0;
clk = 0;
end
initial begin
clk=1'b0;
forever #100 clk=~clk
end
initial
begin
#100 clk=1;s=1'b1;r=1'b0;
#100 clk=0;
#100 clk=1;s=1'b0;r=1'b1;
#100 clk=0;
#100 clk=1;s=1'b1;r=1'b1;
#100 clk=0;
end
always @(r or s or clk or q or qb)
begin
$display("at time %t,input is %b%b%b,output is %b%b",
$time ,s,r,clk,q,qb);
end
endmodule
Output Waveform:
JK FLIPFLOP:
module jkfftest_v;
// Inputs
reg j;
reg k;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
jkkk uut (
.j(j),
.k(k),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial begin
j = 0;
k = 0;
clk = 0;
rst=0;
end
initial begin
#100 clk=1;j=1'b1;k=1'b0;
#100 clk=0;
#100 clk=1;j=1'b0;k=1'b1;
#100 clk=0;
#100 clk=1;j=1'b1;k=1'b1;
end
endmodule
Output Waveform:
T-FLIP FLOP:
module tfliptest_v;
// Inputs
reg t;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
tfill uut (
.q(q),
.qb(qb),
.t(t),
.clk(clk),
.rst(rst)
);
initial begin
t = 0;
clk = 1;
rst = 1;
always #100 clk=~clk
forever # 100 clk=0
#100 rst=1;t=1;
#100 rst=1;t=0;
#100 rst=0;t=1;
end
endmodule
Output Waveform:
D FLIPFLOP:
module d_flipflop_v;
//inputs
reg d;
reg clk;
reg rst;
//outputs
wire q;
wire qb;
//instantiate the Unit Under Test(UUT)
dflipflop uut(
.d(d),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
always #5 clk=~clk;
initial bigin
//initialize inputs
d=0;
clk=1;
rst=1;
//Wait 100 ns for global reset to finish
# 10 rst=0; d=1;
# 10 rst=1; d=0;
# 10 rst=0; d=1;
# 10 rst=0; d=0;
//
//Add stimulus here
end
endmodule
Output Waveform:
SHIFT REGISTER:
module shftreg_stim_v;
// Inputs
reg [3:0] i;
reg [1:0] s;
reg clk;
// Outputs
wire [3:0] y;
shift uut (
.i(i),
.s(s),
.clk(clk),
.y(y)
);
always #5 clk=~clk;
initial begin
i = 0110;
s = 0;
clk = 1;
// Wait 100 ns for global reset to finish
#100 clk=1;s=2'b00;
#200 clk=1;s=2'b01;
#300 clk=1;s=2'b10;
#400 clk=1;s=2'b11;
// Add stimulus here
end
endmodule
Output Waveform:
UPDOWN COUNTER:
module cntr_stim_v;
// Inputs
reg clk;
reg rst;
reg mode;
// Outputs
wire [3:0] count;
cntr uut (
.clk(clk),
.rst(rst),
.mode(mode),
.count(count)
);
always #5 clk=~clk;
initial begin
clk = 1;
rst = 1;
mode = 0;
#10 rst=1;mode=1;
#10 rst=0;mode=1;
end
endmodule
Output Waveform:
RIPPLE CARRY ADDER:
module rcatest_v;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
bitripple uut (
.sum(sum),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
a = 0;
b = 0;
cin = 0;
#100 a=4'b0010;b=4'b0001;
#100 a=4'b0110;b=4'b1001;
#100 a=4'b0011;b=4'b0100;
End
endmodule
Output Waveform:
Result:
The test benches for the sequential digital system using VERILOG are written and the
output waveforms are observed.
EXP.NO: DESIGN AND IMPLEMENTATION OF ALU USING FPGA
DATE:
Aim:
To design and implement ALU using FPGA.
Tools Required:
Xilinx software
Program:
ARITHMETIC AND LOGIC UNIT (6 Bit) – Behavioral Modeling:
library IEEE;
entity aluvhdl is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
a,b : in STD_LOGIC_VECTOR (5 downto 0);
f : out STD_LOGIC_VECTOR (5 downto 0));
end aluvhdl;
architecture Behavioral of aluvhdl is
begin
process(s,a,b)
begin
case s is
when"000"=>f<="000000";
when"001"=>f<=b-a;
when"010"=>f<=a-b;
when"011"=>f<=a+b;
when"100"=>f<=a xor b;
when"101"=>f<=a or b;
when"110"=>f<=a and b;
when"111"=>f<=not a;
when others=>f<="111111";
end case;
end process;
Output waveform:
Result:
The ALU is designed and implemented using FPGA. Its output waveform is obtained.
EXP.NO: IMPLEMENTATION OF MAC UNIT USING FPGA
DATE:
Aim:
To design and implement MAC unit using FPGA.
Tools Required:
Xilinx software.
Program:
MULTIPLIER AND LOGIC UNIT (MAC) - Structural Modeling:
library IEEE;
--library UNISIM;
entity macvhdl is
Port ( a0,a1,a2,b0,b1,b2,clk,reset : in STD_LOGIC;
y0,y1,y2,y3,y4,y5 : out STD_LOGIC);
end macvhdl;
architecture structural of macvhdl is
component reg
port(a0,a1,a2,a3,a4,a5,clk,reset:in std_logic;
y0,y1,y2,y3,y4,y5:out std_logic);
end component;
component multiplier is
port(a0,a1,a2,b0,b1,b2:in std_logic;
s0,s1,s2,s3,s4,s5:out std_logic);
end component;
signal c0,c1,c2,c3,c4,c5:std_logic;
begin
x1:multiplier port map (a0,a1,a2,b0,b1,b2,c0,c1,c2,c3,c4,c5);
x2:reg port map (c0,c1,c2,c3,c4,c5,clk,reset,y0,y1,y2,y3,y4,y5);
end structural;
MULTIPLIER:
library IEEE;
--library UNISIM;
entity multiplier is
Port ( a0,a1,a2,b0,b1,b2 : in STD_LOGIC;
s0,s1,s2,s3,s4,s5 : out STD_LOGIC);
end multiplier;
architecture Behavioral of multiplier is
component andgate is
port(a,b:in std_logic; y:out std_logic);
end component;
component halfadd is
port(a,b:in std_logic; s,c:out std_logic);
end component;
component fulladd is
port(a,b,cin:in std_logic;s,cout:out std_logic);
end component;
signal m,c:std_logic_vector(5 downto 0);
signal d:std_logic_vector(9 downto 0);
begin
x1:andgate port map(a0,b0,d(1));
x10:halfadd port map(d(2),d(3),m(1),c(1));
x11:fulladd port map(d(4),d(5),c(1),m(2),c(2));
x12:halfadd port map(d(6),m(2),m(3),c(3));
x13:fulladd port map(d(7),d(8),c(3),m(4),c(4));
x14:halfadd port map(d(9),c(4),m(5),c(5));
s0<=d(1);
s1<=m(1);
s2<=m(3);
s3<=m(4);
s4<=m(5);
s5<=c(5);
end Behavioral;
AND GATE:
library IEEE;
--library UNISIM;
entity andgate is
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
begin
y<=a and b;
end Behavioral;
HALF ADDER:
library IEEE;
--library UNISIM;
entity halfadd is
Port ( a,b : in STD_LOGIC;
s,c : out STD_LOGIC);
end halfadd;
architecture Behavioral of halfadd is
begin
s<=a xor b;
c<=a and b;
end Behavioral;
FULL ADDER:
library IEEE;
--library UNISIM;
entity fulladd is
Port ( a,b,cin : in STD_LOGIC;
s,cout : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
s<=a xor b xor cin;
cout<=(a and b) or (b and cin) or (a and cin);
end Behavioral;
REGISTER:
library IEEE;
--library UNISIM;
entity reg is
Port ( a0,a1,a2,a3,a4,a5,clk,reset : in STD_LOGIC;
y0,y1,y2,y3,y4,y5 : out STD_LOGIC);
end reg;
architecture Behavioral of reg is
component dff is
port(d,clk,reset:in std_logic;q:out std_logic);
end component;
begin
x1:dff port map(a0,clk,reset,y0);
end Behavioral;
D FLIPFLOP:
library IEEE;
--library UNISIM;
entity dff is
Port ( d,clk,reset : in STD_LOGIC;
q : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk,reset,d)
begin
if(reset='1') then
q<='0';
elsif(clk'event and clk='1') then
q<=d;
end if;
end process;
end Behavioral;
Output Waveform:
Result:
The MAC unit is designed and implemented using FPGA.

EXP.NO: MODELING OF MOSFET USING C
DATE:
Aim:
To execute MOSFET using C.
Tools Required:
C-program
Program:
MOSFET Using C:
#include<stdio.h>
#include<math.h>
Void main()
{
Float 0=8.85e-14,eins=4.0,un=650,up=240,tox=225.00E-8,vtn=0.022490’vtp=-
0.03025,i=1.25E-4;
Float k,ids,vgs,vds,b,w;
Inx;
Clrscr();
Printf(“ENTER THE CHOICE:1.nmos 2.pmos”);
Scanf(“%d”,&x);
Switch(x)
{
Case 1;
{
W=3*1;
Printf(“\t ENTER vgs:”);
Scanf(“%f”,&vgs);
Printf(“\t ENTER vds:”);
Scanf(“%f”,&vds);
k=((eins*e0)*un)/tox;
b=k*(w/l);
if((vds>=(vgs-vtn))&&(vgs>vtn))
{
ids =b*((vgs-vtn)*(vgs-vtn));
printf(“\n\t SATURATION REGION \n\t vds=%f v\n\t w=%fcm\n\t l=%f cm\n\t ids=%f
a\n\t”,vgs,vds,w,l,ids);
}
else if((vds<(vgs-vtn))&&(vgs>vtn))
{
ids = (b/2)*((2*(vgs-vtn)*vds)-(vds*vds);
printf(“LINEAR REGION\n\t vds=%fv\n\tw=%f ids=%f fcm\n\t l=%f cm\n\t ids=%f
}
else if(vgs<vtn)
{
ids=0;
printf(“CUT OFF REGION n\t vds=%f v\n\t w=%fcm\n\t l=%f cm\n\t ids=%f
}
Break;
}
{
W=2*1;
Printf(“\t ENTER vgs:”);
Scanf(“%f”,&vgs);
Printf(“\t ENTER vds:”);
Scanf(“%f”,&vds);
k=((eins*e0)*un)/tox;
b=k*(w/l);
if((vds>=(vgs-vtp))&&(vgs>vtp))
{
ids =-b*((vgs-vtp)*(vgs-vtp));
printf(“\n\t SATURATION REGION \n\t vds=%f v\n\t w=%fcm\n\t l=%f cm\n\t ids=%f
}
else if((vds<(vgs-vtp))&&(vgs>vtp))
{
ids = (b/2)*((2*(vgs-vtp)*vds)-(vds*vds);
printf(“LINEAR REGION\n\t vds=%fv\n\tw=%f ids=%f fcm\n\t l=%f cm\n\t ids=%f
}
else if(vgs<vtp)
{
ids=0;
printf(“CUT OFF REGION n\t vds=%f v\n\t w=%fcm\n\t l=%f cm\n\t ids=%f
}
Break;
}
Default:
Printf(“\n\t INVALID CHOICE\n”);
}
Getch();
}
Output:
Enter the value 1)nmos 2)pmos -1

Enter vgs:0.05
Enter vds: 0.30v
SATURATION REGION
Vgs=0.050000v
Vds=0.300000v
W=3.000000cm
L=0.000125cm
Ids=0.001857A

Enter vgs:0.3
Enter vds: 0.050v
LINEAR REGION
Vgs=0.300000v
Vds=0.050000v
W=3.000000cm
L=0.000125cm
Ids=0.030988A

Enter vgs:0.025
Enter vds: 0.12v
CUT OFF REGION
Vgs=0.020500v
Vds=0.120000v
W=3.000000cm
L=0.000125cm
Ids=0.000000A
Result:
The program for MOSFET using C has been executed.

EXP.NO: IMPLEMENTATION OF FFT USING MATLAB
DATE:
Aim:
To implement FFT-
i. Decimation in time and
ii. Decimation in frequency.
Tools Required:
MAT LAB
Program:
i)FFT- Decimation in Time

clc;
n=input('enter the point n:');
x0=input('enter input sequence in bit reversed order:');
x1=0;
x2=00;
m=log2(n);
for i1=1:m
p=n/(2^i1);
q=n/p;
for j1=1:q:n
r=j1;
for k=1:(q/2)
a=x0(r);
b=x0(r+(q/2));
k1=cos(2*pi*(k-1)/q)-i*sin(2*pi*(k-1)/q);
c=a+k1*b;
d=a-k1*b;
x1(r)=c;
x1(r+(q/2))=d;
r=r+1;
end;
end;
x0=x1;
x2=x1;
x1=x0;
end;
disp('the result is');
disp(x2);
t=1:n;
amplitude=abs(x2);
phase=angle(x2);
subplot(1,2,1);
stem(t,amplitude);
grid;
title('amplitude spectrum');
xlabel('sample');
ylabel('amplitude');
subplot(1,2,2);
stem(t,phase);
grid;
title('phase spectrum');
xlabel('sample');
ylabel('phase');
Input:
Enter the point n: 8

Enter input sequence in bit reversed order:[0 4 2 6 1 5 3 7]
Output:
The result is
Columns 1 through 3
28.0000 -4.0000 + 9.6569i -4.0000 + 4.0000i
Columns 4 through 6
-4.0000 + 1.6569i -4.0000 -4.0000 - 1.6569i
Columns 7 through 8
-4.0000 - 4.0000i -4.0000 - 9.6569i

Output waveform of Decimation in Time:
Program:
ii) Decimation in Frequency
clc;
n=input('enter the point n:');
x0=input('enter input sequence in natural order:');
x1=0;
x2=0;
m=log2(n);
for i1=1:m
p1=n/(2^i1);
p=n/(p1*2);
q=n/p;
for j1=1:q:n
r=j1;
for k=1:(q/2)
a=x0(r);
b=x0(r+(q/2));
k1=cos(2*pi*(k-1)/q)-i*sin(2*pi*(k-1)/q);
c=a+b;
d=(a-b)*k1;
x1(r)=c;
x1(r+(q/2))=d;
r=r+1;
end;
end;
x0=x1;
x2=x1;
x1=x0;
end;
q=x2(3);
x2(3)=x2(2);
x2(2)=q;
g1=x2(3);
x2(4)=x2(3);
x2(3)=g1;
disp('the result is');
disp(x2);
t=1:n;
amplitude=abs(x2);
phase=angle(x2);
subplot(1,2,1);
stem(t,amplitude);
grid;
title('amplitude spectrum');
xlabel('sample');
ylabel('amplitude');
subplot(1,2,2);
stem(t,phase);
grid;
title('phase spectrum');
xlabel('sample');
ylabel('phase');
Input:
enter the point n:8

enter input sequence in natural order:[1 2 3 4 5 6 7 8]
Output:
the result is
Column 1
36.0000
Column 2
-4.0000 + 4.0000i
Column 3
-4.0000
Column 4
-4.0000
Column 5
-4.0000 + 9.6569i
Column 6
-4.0000 - 1.6569i
Column 7
-4.0000 + 1.6569i
Column 8
-4.0000 - 9.6569i
Output wave form of Decimation in Frequency:
Result:
The FFT in DIT and DIF algorithms were designed and implemented using MATLAB.
EXP.NO: IMPLEMENTATION OF FIR AND IIR FILTER
DATE: USING MATLAB
Aim:
To implement FIR and IIR filters using MAT lab.
Tools Required:
MAT LAB
Program:
FIR filter
clc;
clear all;
close all;
disp('the type of filter are:');
disp('1)low pass filter');
disp('2)high pass filter');
disp('3)band pass filter');
disp('4)band stop filter');
k=input('enter the choice of the filter');
N=input('enter the length of the filter');
t=(N-1)/2;
switch k
case 1
wc=input('Enter the lower cut off frequency');
for n=1:N
if(n-1)==t
hd(n)=(wc)/pi;
else
hd(n)=sin(wc*(n-1)-t)/(pi*(n-1)-t);
end;
end;
case 2
wc=input('Enter the higher cut off frequency');
for n=1:N
if(n-1)==t
hd(n)=(pi-wc)/pi;
else
hd(n)=(sin(pi*(n-1)-t))-(sin(wc*(n-1)-t))/(pi*(n-1)-t);
end;
end;
case 3
wc1=input('enter the lower cutoff frequency');
wc2=input('enter the higher cutoff frequency');
for n=1:N
if(n-1)==t
hd(n)=(wc2-wc1)/pi;
else
hd(n)=sin(wc2*(n-1)-t)-sin(wc1*(n-1)-t)/(pi*((n-1)-t));
end;
end;
case 4
wc1=input('enter the lower cutoff frequency:');
wc2=input('enter the upper cutoff frequency:');
for n=1:N
if(n-1)==t
hd(n)=(pi+(wc2-wc1))/pi;
else
hd(n)=(sin(pi*(n-1)-t)*sin(wc2*(n-1)-t)+sin(wc1*(n-1)-t))/(pi*((n-1)-t));
end;
end;
end;
disp('the types of windows function');
disp('1)rectangle');
disp('2)hamming');
disp('3)hanning');
choice=input('enter your choice=');
switch choice
case 1
for n=1:1:N
w(n)=1;
end;
case 2
for n=1:1:N
w(n)=0.54-(0.46*cos(2*(n-1)*pi)/(N-1));
end;
case 3
for n=1:1:N
w(n)=0.5-(0.5*cos(2*(n-1)*pi)/(N-1));
end;
end;
disp('hd=');
disp(hd);
disp('w=');
disp(w);
for n=1:1:N
h(n)=hd(n)*w(n);
end;
disp('h=');
disp(h);
N=linspace(-2*pi,2*pi);
[h1,w1]=freqz(h,1,1024);
subplot(2,1,1);
plot(w1,(10*log(abs(h1))));
grid;
title('magnitude plot');
xlabel('frequency in radians');
ylabel('magnitude in db');
subplot(2,1,2);
plot(w1,angle(h1));
grid;
title('phase plot');
ylabel('angle');
Input:
the type of filter are:

1)low pass filter
2)high pass filter
3)band pass filter
4)band stop filter
enter the choice of the filter 3
enter the length of the filter 15
enter the lower cutoff frequency 2.2
enter the higher cutoff frequency 3.5
the types of windows function
1)rectangle
2)hamming
3)hanning
enter your choice= 1
Output:
hd = Columns 1 through 6
-0.6869 0.4036 -0.0328 -0.3818 0.7603 -1.0001
Columns 7 through 12
0.9642 0.4138 1.1304 -0.6282 0.2019 0.1633
-0.4615 0.6977 -0.8723

w = Columns 1 through 10
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
h= Columns 1 through 6
-0.6869 0.4036 -0.0328 -0.3818 0.7603 -1.0001
0.9642 0.4138 1.1304 -0.6282 0.2019 0.1633
-0.4615 0.6977 -0.8723

Output waveform of FIR Filter:
Program:
IIR filter
clc;
clf;
close all;
t=input('enter the sampling time');
w1=input('enter the pass band freq in radians');
w2=input('enter the stop band freq in radians');
k1=input('enter the stoppband attenuation in db');
k2=input('enter the passband attenuation in db');
disp('enter the type of filter');
p=input('1.Butterworth\n 2. Chebychev');
q=input('1.Impulse invaraiant\n 2.Bilinear transform');
if q==1
wp=w1/t;
ws=w2/t;
else
wp=(2/t)*tan(w1/2);
ws=(2/t)*tan(w2/2);
end;
if p==1
x=(10^(0.1*k2)-1);
y=(10^(0.1*k1)-1);
k=wp/ws;
N= ceil (log10(x/y)/(2*log10(1/k)));
wc=wp/((10^(k1/10)-1)^(1/(2*N)));
[b,a]=butter(N,wc,'s');
else
N=ceil((acosh(sqrt((10^(0.1*k2)-1)/(10^(0.1*k1)-1))) /(acosh(ws/wp))));
[b,a]=cheby1(N,k1,wp,'s');
end;
if q==1
[c,d]=impinvar(b,a,t);
else
[c,d]=bilinear(b,a,t);
end;
w=linspace(-2*pi,2*pi);
h=freqz(c,d,w);
subplot(2,1,1);
plot(w,(10*log10(abs(h))));
title('magnitude plot');
ylabel('magnitude plot');
grid;
disp('c=');
disp(c);
disp('d=');
disp(d);
subplot(2,1,2);
plot(w,angle(h));
title('phase plot');
xlabel('freq in rad');
ylabel('angle');
grid;
Input:
enter the sampling time1

enter the pass band freq in radians0.2*pi
enter the stop band freq in radians0.4*pi
enter the stoppband attenuation in db 14
enter the passband attenuation in db 21
enter the type of filter
1.Butterworth
2. Chebychev2
1.Impulse invaraiant
2.Bilinear transform2
Output:
c=
0.0098 0.0195 0.0098
d=
1.0000 -1.7196 0.9154
Output waveform of IIR Filter:
Result:
The FIR and IIR were designed and implemented using MATLAB.
EXP.NO: SIMULATION OF CMOS CIRCUITS USING SPICE
DATE:
Aim:
To simulate CMOS inverter, NAND & NOR gates using T-Spice.
Tools Required:
T-SPICE
CMOS-Inverter:
Circuit Diagram:
Netlist Program:
* SPICE netlist written by S-Edit Win32 7.00

* Written on Dec 20, 2011 at 12:43:11
* Waveform probing commands
.probe
.options probefilename="in2.dat"
+ probesdbfile="D:\Tanner\in2.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
.include "C:\Tanner123\Tanner\TSpice70\models\cmos0.18u(1).md"
M1 out in Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 out in Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5
v2 in gnd BIT ({1100} rt=0.1n ft=0.1n)
.tran 10n 80n
.print tran in out
* End of main circuit: Module0
Output Waveform:
CMOS INVERTER - DC ANALYSIS:
Circuit Diagram:
W
=22u
L=2u
V=5. 0 W
=22u
L=2u
R
=50
Netlist Program:

* Written on Dec 20, 2011 at 16:14:35
.probe
.options probefilename="invdc.dat"
+ probesdbfile="D:\Tanner\invdc.sdb"
.include "C:\Tanner123\Tanner\TSpice70\models\ml2_125.md"
M1 N3 N1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N3 N1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
R3 N3 Gnd 50 TC=0.0, 0.0
v4 N1 Gnd 5.0
v1 vdd gnd 5
.dc v4 0 5 0.1
.print dc v(n1) v(n3)
Otput Waveform:
CMOS NAND GATE:
Circuit Diagram:
Netlist Program:

* Written on Dec 8, 2011 at 10:49:32
.probe
.options probefilename="nandckt.dat"
+ probesdbfile="D:\Tanner\nandckt.sdb"
M1 N8 b output Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 output b Vdd Vdd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 Gnd a N8 Gnd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 output a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 4
v2 a gnd BIT ({1010} rt=0.1n ft=0.1n)
v3 b gnd BIT ({1010} rt=0.1n ft=0.1n)
.tran 20n 80n
.print tran a b output
*End of main circuit: Module0
Output Waveform:
CMOS NOR GATE:
Circuit Diagram:
Netlist Program:

* Written on Dec 8, 2011 at 11:39:54
.probe
.options probefilename="sedit.dat"
+ probesdbfile="norckt.sdb"
M1 out a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd b out Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 out a N2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 Vdd b N2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5
v2 a gnd BIT ({1010} rt=0.1n ft=0.1n)
v3 b gnd BIT ({1010} rt=0.1n ft=0.1n)
.tran 20n 80n
.print a b out
Output Waveform:
Result:
Thus CMOS Inverter, NAND gate, NOR gate are simulated using T-SPICE.
EXP.NO: DESIGNING OF STATIC AND DYNAMIC LOGIC CIRCUITS
DATE:
Aim:
To design static and dynamc logic circuits using TSPICE
Tools Required:
T-SPICE
STATIC SUM:
Circuit Diagram:
Netlist Program:

* Written on Dec 16, 2011 at 10:12:36
.probe
.options probefilename="ssum.dat"
+ probesdbfile="D:\Tanner\ssum.sdb"
.SUBCKT inv1 in out Gnd Vdd
.ENDS
Xinv1_1 f N1 Gnd Vdd inv1
M1 abar b f Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 f bbar a Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N1 c sum Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 sum cbar f Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.print tran sum
.print tran a
.print tran b
.print tran c
v1 a gnd BIT ({1100110} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v2 abar gnd BIT ({11110000} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v3 bbar gnd BIT ({11001100} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v4 b gnd BIT ({00110011} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v5 c gnd BIT ({01010101} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v6 cbar gnd BIT ({10101010} pw=20u lt=10u ht=10u on=5 off=0 rt=.1u ft=.1u delay=0)
v7 vdd gnd 5
.tran 1u 100u
Output Waveform:
STATIC CARRY:
Circuit Diagram:
Netlist Program:

* Written on Dec 16, 2011 at 11:45:15
.probe
.options probefilename="scarry.dat"
+ probesdbfile="D:\Tanner\scarry.sdb"
.SUBCKT Module0 in out Gnd Vdd
.ENDS
XModule0_1 N8 N9 Gnd Vdd Module0
XModule0_2 N12 N3 Gnd Vdd Module0
M1 N8 b a Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 b bbar N8 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N8 c b Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 c cbar N8 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N12 a c Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 a abar N12 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N8 N9 N10 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N10 N8 N8 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 carry N12 N10 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 N12 N3 carry Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.print tran carry
.print tran a
.print tran b
.print tran c
v7 vdd gnd 5
.tran 1u 100u
Output Waveform:
DYNAMIC SUM:
Circuit Diagram:
Netlist Program:

* Written on Dec 16, 2011 at 12:23:38
.probe
.options probefilename="dsum.dat"
+ probesdbfile="D:\Tanner\dsum.sdb"
.ENDS
Xinv1_1 N9 sum Gnd Vdd inv1
M1 N6 b N8 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N9 a N6 N5 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N2 bbar N6 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N8 c N10 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N10 cbar N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N10 clk Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N7 bbar N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 N10 cbar N7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 N9 N9 N1 abar NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 N9 clk Vdd N3 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.print tran sum
.print tran a
.print tran b
.print tran c
.print tran clk
v7 vdd gnd 5
.tran 1u 100u
*End of main circuit: Module0
Output Waveform:
DYNAMIC CARRY:
Circuit Diagram:
Netlist Program:

* Written on Dec 16, 2011 at 12:46:02
.probe
.options probefilename="sedit.dat"
+ probesdbfile="dcarry.sdb"
.ENDS
Xinv1_1 N3 carry Gnd Vdd inv1
M1 N3 a N7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N1 a N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N2 clk Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N3 clk Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.print tran carry
.print tran a
.print tran b
.print tran c
.print tran clk
v7 vdd gnd 5
.tran 1u 100u
Output Waveform:
Result:
The static and dynamic circuits are simulated and the output waveforms are observed using
TSPICE
EXP.NO: IMPLEMENTATION OF FIR FILTER
DATE: USING VERILOG
Aim:
To implement FIR and IIR filters using VERILOG.
Tools Required:
Xilinx Software
Programn:
module fir(clk,rst,sum1);
input clk,rst;
output wire[16:0]sum1;
reg[3:0]pct,dcnt1,dcnt2,dcnt3,dcnt4;
reg c,d,e,f,g;
reg[7:0]em;
wire in_clk;
reg[7:0]q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,q16,q17,q18,q19,q20,q21,q22,
q23,q24,q25,q26,q27,q28,q29,q30,q31,q32,q33,q34,q35,q36,q37,q38,q39,q40,q41,q42,q43,q
44,q45,q46,q47,q48,q49,q50,q51,q52,q53,q54,q55,q56,q57,q58,q59,q60,q61;
wire[15:0]tproduct1; wire[15:0]tproduct2; wire[15:0]tproduct3; wire[15:0]tproduct4;
wire[15:0]tproduct5; wire[15:0]tproduct6; wire[15:0]tproduct7; wire[15:0]tproduct8;
wire[15:0]tproduct9; wire[15:0]tproduct10;wire[15:0]tproduct11;wire[15:0]tproduct12;
wire[15:0]tproduct13;wire[15:0]tproduct14;wire[15:0]tproduct15;wire[15:0]tproduct16;
wire[15:0]tproduct61;
parameter coeff1=8'd1; parameter coeff2=8'd1; parameter coeff3=8'd1;
parameter coeff58=8'd1; parameter coeff59=8'd1; parameter coeff60=8'd1; parameter
coeff61=8'd1;
always@(negedge clk or negedge rst)
begin
if(!rst)
begin
pct=4'b0;
c=1'b0;
end
else if(pct==4'b0100)
begin
pct=4'b0;
c=~c;
end
else
begin
pct=pct+1;
end
end
//assign clkout1=pct[0];
always@(negedge c or negedge rst)
begin
if(!rst)
begin
dcnt1=4'b0;
d=1'b0;
end
else if(dcnt1==4'b0100)
begin
dcnt1=4'b0;
d=~d;
end
else
begin
dcnt1=dcnt1+1;
end
end
always@(negedge d or negedge rst)
begin
if(!rst)
begin
dcnt2=4'b0;
e=1'b0;
end
begin
dcnt2=4'b0;
e=~e;
end
else
begin
dcnt2=dcnt2+1;
end
end
always@(negedge e or negedge rst)
begin
if(!rst)
begin
dcnt3=4'b0;
f=1'b0;
end
begin
dcnt3=4'b0;
f=~f;
end
else
begin
dcnt3=dcnt3+1;
end
end
always@(negedge f or negedge rst)
begin
if(!rst)
begin
dcnt4=4'b0;
g=1'b0;
end
begin
dcnt4=4'b0;
g=~g;
end
else
begin
dcnt4=dcnt4+1;
end
end
always@(negedge f )
begin
if(g==1'b0)
begin
em=8'b10101010;
end
else
begin
em=8'b11111111;
end
end
always @(negedge e or negedge rst)
begin
if(!rst)
begin
q1<=8'b0;q2<=8'b0;q3<=8'b0;q4<=8'b0;q5<=8'b0;q6<=8'b0;q7<=8'b0;q8<=8'b0;q9<=8'b0;q
10<=8'b0;q11<=8'b0;q12<=8'b0;q13<=8'b0;q14<=8'b0;q15<=8'b0;
q16<=8'b0;q17<=8'b0;q18<=8'b0;q19<=8'b0;q20<=8'b0;q21<=8'b0;q22<=8'b0;q23<=8'b0;q
24<=8'b0;q25<=8'b0;q26<=8'b0;q27<=8'b0;q28<=8'b0;q29<=8'b0;q30<=8'b0;
q31<=8'b0;q32<=8'b0;q33<=8'b0;q34<=8'b0;q35<=8'b0;q36<=8'b0;q37<=8'b0;q38<=8'b0;q
39<=8'b0;q40<=8'b0;q41<=8'b0;q42<=8'b0;q43<=8'b0;q44<=8'b0;q45<=8'b0;q46<=8'b0;q4
7<=8'b0;q48<=8'b0;q49<=8'b0;q50<=8'b0;q51<=8'b0;q52<=8'b0;q53<=8'b0;q54<=8'b0;q55
<=8'b0;q56<=8'b0;q57<=8'b0;
q58<=8'b0;q59<=8'b0;q60<=8'b0;q61<=8'b0;
end
else
begin
q1<=em;q2<=q1;q3<=q2;q4<=q3;q5<=q4;q6<=q5;q7<=q6;q8<=q7;q9<=q8;q10<=q9;q11<=
q10;q12<=q11;q13<=q12;q14<=q13;q15<=q14;q16<=q15;q17<=q16;q18<=q17;q19<=q18;q
20<=q19;q21<=q20;q22<=q21;q23<=q22;q24<=q23;q25<=q24;q26<=q25;q27<=q26;q28<=
37<=q36;q38<=q37;q39<=q38;q40<=q39;q41<=q40;q42<=q41;q43<=q42;q44<=q43;q45<=
54<=q53;q55<=q54;q56<=q55;q57<=q56;q58<=q57;q59<=q58;q60<=q59;q61<=q60;
end
end
assign tproduct1=q1*coeff1;assign tproduct2=q2*coeff2;assign tproduct3=q3*coeff3;
assign tproduct10=q10*coeff10; assign tproduct11=q11*coeff11;
assign
sum1=tproduct1+tproduct2+tproduct3+tproduct4+tproduct5+tproduct6+tproduct7+tproduct8
+tproduct9+tproduct10+tproduct11+tproduct12
+tproduct13+tproduct14+tproduct15+ tproduct16+ tproduct17+ tproduct18+ tproduct19+
tproduct20+
tproduct21+ tproduct22+ tproduct23+ tproduct24+ tproduct25+ tproduct26+ tproduct27+
tproduct42+ tproduct43+ tproduct44+tproduct45+ tproduct46+ tproduct47+tproduct48+
tproduct49+tproduct50+tproduct51+tproduct52+ tproduct53+ tproduct54+ tproduct55+
tproduct56+ tproduct57+ tproduct58+ tproduct59+ tproduct60+ tproduct61;
endmodule
Result:
The program for FIR filter using VERILOG is written and the output waveform is
observed.

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