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Microwave Analysis of SiGe Heterojunction Double-Gate Tunneling Field-Effect Transistor Through Its Small-Signal Equivalent Circuit
Microwave Analysis of SiGe Heterojunction Double-Gate Tunneling Field-Effect Transistor Through Its Small-Signal Equivalent Circuit
DOI: 10.1002/mmce.21678
RESEARCH ARTICLE
1
Department of Electronics Engineering, Gachon
University, Gyeonggi-do, Korea Abstract
2
School of Electronics Engineering, Kyungpook In this study, Si0.5Ge0.5 was used as a source junction material in a tunneling
National University, Daegu, Korea field-effect transistor (TFET), which was analyzed using technology computer-aided
Correspondence design (TCAD) simulation and a small-signal non-quasi static (NQS) equivalent
Seongjae Cho, Department of Electronics
circuit. The NQS equivalent circuit with additional tunneling resistance (Rtunnel)
Engineering, Gachon University, Gyeonggi-do
13120, Republic of Korea. enables more accurate analyses. By using a de-embedding process, small-signal
Email: felixcho@gachon.ac.kr parameters in the intrinsic area were obtained. This process was used to analyze the
Funding information resistance and capacitance in each section, the tendencies of the materials, and the
Korea Evaluation Institute of Industrial voltage. The error between the NQS equivalent circuit and TCAD device simulation
Technology, Grant/Award Numbers: 10052928,
10080513; Ministry of Science and ICT, Grant/
was within 1.9% in the 400-GHz regime. A cut-off frequency (fT) of up to
Award Number: 2017R1A2B2011570 0.876 GHz and maximum oscillation frequency (fmax) of 146 GHz were obtained.
KEYWORDS
Int J RF Microw Comput Aided Eng. 2019;e21678. wileyonlinelibrary.com/journal/mmce © 2019 Wiley Periodicals, Inc. 1 of 7
https://doi.org/10.1002/mmce.21678
2 of 7 JUNG ET AL.
" #
gm Rtunnel τgm Rch R2tunnel C sd
Y 21 ≈ − ω Rgd Cgd +
2 2
Rtunnel + Rch ðRtunnel + Rch Þ2
" #
τgm Rtunnel g Rch R2tunnel C sd
− jω Cgd + + m
ðRtunnel + Rch Þ ðRtunnel + Rch Þ2
FIGURE 2 Schematic of the simulated SiGe heterojunction double-gate
TFET device ð3Þ
JUNG ET AL. 3 of 7
FIGURE 7 Schematic definitions of tunneling and channel resistances in FIGURE 9 Transfer curves of TFETs with Si and Si0.5Ge0.5 source
the small-signal equivalent circuit of TFET junctions at different VDS biases
JUNG ET AL. 5 of 7
TABLE 1 Capacitances and resistances in the intrinsic areas of TFETs with different source materials at different VDD values
Source material VDD (V) Cgd (fF/μm) Cgs (fF/μm) Rch (Ω) Rtunnel (Ω)
Si 0.6 0.310 0.143 9.18 × 10 8
7.37 × 10−9
0.8 0.298 0.142 7.97 × 10 7
9.67 × 10−8
1.0 0.286 0.142 1.31 × 10 7
6.44 × 10−7
Si0.5Ge0.5 0.6 0.157 0.158 9.76 × 107 2.17 × 10−7
0.8 0.149 0.158 6.98 × 10 6
3.55 × 10−6
1.0 0.142 0.161 1.19 × 10 6
2.29 × 10−5
Figure 10A,B depicts fT and fmax of the TFETs having high accuracy with errors of within 2% up to 1 THz. The real
Si0.5Ge0.5 and Si source junctions, respectively, in compari- part of Y22 in the operations at VGS > 0 V where band-to-
sons at different driving voltages (VDD's). fT and fmax of the band tunneling comes to presence is closely investigated
TFETs are not exactly equal to those expected by the equa- in Figures 11A,B. Re(Y22) can be approximated to a
tions for MOSFET, but the trend is similar.20 fT, fmax, and quadratic function of w in Equation (10) as can be induced
Cgd decrease in the order of VDS = 0.6 V, VDS = 0.8 V, and from Equation (4). Figure 11A plots Re(Y22) as a function of
VDS = 1.0 V, and the Si0.5Ge0.5 junction has a smaller Cgd frequency from the device simulation and the mathematical
than Si. The inverse tendency of Cgd is revealed since equations in comparison up to 400 GHz with an error
Cgd is larger than Cgs in TFET. As the result, small capaci- within 1.9%.
tance is the crucial factor improving the TFET RF
performances19,21,22 " #
2 2
1 R ch R C
It was previously demonstrated in Figure 5 that the Y 22 ≈ + ω2 Rgd C 2gd + tunnel sd
ð10Þ
capacitive components in the off-state (VGS = 0 V) had
Rtunnel + Rch ðRtunnel + Rch Þ2
FIGURE 10 RF performance parameters as a function of VGS at different FIGURE 11 Comparison between Re(Y22) changes from device simulation
source junction materials and VDS values. A, fT and B, fmax and small-signal circuit. Up to (A) 400 GHz and (B) 10 THz
6 of 7 JUNG ET AL.
A U T H O R B IO G R A P H I E S
Society (EDS) of the Institute of Electrical and Electron-
ics Engineers (IEEE).
YUNG HUN JUNG received the B.S.
degree in electronic engineering from SEONGJAE CHO received the B.S. and
Gachon University, Seongnam, Korea, Ph.D. degrees in Electronic Engineer-
where he is current pursuing the ing from Seoul National University,
M.S. degree. His research interests Seoul, Korea, in 2004 and 2010,
include design, modeling, and fabrica- respectively. He worked as an
tion of nanoscale CMOS devices and Exchange Researcher at the National
optical components such as high-speed photodetector Institute of Advanced Industrial Sci-
and resonators. He is a Student Member of the Institute ence and Technology (AIST), Tsukuba, Japan, in 2009.
of the Electronics and Information Engineering of He worked as a Postdoctoral Researcher at Seoul
Korea (IEIE). National University in 2010 and at Stanford University,
CA, USA from 2010 to 2013. He joined as a faculty
IN MAN KANG received the B.S. degree
member in the Department of Electronics Engineering at
in electronic and electrical engineering
Gachon University, Seongnam, Korea, in 2013. His
from Kyungpook National University,
research interests include group-IV-based alloy materials
Daegu, Korea, in 2001, and the Ph.D.
and their characterization, and design, modeling, and fab-
degree in electrical engineering from
rication of novel nanoscale CMOS devices, emerging
Seoul National University, Seoul,
memory technology, photonic devices and integrated cir-
Korea, in 2007. He worked as a Teach-
cuits, and neuromorphic devices and circuits. He is a Life
ing Assistance at the Inter-university Semiconductor
Member of the IEIE and a Member of IEEE (EDS).
Research Center (ISRC) at Seoul National University
from 2001 to 2006. From 2007 to 2010, he worked as a
Senior Engineer at Design Technology Team at Samsung
Electronics. He joined Kyungpook National University
How to cite this article: Jung YH, Kang IM, Cho S.
as a Full-Time Lecturer of the School of Electronics
Microwave analysis of SiGe heterojunction double-
Engineering where now he works as an Associate Profes-
gate tunneling field-effect transistor through its small-
sor. His current research interests include CMOS RF
signal equivalent circuit. Int J RF Microw Comput
modeling, silicon nanowire devices, tunneling transistors,
Aided Eng. 2019;e21678. https://doi.org/10.1002/
low-power nanoscale CMOS, and III-V compound semi-
mmce.21678
conductor devices. He is a Member of Electron Devices