Introducing IEEE Collabratec™

The premier networking and collaboration site for technology

professionals around the world.

IEEE Collabratec is a new, integrated online community where IEEE members,

Network.
researchers, authors, and technology professionals with similar fields of interest
can network and collaborate, as well as create and manage content. Collaborate.
Featuring a suite of powerful online networking and collaboration tools, Create.
IEEE Collabratec allows you to connect according to geographic location,
technical interests, or career pursuits.

You can also create and share a professional identity that showcases key
accomplishments and participate in groups focused around mutual interests,
actively learning from and contributing to knowledgeable communities.
All in one place!

Learn about IEEE Collabratec at

ieee-collabratec.ieee.org
 WINTER 2020
VOL. 12 • NO. 1
www.ieee.org/sscs-news

FEATURES
 8 Through the Looking Glass—2020 Edition
By Denis C. Daly, Laura C. Fujino,
and Kenneth C. Smith

25 Basics of Clock and Data

Recovery Circuits
By Amir Amirkhany

39 Yield Analysis for Electrical Circuit Designs

By Stephan Weber and Cândido Duarte
ABOUT THIS IMAGE:
To read more about plotting high-dimensional images
as a 3D projection of an E8 lattice, see “Yield Analysis
for Electrical Circuit Designs” by Stephan Weber and
Cândido Duarte.

COLUMNS/DEPARTMENTS
3 EDITOR’S NOTE
4 PRESIDENT’S CORNER
5 ASSOCIATE EDITOR’S VIEW
6 CIRCUIT INTUITIONS
53 CHAPTERS
84 PEOPLE
87 CONFERENCE REPORTS
98 IEEE NEWS
100 SOCIETY NEWS
104 CONFERENCE CALENDAR

Digital Object Identifier 10.1109/MSSC.2019.2951649

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 1

 SSC ADMINISTRATIVE COMMITTEE Terms to 31 Dec. 2021
President, Kenneth O Alison Burdett, Eugene Cantatore,
IEEE SOLID-STATE UT Dallas Kofi Makinwa, Dennis Sylvester,
CIRCUITS MAGAZINE Vice President, John R. Long Kathryn Wilcox
EDITOR-IN-CHIEF U Waterloo Terms to 31 Dec. 2022
R. Jacob (Jake) Baker Secretary, Emre Ayranci Andreia Cathelin, Vivek De, Makoto Ikeda,
rjacobbaker@gmail.com Peregrine Semiconductor Alvin Loke, Makoto Nagata
TECHNOLOGY EDITOR Treasurer, Wanda Gass Region 7 Representative
Tim Hollis Design, Connect, Create Ali Sheikholeslami
thollis@ieee.org Past President, Bram Nauta
University of Twente Region 8 Representative
TUTORIALS EDITOR Bram Nauta
Ali Sheikholeslami
Other Representatives
ali@eecg.utoronto.ca Representative to Sensors Council Region 10 Representative
ASSOCIATE EDITOR FOR Wai Lee Hideto Hidaka
THE FAR EAST Representative to CAS from SSCS Vice Presidents of Standing Committees
Open Shanthi Pavan Awards—John J. Corcoran
ASSOCIATE EDITOR FOR Representative to SSCS from CAS Chapters—Stefan Rusu
EUROPE AND AFRICA Franco Maloberti Conferences—Bill Bowhill
Marcel Pelgrom Representatives to EDA Council Education—Ali Sheikholeslami
pelgromconsult@kpnmail.nl Bryan Ackland, Vivek Tiwari Membership—Patrick Yue
CONTRIBUTING EDITORS Publications—John Long
Representative to ISSCC
Behzad Razavi Jan Van der Spiegel
razavi@ee.ucla.edu
Representative to CICC
Tom Lee
tomlee@ee.stanford.edu
Christophe Antoine IEEE PERIODICALS/
Representative to A-SSCC
NEWS EDITOR Hoi-Jun Yoo MAGAZINES DEPARTMENT
Abira Altvater Representative to ESSCIRC MANAGING EDITOR
abira.altvater@ieee.org Christian Enz Mark Gallaher
MAGAZINE ADVISORY Representatives to VLSI Symposium SENIOR MANAGING EDITOR
COMMITTEE Stephen Kosonocky, Philip Wong Geraldine Krolin-Taylor
Chair: Rakesh Kumar. Jake Baker, Representative to Sustainable ICT SENIOR ART DIRECTOR
Bill Bidermann, Glenn Gulak, Earl McCune Janet Dudar
Erik Heijne, ­Hideto Hidaka,
Richard Jaeger, Michael Kelly, Representative to IEEE YP Program ASSOCIATE ART DIRECTOR
Tom Lee, Marcel Pelgrom, Sevil Zeynep Lulec Gail A. Schnitzer
Willy Sansen, Abira Altvater, Representatives to Nanotechnology Council PRODUCTION COORDINATOR
Ali Sheikholeslami, Lewis Terman, Edith Beigne
Theresa L. Smith
Alice Wang, Patrick Yue Representative to Technical Committee on RFID
Jeffrey Walling PRODUCTION DIRECTOR
Peter M. Tuohy
Representative to Engineering Technology
Management Society ADVERTISING PRODUCTION MANAGER
IEEE SOLID-STATE Mike Beunder Felicia Spagnoli
CIRCUITS SOCIETY Representative to Biometrics Council DIRECTOR, BUSINESS
Executive Director, Michael Kelly Bruce Hecht DEVELOPMENT—MEDIA & ADVERTISING
IEEE SSCS, 445 Hoes Lane Representative to Internet of Things (IoT) Mark David
Piscataway, NJ 08854 USA Ramin Poorfard +1 732 465 6473, FAX: +1 732 981 1855
Tel: +1 732 981 3400 Future Network Initiative m.david@ieee.org
sscs-staff@ieee.org Aarno Pärssinen www.ieee.org/ieeemedia
Technical Community Program Nominations Committee Chair EDITORIAL SERVICES DIRECTOR
Specialist, Abira Altvater Bram Nauta Kevin Lisankie
IEEE SSCS, 445 Hoes Lane Women in Circuits Committee Chair STAFF DIRECTOR, PUBLISHING OPERATIONS
Piscataway, NJ 08854 USA Azita Emami Dawn M. Melley
Tel: +1 732 562 2676
Administrator, Lauren Caruso Elected AdCom Members at Large IEEE prohibits discrimination, harassment,
IEEE SSCS, 445 Hoes Lane Terms to 31 Dec. 2020 and bullying. For more information,
Piscataway, NJ 08854 USA Edith Beigne, Azita Emami, Daniel Friedman, visit http://www.ieee.org/web/aboutus/
Tel: +1 732 562 3871 Payam Heydari, Vivienne Sze whatis/policies/p9-26.html.

SCOPE: Each issue of IEEE Solid-State Circuits Magazine is envisioned as a self-contained

resource for fundamental theories and practical advances within the field of integrated cir-
cuits (ICs). Written at a tutorial level and in a narrative style, the magazine features articles
by leaders from industry, academia and government explaining historical milestones, current
trends and future developments.
CONTACT INFORMATION: See the “Contact Us” page on SSCS Web site: http://ewh.ieee
.org/soc/sscs/index.php?option=com_content&task=view&id= 10&Itemid=3.
IEEE Solid-State Circuits Magazine (ISSN 1943-0582) (SCMOCC) is published quarterly by The
Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor,
New York, NY 10016-5997, USA +1 212 419 7900. Responsibility for the contents rests upon
©ISTOCKPHOTO.COM/CHAKISATELIER

the authors and not upon the IEEE, the Society, or its members. The magazine is a member-
ship benefit of the IEEE Solid-State Circuits Society, and subscriptions are included in Society
fee. Replacement copies for members are available for US$20 (one copy only). Nonmembers
can purchase individual copies for US$194.00. Nonmember subscription prices are available
on request. Copyright and Reprint Permissions: Abstracting is permitted with credit to the
source. Libraries are permitted to photocopy beyond the limits of the U.S. Copyright law for
private use of patrons: 1) those post-1977 articles that carry a code at the bottom of the first
page, provided the per-copy fee indicated in the code is paid through the Copyright Clearance
Center, 222 Rosewood Drive, Danvers, MA 01970, USA; and 2) pre-1978 articles without fee.
For other copying, reprint, or republication permission, write to: Copyrights and Permissions
Department, IEEE Service Center, 445 Hoes Lane, Piscataway NJ 08854 USA Copyright © 2020
by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Periodicals ABOUT THE COVER:
postage paid at New York, NY, and at additional mailing offices. Postmaster: Send address This issue provides a glimpse “through the
changes to IEEE Solid-State Circuits Magazine, IEEE, 445 Hoes Lane, Piscataway, NJ 08854 USA.
Canadian GST #125634188 PRINTED IN USA looking glass” of what will be highlighted
during the 2020 International Solid-State
Digital Object Identifier 10.1109/MSSC.2019.2951650 Circuits Conference (ISSCC).

Promoting Sustainable Forestry

SFI-01681

2 W
S PI R
NITNEG
R 2 0 218
0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Welcome to the Winter 2020 Issue
of IEEE Solid-State Circuits Magazine!
I
In this first issue of the 12th year
of IEEE Solid-State Circuits Magazine,
we are pleased to feature a sam-
pling of forecasts for trends in ICs
and systems on chip, compiled
from research by members of the
11 subcommittees of the Interna-
tional Solid-State Circuits Conference
(ISSCC) 2020 Program Committee.
This year, these subcommittees are
as follows:
■■ Analog Systems
■■ Data Converters
■■ Digital Architectures Digital Cir-
cuits and Systems
■■ Innovative Topics: Medical, Imag-
ers, and Technology Directions
■■ Machine Learning and Artificial
Intelligence (AI)
■■ Memory
■■ Power Management
■■ Radio-Frequency Circuits and Wire-
less Systems
■■ Wireless
■■ Wireline.
Digital Object Identifier 10.1109/MSSC.2019.2951653
Date of current version: 23 January 2020
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 3
EDITOR’S NOTE
In this first issue
of the 12th year
of IEEE Solid-State
Circuits Magazine,
we are pleased to
feature a sampling
of forecasts for
trends in ICs and
systems on chip.
The 2020 theme for ISSCC is Inte-
grated Circuits Powering the AI Era.
We appreciate the efforts of Denis C.
Daly, Laura C. Fujino, and Kenneth C.
Smith, and the many subcommittee
chairs in putting together a feature
article about ISSCC for this issue.
As usual, several topics of inter-
est to our magazine’s readers, rang-
ing from tutorials to technology
overviews, are included in the issue.
These include the always w e l l -
received editorials/tutorials from
Marcel Pelgrom and Ali Sheikholesl-
ami. In addition, Amir Amirkhany
R. Jacob Baker
provides an article on the basics of
clock and data recovery circuits,
and Stephan Weber and Cândido
Duarte contribute an article on yield
analysis. Readers should find these
both interesting and useful.
The goal of the magazine contin-
ues to be to provide Society news
and information as well as a series
of self-contained resources to keep
the IEEE Solid-State Circuits Society
member up to date with changes in
technology, while at the same time,
providing reviews of circuit design
concepts. These include contributions
from experts describing the current
state of affairs and evolution of a
particular IC technology. We will also
continue to feature articles focused
on contributions by luminaries. Of
course, suggestions from readers are
always welcome.
We hope you enjoy reading IEEE
Solid-State Circuits Magazine. Please
send comments to me at rjacobbaker@
gmail.com.

 PRESIDENT’S CORN ER
Kenneth O
The Opportunity to Serve
I
IEEE Solid-State Circuits Society (SSCS)
members represent the innovation
engine for the half-trillion-dollar semi-
conductor industry that enables the
electrification of our surroundings.
They have made the use of informa-
tion, communication, and radar tech-
nologies possible in daily life. Now,
our members are creating technologies
that increase the use of artificial intel-
ligence (AI). It is a great honor, as your
incoming president for 2020–2021, to
represent and serve the Society.
There is so much happening in our
Society’s field of interest. AI integrated
circuits, hardware security for mixed-
signal circuits, codesign of power sup-
ply and systems, millimeter-wave and
terahertz circuits, and advanced sen-
sors are just a few examples. It is an
exciting time to be a member of SSCS.
However, the accompanying rapid
change is also challenging for our
members as well as industry and soci-
ety more generally.
With members’ help in managing
this challenge, the Society can increase
its value to members as well as its rel-
evance. Overcoming this challenge
will require greater participation of
members from all regions, ages, and
backgrounds. I look forward to work-
ing and serving with many of you.
Having said this, the Society is in
excellent shape. Under the leadership
of immediate Past President Bram
Nauta (2018–2019), the SSCS has estab-
lished a strategy to proactively man-
age a potentially disruptive change
Digital Object Identifier 10.1109/MSSC.2019.2951651
Date of current version: 23 January 2020
4 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
I am also
committed to
ensuring that
someone in a
far corner of
the globe who
hears about the
ISSCC and SSCS
for the first time
will have the
opportunity to
someday become
a leader of our
Society.
in publishing: the requirement for re­­
searchers to publish in open access
forums. Starting in the fall of 2019,
the open access Journal of Solid-State
Circuits began to accept submissions.
If you are interested in learning more
about this new journal, please visit the
Society website.
Our journals and conferences are re­­
cognized as being a primary venue for
reporting and learning about research of
the highest quality and greatest impact
in our field of interest. The SSCS’s mem-
bership and educational programs
are growing. Our young professional
and diversity programs are energetic.
This, of course, is due to the efforts
of the Society’s dedicated Administra-
tive Committee, leadership team, and
professional staff, as well as our past
presidents, all of whom are committed
to excellence in serving our members.
I first heard of the International
Solid-State Circuits Conference (ISSCC)
and Bob Widlar during a VLSI design
class 30 some years ago. It was beyond
my imagination that I would some-
day serve as SSCS president. I would
not have this opportunity without the
help, camaraderie, and mentorship
of the amazing people of our Society
I have met along the way or without
what the Society has given me by
being faithful to its mission of serv-
ing members through education, com-
munication, recognition, leadership
opportunities, and networking.
As your incoming president, I am
committed to ensuring the legacy
of excellence our Society is known
for, exciting the younger generation
by cultivating a greater appreciation
and understanding of the miraculous
technologies our members create,
enhancing our ability to respond to
the accelerating pace of technology
changes, and augmenting programs
that provide career development help
to members. I am also committed to
ensuring that someone in a far corner
of the globe who hears about the ISSCC
and SSCS for the first time will have
the opportunity to someday become a
leader of our Society due to our con-
tinued perseverance in executing our
mission of fostering innovation and
excellence in solid-state circuits for
the benefit of humanity.
Once again, it is my honor to have
this opportunity to serve, and I hope
to work with many of you to improve
the Society’s value and relevance for
members. Please share your thoughts
on how we can make our Society even
better by emailing me at k.k.o@ieee
.org or talking to me at our meetings.


A Sad, Sad Story
H
He caught my eye at the first lecture.
Strong students (not to be confused
with arrogant students) stand out
because of quick responses, comments
that are just a little ahead of the mate-
rial, and a relaxed attitude. He didn’t
have that. Was it the glance, the slightly
late reaction to a technical joke, or his
uncertainty in class assignments?
After the first few homework cor-
rections, he dangled at the bottom of
the score list. In conversations during
breaks, I noticed his language defi-
ciency, but speaking proper English
was a problem for almost the entire
class. If I called him aside to explain a
problem with the homework, I never
knew whether he understood until the
next assignment; of course, I advised
him to retake some prerequisite classes
before attempting the course again.
A while later, a university intern
came to my department. It was the
same young man. When new people
joined my department, I chatted with
their supervisors more often, just to
keep a finger on the pulse. After a few
days, the supervisor grumbled, “Do you
know how he calculates a spectrum?
He counts pulses!” He had been sent to
us by the signal-analysis department of
a renowned institute and was unable to
calculate a spectrum. After two weeks,
we sent him back. I took this failure
personally. How could we have missed
this during the initial interview? He
had passed all master’s subjects with
70–80% scores. However, because of
his language problems, he did not take
Digital Object Identifier 10.1109/MSSC.2019.2952234
Date of current version: 23 January 2020
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 5
A SSOC IATE EDITOR’S VIE W
regular written exams but instead took
a dozen oral assessments. For exam-
ple, he may have simply been asked to
summarize Chapter 7. And who cruci-
fies a stuttering student who is strug-
gling with a nonnative language?
He came into the picture again as
a Ph.D. student. The university had
appointed him based on only a resume
and a telephone call. The first year
was very difficult. Even though the
language problem should no longer
have been considered an excuse,
sending this man back to his home
country would have been seen as a
major loss of face. The first chance to
terminate the preliminary Ph.D. con-
tract expired. The state policy of output
monitoring means that departments
receive considerable compensation for
each successful Ph.D. graduate. For-
tunately, after two years, the professor
saw the futility of achieving reim-
bursement and took his loss.
That is why, a year later, he turned
up at a different university, one that
also does not check past achievements.
Apparently, the subject or the Ph.D.
requirements better suited his capaci-
ties. I was surprised to receive an email
from his professor a month before
his defense requesting that I act as
a replacement for an unexpectedly
resigning committee member. I like
to participate in the defense of candi-
dates who have successfully presented
at an International Solid-State Circuits
Conference or can show a first-author
publication in an IEEE journal. He
could only show much less selective
and prestigious conferences and local
workshops. Still, he was now a doctor
Marcel Pelgrom
of philosophy; therefore, he had a cor-
responding feeling of entitlement.
The job application process became
a lottery for him. His many unsuccess-
ful attempts at finding a job took so
much time that the market became
hot: human resource departments of
large companies offered a job with a
leased car to any applicants with the
term IT in their curriculum vitae. He
got a lucky strike.
But it was not the start of a spar-
kling career. Everyone was surprised
to discover what simple things this
Ph.D. graduate was incapable of doing.
After a long run-up with various
courses, and improvement programs,
it was clear that he would not make
a crucial contribution to the com-
pany’s bottom line. Although he was
now socially skilled, his poor perfor-
mance remained a barrier. Still, as
his boss assured me, a pink slip was
bad for public relations and the com-
pany’s atmosphere. Fortunately, it also
became clear to my former student
that his first career attempt was no
success. Everyone was happy when he
left for the next stop, now as an ambi-
tious applicant with several years of
industry experience. And it went on,
time and time again. He was highly
overrated because of his Ph.D. degree,
even though his skill set did not even
meet the bachelor’s degree level.
How he ended up is unfortunately
very different from what all those will-
ing teachers, supervisors, and bosses
had hoped for. Gentle healers make
smelly wounds, and that also holds for
our profession.

 C IRCU IT INTU ITIONS

Ali Sheikholeslami

Equalizer Circuit

W
Welcome to the 23rd article in the “Cir-
cuit Intuitions” column series. As the
title suggests, each article provides
insights and intuitions into circuit
design and analysis. These articles are
Transmitter

Tx
+
VTx(f )
Channel

Hw (f )
+
Vid(f )
Equalizer

Heq(f )
+
Vod(f )
– – –
aimed at undergraduate students but
may serve the interests of other read-
ers as well. If you read this article, I FIGURE 1: A simplified block diagram of a high-speed wireline transceiver. An equalizer at the
receiver end of the channel compensates for the channel attenuation of the transmit signal.
would appreciate your comments and
feedback as well as your requests and
suggestions for future articles in this
RL RL
H w (f )/(dB)

series. Please email me your comments:

+
ali@ece.utoronto.ca. – Vod
In a previous article [1] in this series, Vid /2 –Vid /2
we discussed how a piece of wire con- M1 M2
f RS CL CL
necting a data transmitter to a receiver fN (a)
attenuates the transmit signal at high
H eq(f )/(dB)

IB CS
frequencies, making the task of reli- IB
able data recovery by the receiver dif-
ficult. To compensate for the channel
f FIGURE 3: A differential circuit implemen-
attenuation, we design an equalizer
fz fp1 fp2 (b) tation of a continuous-time linear equalizer.
circuit and place it after the channel
H (f )/(dB)

(Figure 1). The equalizer circuit has a
transfer function that is the inverse
of the wire’s transfer function in the
frequency range of interest, as shown
in Figure 2. The equalizer is designed
such that the combined transfer func-
tion of the wire and the equalizer
circuit will be flat up to the Nyquist
frequency fN , defined as half of the
baud rate. In this article, we review a
common equalizer known as the con-
tinuous-time linear equalizer. We rely
on the techniques described in the
first article in this series [2] to find the
transfer function of this equalizer.
Figure 3 presents a circuit diagram
of an equalizer consisting of a differ-
ential pair with capacitive and resis-
Digital Object Identifier 10.1109/MSSC.2019.2952233
Date of current version: 23 January 2020
f attenuated at high frequencies, we wish
(c)
FIGURE 2: (a) The channel’s (wire’s) transfer
function exhibits a low-pass characteristic.
The attenuation at the Nyquist frequency fN
is highlighted. (b) The equalizer’s transfer
function exhibits a high-pass characteristic
at the frequencies of interest. It has one zero
and two poles. (c) The combined transfer
function of the channel and the equalizer
has a flat frequency response up to fN .
tive degeneration (C s and R s) and a
parallel combination of resistive and
capacitive load (R L and C L). The input
to the differential pair is the differen-
tial received signal, Vid . This signal is
essentially a low-pass-filtered version
of the transmit signal, and we wish
to use the equalizer to undo what
the channel (the wire) has done to it.
Intuitively, since the transmit signal is
to amplify the received signal at high
frequencies. Therefore, we need a high-
pass filter; such a filter will amplify the
high-frequency content of the signal
or, equivalently, attenuate the low-fre-
quency content. With this circuit, all
frequency components of the transmit
signal receive the same treatment and
are, hence, equalized.
Let us first understand intuitively
how this circuit performs equaliza-
tion. If we assume the input is differ-
ential, that is, the left side sees Vid /2
and the right side -Vid /2, then, by
symmetry, the circuit can be reduced
to a half circuit, as demonstrated in
Figure 4(a). Note that the transfer function

6 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

of this circuit is identical to that of the
differential one since both the input
and the output are divided by two in
the half circuit. We observe that the
half circuit is an amplifier with source
degeneration [3]. In general, the gain
of a common-source amplifier is
reduced when a resistor is added to
its source terminal. In this case, at low
frequencies, when C s is considered
open, a nonzero R s does reduce the
voltage gain of the circuit. At higher
frequencies, however, the capacitor
(C s) begins to short R s, reducing the
degeneration and increasing the gain.
So, in effect, this capacitor produces
a frequency-dependent gain where
the gain increases with frequency (as
the capacitor becomes a short circuit
with increasing frequency). This is the
exact effect we wished to produce.
Let us now find Vo in the half cir-
cuit using the method described in
[2]. We find the short circuit current
at the output node (I scd) and multi-
ply it by the total impedance (Z eqd)
seen at the output.
Figure 4 presents the steps toward
finding I scd . In the first step [Fig-
ure  4(b)], we find Vs by multiplying
its short circuit current (I scs) and its
equivalent impedance Z eqs . We then
use Figure 4(c) to find I scd .
The short circuit current at the
source node can be written as
I scs = g m Vi,
where g m is the transistor’s transcon-
ductance. Note that this is the short
circuit current at the source node
while the drain is also shorted to
ground. The equivalent impedance at
this node, while the drain is shorted,
can be written as
Z eqs = 1 ,
g m + 2/R s + 2sC s
where we have ignored the body
effect and the channel-length mod-
ulation (that is, we have assumed
g me = g m and g m ro & 1). The voltage
at the source node, while the drain
is shorted, can be written as the
product of I scs and Z eqs:
g m Vi
Vs = .
g m + 2/R s + 2sC s
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 7
RL CL
Zeqd
Vo
Iscd
Vi M1 Vi
RS RS
2CS
2 2
(a)
FIGURE 4: (a) A small-signal half circuit for the differential equalizer in Figure 3. We use this
circuit to derive an expression for Vo . (b) A circuit model to derive an expression for Vs while
the output node is shorted to ground. (c) Calculating the short circuit current at the output
node given Vi and Vs.
We now use Figure 4(c) to find the
output short circuit current
I scd = g m (Vs - Vi).
If we further divide I scd by Vi, we
find the short circuit transadmittance
of this amplifier, which is
- g m 1 + sC s R s
G (s ) = , changing C s, we can move fz and fp1
a 1 + sC s R s /a
where a = 1 + g m R s /2 is the degen-
eration factor.
We note that G (s ) does not include
the load. This is simply because
we have shorted the output node to
ground. This transfer function exhib-
its a gain at dc (-g m /a) and has one
zero at 1/2rC s R s and one pole at
a/2rC s R s . The high-pass characteris-
tic of this equalizer is due to the fact
that the zero frequency is lower than
the pole frequency (since a 2 1).
We now multiply this transfer
function by the equivalent output
impedance (Z eqd) to find the overall
voltage gain of this amplifier:
Z eqd = RL . trum of the transmit signal.
1 + sC L R L
In writing this equation, we have
ignored the impedance looking down
into the drain of the transistor as it is
assumed to be much larger than the
load. Finally, we can write
Vo -g m R L 1 + sC s R s 1 [3] A. Sheikholeslami, “Circuit intuitions:
= .
Vi a 1 + sC s R s /a 1 + sC L R L
This expression clearly identifies
one zero and two poles of the trans-
Vo
Vi
M1 M1 Iscd
VS
Zeqs Iscs VS
2CS
(b) (c)
fer function. More explicitly, in con-
nection to the parameters shown on
Figure 2, we have
fz = 1/2rC s R s,
fp1 = a/2rC s R s,
fp2 = 1/2rC L R L .
The reader can verify that, by
without changing fp2 or the equal-
izer’s dc gain. Indeed, by making C s
tunable, this circuit can equalize a
wider variety of channels, although an
equalizer with only one zero may not
be able to compensate for higher-order
channel attenuations. In these cases,
we may require two to three stages of
equalization or a more sophisticated
equalizer altogether.
In summary, an equalizer provides a
transfer function in the signal path that
is the inverse of the transfer function
introduced by the wire connecting the
transmitter and the receiver. In doing
so, the equalizer compensates for the
frequency-dependent loss caused by
the wire and restores the original spec-
References
[1] A. Sheikholeslami, “Circuit intuitions: The
electrical length of a wire,” IEEE Solid-State
Circuits Mag., vol. 11, no. 3, pp. 7–9, 2019.
doi: 10.1109/MSSC.2019.2922885.
[2] A. Sheikholeslami, “Circuit intuitions: Look-
ing into a node,” IEEE Solid-State Circuits Mag.,
vol. 6, no. 2, pp. 8–10, 2014. doi: 10.1109/
MSSC.2014.2315062.
Source degeneration,” IEEE Solid-State Cir-
cuits Mag., vol. 6, no. 3, pp. 5–6, 2014. doi:
10.1109/MSSC.2014.2329233.

 ©ISTOCKPHOTO.COM/CHAKISATELIER

Denis C. Daly, Laura C. Fujino, and Kenneth C. Smith

Through the Looking

Glass—2020 Edition
Trends in solid-state circuits from ISSCC

T
he International Solid- the Artificial Intelligence (AI) Era.” Ad­­ maintain connections and support net-
State Circuits Con- vances in solid-state circuits and sys- works not otherwise possible; they pro-
ference (ISSCC) is the tems have brought ever more powerful vide the ability to access information
flagship ­c onference communication and computational instantaneously and from any loca-
of the IEEE Solid-State capabilities into mobile form factors. tion, thereby helping to shape world
Circuits Society. The theme for ISSCC Such ubiquitous smart devices lie at events and culture, empower citizens
2020 is “Integrated Circuits ­Powering the heart of a revolution shaping how of all nations, and create social net-
we connect, collaborate, build relation- works that help worldwide communi-
Digital Object Identifier 10.1109/MSSC.2019.2952282 ships, and share information. These ties develop and form bonds based on
Date of current version: 23 January 2020 social technologies enable people to common interests.

8 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/20©2020IEEE

 ISSCC covers a spectrum of design
approaches in various technical areas
and advances, broadly categorized
as analog systems, power manage-
ment, analog-to-digital data conver-
sion, communication systems, digital
systems (including machine learning
and AI), and memory. It also covers
innovative topics such as microelec-
tromechanical systems, imagers,
sensors, and biomedical devices, in­­
cluding forward-looking solutions
that may be several years away from
becoming commercialized.
The 12 ISSCC technical subcom-
mittees annually update their analy-
sis of industry trends for the benefit
of the community at large. This arti-
cle summarizes some of these views
in selected technical areas.
Analog Systems
Subcommittee Chair:
Kofi A.A. Makinwa, Delft
­University of Technology,
The Netherlands
At ISSCC 2020, new analog-circuit
techniques are enabling improved
performance and reduced power
for temperature sensors, frequency
references, voltage references, and
amplifiers. Copackaged bulk-acous-
tic-wave technology with stability
better than ! 30 parts per million
(ppm) enables crystal-less radio ap­­
plications. Gallium nitride (GaN)
technology provides the ability to
realize voltage references that span
the ver y wide temperature range
of -50 to 200 °C. Class-D amplifiers
achieve the highest total harmonic
distortion to date by utilizing delta-
sigma techniques.
In the case of integrated tempera-
ture sensors, bipolar and resistor-
based designs continue to dramati­­cally
improve energy efficiency, as revealed
by Figure 1. In addition, single-trim,
resistor-based temperature sensors’
accuracy is approaching that of their
bipolar-junction transistor counter-
parts. Noncrystal oscillators continue
to improve in power efficiency while
achieving accuracies below !500 ppm,
as indicated in Figure 2.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 9
Power Management promise better utilization of active
semiconductors and passive compo-
Subcommittee Chair: Yogesh nents, are beginning to mature and
Ramadass, Texas Instruments, spread into diverse applications (from
Santa Clara, California LEDs and display drivers to high-con-
Power and energy management is im­­ version load-power delivery). At lower
portant for a number of applications voltages, hybrid approaches are push-
spanning embedded and performance ing toward higher integration with
computing, communications systems, all passive components integrated
consumer devices, automotive/indus- on chip.
trial sensing, and control. Over the The need for higher-voltage power
past decade, new topologies, semi- conversion is also growing, with more
conductor technologies, and control designs targeting the 48–400-V line,
paradigms have driven fundamen- power delivery, and cross-domain iso-
tal changes at the architecture and lation interfaces. GaN semiconductor
system levels. Hybrid and resonant technologies are improving in their
switched-capacitor topologies, which integration levels and functionality,
1.0E+03
1.0E+02
Resolution FOM (nj . K2)
1.0E+01
1.0E+00
1.0E–01
1.0E–02
1.0E–03
BJT
1.0E–04 Resistor
1.0E–05 ISSCC 2020
1.0E–06
2010 2012 2014 2016 2018 2020
Year
FIGURE 1: Trends in the energy efficiency of integrated temperature sensors: the resolution
figure of merit (FOM) versus time. BJT: bipolar-junction transistor.
1,000
ISSCC VLSI
CICC ESSCIRC
100 ASSCC ISSCC 2020
FOM (nW/kHz)
10
1
0.1
0.01
2006 2008 2010 2012 2014 2016 2018 2020 2022
Year
FIGURE 2: Trends in the power efficiency of noncrystal oscillators versus time. CICC: IEEE
Custom Integrated Circuits Conference; ASSCC: IEEE Asian Solid-State Circuits Conference;
VLSI: Symposia on VLSI Technology and Circuits (VLSI: very-large-scale integration); ESSCIRC:
European Solid-State Circuits Conference.
 reliability of high-voltage, high-fre-
Advances in solid-state circuits and quency switching power converters.
systems have brought ever more powerful These circuit techniques resemble
communication and computational capabilities “old school” NMOS-only techniques
of many decades ago yet add new
into mobile form factors. and important capabilities.
■■ Hybrid and resonant switched-ca-
pacitor converter techniques are
with power devices, gate drivers, instru- Perhaps the most important observ- increasingly leveraged in a wide
mentation, and interface circuitry able trends in power-management ICs range of topologies to reduce the
starting to share the same die. In addi- pertain to the diversification of appli- voltage stress on switches, shrink
tion to high-voltage isolated power cations, voltage, and power ranges. passive component size, and en-
delivery, data transmission across The following trends are observed at able a higher switching frequency.
galvanic isolation boundaries is in­­­ ISSCC 2020: ■■ The number and diversity of high-
creasingly important in many appli- ■■ As GaN gains greater capability for voltage IC designs are increasing to
cations. Energy harvesting continues high-level integration, a variety deal with challenges related to the
to mature for a variety of piezoelec- of circuit techniques is emerging grid interface, signal and power
tric, electromagnetic, and optical trans- that can improve the electromag- isolation, and powering embedded
ducer systems. netic interference, efficiency, and and sensor interface systems from
high dc-voltage domains.

1.E+07 Data Converters

1.E+06
1.E+05 Subcommittee Chair: Michael Flynn,
University of Michigan, Ann Arbor
1.E+04
P/fsnyq (pJ)

Data converters are a critical link

1.E+03 between the analog physical world
1.E+02 and the digital computing and sig-
nal processing prevalent in modern
1.E+01
electronics. The need to faithfully
1.E+00
preserve the signal across domains
1.E–01 continues to pressure data converters
10 20 30 40 50 60 70 80 90 100 110 120 to deliver more bandwidth and linear-
SNDR at fin,hf (dB)
ity while continuing to increase power
ISSCC 1997–2019 FOMS = 185 dB efficiency. ISSCC 2020 continues the
FOMW = 1 fJ/Conv. Step ISSCC 2020 trend of highly energy-efficient ana-
log-to-digital converters (ADCs) with
a combination of successive-approx-
FIGURE 3: ADC power efficiency (P/fsnyq) as a function of the SNDR. Conv.: conversion;
FOMW: FOM-Walden; FOMS: FOM-Schreier. imation-register (SAR), noise-shaping
SAR, and delta-sigma-based designs.
Time-interleaved pipeline architec-
tures are pushing the speed limits of
190
converter design.
180 Figures 3–5 represent traditional
170 metrics that capture the innovative
FOMS,hf (dB)

progress in ADC design. Figure 3 plots

160 ISSCC 1997–2019
the power dissipated relative to the
Envelope
150 ISSCC 2020 Nyquist sampling rate (P/fsnyq) as a
function of the signal-to-noise and dis-
140
tortion ratio (SNDR) to give a measure
130 of ADC power efficiency. Note that
120 a lower P/fsnyq metric represents a
1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12 more efficient circuit on this chart. For
fsnyq (Hz) low-to-medium-resolution convert-
ers, energy is primarily expended to
FIGURE 4: Power-normalized noise and distortion versus the Nyquist sampling rate. quantize the signal; thus, the overall

10 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

efficiency of this operation is typically
measured by the energy consumed per
conversion and quantization step. The
dashed trend line represents a bench-
mark of the 1fJ/conversion-step. Cir-
cuit noise becomes more significant
with higher-resolution converters,
necessitating a different benchmark
proportional to the square of the sig-
nal-to-noise ratio, represented by the
solid line. Designs published from
1997 to 2019 are shown in circles.
ISSCC 2020 designs are shown in black
dots, which continue moving toward
the lower right of the figure.
Figure  4 shows the signal fidelity
versus the Nyquist sampling rate nor-
malized to power consumption. At
low sampling rates, converters tend
to be limited by thermal noise, inde-
pendent of the sample rate. Higher
speeds of operation present addi-
tional challenges in maintaining accu-
racy in an energy-efficient manner,
indicated by the roll-off versus fre-
quency in the dashed line. The past
10 years have resulted in an improve-
ment of more than 10 dB in power-
normalized signal fidelity, i.e., a 10#
improvement in speed for the same
normalized signal fidelity. Of note at
this year’s ISSCC is that two designs
are pushing toward thermal-noise-
limited efficiency, using delta-sigma
and noise-shaped SAR architectures.
A pipelined SAR architecture deliv-
ers record-setting performance in
the speed-versus-efficiency corner of
the graph.
Figure 5 illustrates the ADC band-
width as a function of the SNDR.
Sampling jitter and aperture errors
coupled with an increased noise band-
width make achieving high resolu-
tion and bandwidth a particularly
difficult task. While a state-of-the-art
data converter sho­wed an aperture
error of approximately 1ps rms 10
years ago, designs with aperture
errors below 100 fs rms have been
published in recent years. ISSCC 2020
further advances the state of the art
with an extremely high-performing,
time-interleaved pipeline archi-
tecture that surpasses the 100-fs rms
aperture line.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 11
New analog-circuit techniques are enabling
improved performance and reduced power for
temperature sensors, frequency references,
voltage references, and amplifiers.
Communication Systems:
Radio-Frequency Subcommittee
Subcommittee Chair: Piet Wambacq,
IMEC, Leuven, Belgium
ISSCC 2020 features terahertz imag-
ing demonstrators, CMOS power
amplifiers (PAs), and phase-locked-
loop (PLL) prototypes. App­lications
driving advances in the field of radio-
frequency (RF) ICs in silicon technolo-
gies include 1) broadband and 5G
communications using massive mul-
tiple input/multiple output (MIMO)
and millimeter-wave (mm-wave) tech-
nologies, 2) the Internet of Things
(IoT), and 3) sensing and imaging at
sub-mm-wave frequencies.
PLL Synthesizers
Visible highlights are PLLs generating
mm-wave frequency carriers directly
or via on-chip multipliers; synthesiz-
ers offering lower integrated jitter
and power consumption (for exam-
ple, a –250-dB jitter-power FOM);
and wideband, frequency-modulated,
continuous-wave radar-chirp gen-
eration. Overall, subsampling PLLs
1.E+11
1.E+10
1.E+09
fin,hf (Hz)
1.E+08
1.E+07
1.E+06
10 20
FIGURE 5: The bandwidth versus the SNDR. psrms: picoseconds/root mean square.
continue to trend lower in power con-
sumption and integrated timing jit-
ter, with all-digital PLLs continuing to
displace traditional analog designs.
Fractional-N bang–bang, all-digital,
and hybrid fractional-N/integer syn-
thesizers are also demonstrating
continuing innovations in more tradi-
tional PLL designs.
The trend in the FOM for PLLs, which
depends on integrated jitter (jitter vari-
ance) and power consumption, is illus-
trated in Figure 6. ISSCC 2020 presents
two fractional-N PLLs with outstand-
ing timing-jitter performance:
1) a 12.8–15.2-GHz digital bang–bang
PLL that realizes 66-fs rms jitter and
performs a 1-GHz hop to within
0.1% of the steady-state frequency
in 18.55 ns
2) a 12.5-GHz fractional-N sam-
pling PLL in 28-nm CMOS that in-
corporates a digital background
phase-error correction to enable
58-fs integrated jitter (fractional
mode) and 51 fs (operating in in-
teger mode).
The overall FOM for these PLLs is con-
sistent with previous designs, as seen in
ISSCC 1997–2019
Jitter = 1 psrms
Jitter = 0.1 psrms
ISSCC 2020
30 40 50 60 70 80 90 100 110 120
SNDR at fin,hf (dB)
 FO
M ISSCC 2015 JSSC 2014
JI
1 T = 1
–2 FO
30 M
FO JIT
M =–
22
JI
T 0
=
–2
40 ESSC IRC 2015 ISSCC 2013
Jitter Variance (σRMS 2) (ps2)

Jitter Variance (σRMS 2) (ps2)

ISSCC 2015
JSSC 2016
0.1 ISSCC 2010 0.1
ISSCC 2017FOM
JSSC 2015 ISSCC 2013 JIT
=–
VLSI 2013 ISSCC 2014 ISSCC 2014 [2] 23
0
ISSCC 2018 ISSCC 2015 [3] ISSCC 2018 [6]
ISSCC 2016 JSSC 2014
JSSCC 2009 JSSCC 2018

0.01 0.01 FO
ISSCC 2020 M
ISSCC 2020
JIT
ISSCC 2019 =–
24
ISSCC 2019 0
ISSCC 2019 ISSCC 2019
FO FO
M M FO
JI JI M
T = T JIT
–2 = =–
–2 25
60 50 0
0.001 0.001
1 10 100 1 10 100
Power (mW) Power (mW)
(a) (b)

FIGURE 6: Oscillator trends for (a) subsampling PLLS and (b) frequency synthesizers above 20 GHz. JSSC: IEEE Journal of Solid-State Circuits.

added efficiency (PAE) at the higher

100 peak-to-average power ratios de­­
90 manded by advanced modulation for-
80 mats, such as 5G New Radio (NR). A
70
Peak PAE (%)

24–30-GHz watt-level Doherty PA fully

60
50 integrated in 45-nm silicon-on-insu-
40 lator CMOS employs a multiprimary
30 distributed active-transformer power
20 combiner and is capable of support-
10
ing 5G NR transmissions. Multiway
0
10 20 30 40 50 60 power combing and active load mod-
Psat (dBm) ulation are achieved simultaneously.
A digital polar PA prototype operating
CMOS SiGe GaN GaAs LDMOS
in class-G mode also functions above
CMOS Trend SiGe Trend ISSCC 2020 CMOS
1 W but in the 2.4-GHz industry, sci-
ence, and medicine band (Figure  7).
FIGURE 7: The under-6-GHz PA trend. SiGe: silicon germanium; GaAs: gallium arsenide; Remarkably, when the output power
LDMOS: laterally diffused metal-oxide semiconductor.
is reduced by 18 dB, this PA can still
provide drain efficiencies approach-
the figure. Advanced voltage-controlled in frequency synthesis will continue for ing 50% of peak performance. The
­oscillatorandmm-waveoutputfrequency- the foreseeable future. signal quality under 1,024  quadra-
generation circuit designs operating with ture amplitude modulation (QAM) is
greater stability at a lower power con- RF and mm-Wave PAs excellent at a - 44.5-dB error vector
sumption redefine the state of the art in Doherty-type PAs integrated in CMOS magnitude for a 23.2-dBm RF power
CMOS designs and ensure that advances are demonstrating an improved power- output (Figure 8). ISSCC 2020 will also

12 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

feature the first d-band PA in 16-nm
CMOS [fin field-effect transistor (Fin-
FET)]. It demonstrates a peak gain of
25.6 dB, saturated output power of
15 dBm, and peak PAE of 11.7%. The
active chip area for this 135-GHz PA
is just 0.062 mm 2 (Figure 9).
Emerging Technologies for
­Communication and Terahertz
­Sensing/Imaging
At ISSCC 2020, terahertz (THz)-frequency
imaging and sensing chips—demon-
strating higher levels of complexity
and power outputs than ever before—
and radio front-end circuits enabling
full duplex communication are impor-
tant developments. Computational
THz imaging debuts at ISSCC 2020
w i t h a n 8 # 8-p i x e l s o u r c e - a r r a y
system-on-chip (SOC) with an on-
chip, built-in self-test that radiates up
to 9.2 dBm at 0.42 THz and can support
imaging at up to 30,000 frames per sec-
ISSCC 2020, Wi-Fi and cellular stan-
dards continue to evolve with 5G NR
and Wi-Fi 6 (IEEE Standard 802.11ax) to
deliver ever increasing data throughput
using dense 1,024-QAM modulation, a
wide bandwidth of up to 200 MHz, and
multiple parallel data streams employ-
ing uplink and downlink MIMO. Fur-
thermore, carrier aggregation and
concurrent operation enable cellular
and Wi-Fi radios to obtain larger spec-
trum resources when a single contigu-
ous frequency range is not available.
Figure  10 shows the trend in the
number of downlinks for recent cel-
lular SOC implementations as well
as the shift in process nodes. It indi-
cates an increasing interest in carrier
70
60
50
Peak PAE (%)
aggregation to support higher data
rates. This year, an advanced cellular
transceiver features 10 downlinks in
12-nm FinFET CMOS. The transceiver
extends carrier aggregation to sup-
port up to six interband 3G, 4G, and
5G carriers while also enabling NR
and LTE protocols with dual connec-
tivity (evolved universal terrestrial
radio access NR dual connectivity).
Operation at the low supply ­voltages
available from energy harvesting and
small form factors are vitally impor-
tant for IoT and insertable medical
devices. A low-voltage Bluetooth low-
energy transceiver capable of oper-
ating through energy harvesting
is being introduced at ISSCC 2020;

ond. The highest radiated power for 40

silicon-based sources above 0.35 THz
30
is produced by a beam-steerable
20
array implemented in 40-nm CMOS.
It combines 36 coherent radiators 10
producing 24.1  dBm of equivalent 0
10 15 20 25 30 35 40 45 50 55
isotropically radiated power and a
Psat (dBm)
beam-steering range of 30° at a fre-
quency of 0.59 THz. CMOS SiGe GaN GaAs LDMOS InP
Future low-latency radio-access CMOS Trend SiGe Trend ISSCC 2020 CMOS
networks demand clocks with 0.1 ISSCC 2020 SiGe ISSCC 2020 GaN
parts per billion (ppb) stability. A
70-mW chip-scale molecular clock FIGURE 8: The over-20-GHz PA trend. InP: indium phosphide.
probing the 231.06-GHz transition
of carbonyl sulfide demonstrates
a stability of ! 3 ppb with changing
50
temperature. Finally, a sub-THz back-
45
scattering wireless tag operating at
40
260 GHz has a 5-cm range for bidirec-
35
Peak PAE (%)

tional communication via an on-chip 30

antenna array capable of beam steer- 25
ing across 30c. 20
15
Communication Systems: Wireless 10
5
Subcommittee Chair: Stefano –5
0
0 5 10 15 20 25 30 35 40
Pellerano, Intel, Hillsboro, Oregon Psat (dBm)
The continuing demand for faster
CMOS SiGe GaN GaAs LDMOS InP
wireless-data rates in the context of
mobile-battery limitations drives the CMOS Trend SiGe Trend ISSCC 2020 GaN
development of high-throughput
and power-efficient transceivers. At FIGURE 9: The over-50-GHz PA trend.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 13

 it has a –96.4-dBm sensitivity and
12 60 4.1-dB adjacent-channel rejection
Downlinks Process Node while dissipating 1.9 mW. Further-
10 50 more, a small-form-factor, crystal-
Number of Downlinks less medical implant communication

Process Node (nm)

8 40 system transceiver for insertable
smart pills is being presented with a
6 30 3.5- # 3.8-mm footprint.
Figure 11 displays the trend in
4 20
energy efficiency for 60-GHz and
beyond-80-GHz receivers. A receiver
2 10
being presented at ISSCC 2020 lever-
ages dual-polarization and circuit
0 0
2014 2015 2016 2017 2018 2019 2020 2021 techniques to demonstrate a 1 2 pJ/b
Year efficiency while achieving throughputs
of 250 Gb/s at mm-wave frequencies,
FIGURE 10: Trends in the number of downlinks and process nodes for recent cellular SOC reaching a 64-Gb/s data rate. This is
implementations.
the first 60-GHz phased-array recei­­
ver with 250 Gb/s throughput. The
growing demands on high-data-rate
transceivers are reflected in cellular
18
communications, with the develop-
16
ment of mm-wave systems for 5G NR
Energy per Bit (pJ/Bit)

14
in the 28- and 39-GHz bands.
12
10
Communication Systems: Wireline
8
6
Subcommittee Chair: Frank
4 60 GHz O’Mahony, Intel, Hillsboro, Oregon
2 Above 80 GHz Over the past few decades, electrical
0
2012 2014 2016 2018 2020 and optical interconnects have been
Year key components bridging the gap
between the exponentially growing
FIGURE 11: The receiver power-efficiency trend. demands for data bandwidth across
electronic components/systems and
the relatively gradual increase in pin/
cable density. Ranging from hand-
256 held electronics to supercomputers,
128 PCIe wireline data-communication band-
Per-Lane Transfer Rate (Gb/s)

64 QPI/KTI width must grow exponentially to

32 HT avoid limiting the performance scal-
16 ing of these systems. By increasing
SATA
the data per pin or cable of various
8 SAS
electronic devices and systems, such
4 USB
as memory, graphics, the chip-to-chip
2 DDR fabric, the backplane, rack-to-rack,
1 GDDR and local area networks (LANs), wire-
0.5 CEI line input–­output (I/O) has fueled
0.25 incredible technological innovation
2000 2004 2008 2012 2016 2020 in electronic devices and systems.
Year
Figure 12 shows that the data rate per
pin has approximately doubled every
FIGURE 12: The per-pin data rate versus year for a variety of common I/O standards. PCIe: four years across I/O standards rang-
peripheral component interconnect express; QPI/KTI: QuickPath Interconnect/Keizer Technol-
ogy Interconnect; HT: HyperTransport; SATA: serial advanced technology attachment; ing from double data rate (DDR) to
SAS: serial attached small computer system interface; GDDR: graphics DDR; CEI: comparably graphics and the high-speed Ethernet.
efficient interconnection. Figure 13 demonstrates that the data

14 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

rates for published transceivers have
kept pace with these standards while
taking advantage of CMOS scaling.
Figure 14 depicts the published trans-
ceiver energy efficiency versus chan-
nel losses at the Nyquist frequency in
the 40–50-dB range.
In part, this incredible improve-
ment is enabled by the power-perfor-
mance benefits of process technology
scaling. However, sustaining this expo-
nential trend for I/O bandwidth scal-
ing requires more than just transistor
scaling. Significant advances in energy
efficiency, channel equalization, and
clocking must be made to enable the
next generation of low-power, high-
performance computing systems.
ISSCC 2020 includes examples of short-
reach electrical interconnects operat-
ing at up to 25 Gb/s, long-reach copper
interconnect transceivers operating at
up to 112 Gb/s, and optical transceiv-
ers and components operating at up
to 112 Gb/s (direct modulation) and
640 Gb/s (coherent). New techniques
for noise and power reduction, chan-
nel equalization, and clock recovery
are reported. These transceivers and
transceiver building blocks are imple-
mented in CMOS and bipolar CMOS
(BiCMOS) technologies.
Scaling Electrical Interconnects
to 100 Gb/s
Bandwidth requirements in data cen-
ters and telecommunication infra­
structure continue to drive the demand
for ultrahigh-speed wireline commu-
nication. During the past few years,
complete transceivers operating at up
to 56 Gb/s were demonstrated across a
variety of channel lengths. Two notable
trends in these transceivers, especially
for long-reach channels, are the adop-
tion of pulse amplitude modulation
(PAM)-4 and a transition to digital-to-
analog converter (DAC)/ADC archi-
tectures with digital signal processor
(DSP)-based equalization. Although
PAM-4 provides twice the data rate
at the same baud rate as conventional
nonreturn to zero (NRZ) and thereby
relaxes channel loss requirements
for bandwidth doubling, it also comes
with more stringent requirements
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 15
for linearity, noise, and multilev­ Both transceivers exhibit flexible
­e l signaling. equalization capability and consume
This trend motivated the develop- 15 pJ/b (not including the DSP power).
ment of low-power data converters,
digital equalization, and clock recov- Silicon Photonic Bandwidth
ery as well as linear high-bandwidth Scaling and Integration
transceiver and receiver analog front The explosive growth of data and
ends. During the past two years, the data-centric computing places strin-
first such components were demon- gent demands on the bandwidth
strated to extend these transceivers and energy efficiency of data-center
to 112 Gb/s. At ISSCC 2020, a 56-Gb/s interconnects, spurring the develop-
DAC/ADC-based transceiver, a 100-GBd ment of several 200–400-Gb Ethernet
DAC-based transmitter, and the first standards. Within the rack, much of
descriptions of complete 112-Gb/s the interconnect bandwidth is pro-
PAM-4 long-reach transceivers in 7-nm vided by electrical links over copper
CMOS will be presented. Xilinx will interconnects, and optical intercon-
describe a 112-Gb/s PAM-4 transceiver nects are increasingly used to bridge
for long-reach copper interconnects longer distances. Silicon-photonics-
employing a 36-way, time-interleaved, based solutions are of particular inter-
56-gigasamples/s, 7-b ADC. MediaTek est for low-cost 50+ -Gb/s/m optical
will present a complete four-lane, transceivers. Furthermore, multilevel
112-Gb/s DAC/ADC-based transceiver. modulation schemes, such as PAM-4,
1,000 2007
2008
2009
2010
Data Rate (Gb/s)
100 2011
2012
2013
2014
2015
10
2016
2017
2018
1
2019
2020
5 50
Process Node (nm)
FIGURE 13: Data rate versus process node and year.
1,000
Other
Power Efficiency (mW/Gb/s)
ISSCC 2020
100
10
1
0.1
0 20 40 60
Channel Loss at Nyquist (dB)
FIGURE 14: Transceiver power efficiency versus channel loss.
improve the tradeoff between circuit
bandwidth, power consumption, data
rate, and optical-link range compared
with NRZ optical signaling. Since many
such modules are packed side-by-side
in networking and computing infra-
structure, low power consumption
is required to prevent the equipment
from overheating. The highly inte-
grated silicon-photonic approaches
presented at ISSCC 2020 will address
this need by communicating at 50–
100 Gb/s across each fiber using
PAM-4 modulation with low-power
consumption, reducing the need
for expensive cooling and pushing
100
90
80
70
60
Cores
classical discrete implementation
toward obsolescence.
Intel will describe a PAM-4 micror-
ing-based optical transmitter using
a 3D-integrated silicon-photonic and
CMOS circuit assembly with a robust
112-Gb/s operation. The thermal vari-
ability and nonlinearities that usually
plague such modulators are addressed
with nonlinear equalization and closed-
loop thermal control. STMicroelec-
tronics will demonstrate a transceiver
for the IEEE P802.3bs 200GBASE-DR4
standard. The four-channel electro-
optical transceiver provides an aggre-
gate bandwidth of 200 Gb/s using
a 55-nm BiCMOS technology that is
3D-assembled onto a silicon-photonic
front-end IC through copper pillars.
Data-rate scaling of coherent optics for
longer-reach optical interconnects is
also being highlighted at ISSCC 2020.
NTT will demonstrate a four-chan-
nel Mach-Zehnder modulator driver
capable of transmitting 640 Gb/s over
a single fiber, using dual-polarization
32-QAM modulation while consuming
only 1.4 pJ/b.
Continuing to aggressively scale
the I/O bandwidth is essential for the
industry, but the tradeoffs among
bandwidth, power, area, cost, and
re­­liability are extremely challeng-
ing. Advances in circuit architecture,
interconnect topologies, transistor
scaling, and integrated silicon pho-
tonics are changing the way that I/O
will be done during the next decade.
The most exciting and promising of
these emerging technologies for elec-
trical and optical interconnects will

50 be highlighted at ISSCC 2020.

40
Digital Systems: Digital Architectures
30 and Systems
20
10
Subcommittee Chair: Thomas Burd,
Advanced Micro Devices, ­Santa 
1 Clara, California
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Year ISSCC 2020 features a plethora of flag-
ship industry processors covering
FIGURE 15: Core-count trends (the red diamonds designate a multichip module). servers, desktops, mobile applica-
tion processors (APs), and automotive
processors ranging from 28- to 7-nm
CMOS. Additionally, there are invited
10,000
industry papers on graphics process-
ing units (GPUs) (a first for ISSCC),
a field-programmable gate array, an
Clock Frequency (MHz)

industry full-3D mobile processor, and

1,000 a next-generation, high-performance
ARM core. The trend continues to
exploit multichip integration technolo-
gies to drive the core count and on-die
100 cache (Figure 15).
The computational performance of
mobile AP SOCs historically grew as
silicon process technology advanced
10 (Figure 16). AP SOCs continue to gain
more features, including 5G modems,
94

96

98

00

02

04

06

08

10

12

14

16

18
20
19

19

19

20

20

20

20

20

20

20

20

20

20
20

Year
multimedia intellectual-property cores
(Figure  17), and accelerators on chip
FIGURE 16: Clock-frequency-scaling trends. to enhance functionality (Figure  18).

16 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Mobile phones are receiving more
camera sensors, which drives additional
complexity onto SOCs (Figure 19). Dedi-
cated neural-network accelerators exe-
cute machine-learning functions faster
and with higher energy efficiency
than generic CPUs and GPUs. Neural-
network processing units (NPUs) will
be adopted in most future AP SOCs,
establishing an important direction
in which an efficient software solu-
tion utilizes heterogeneous computing
combining CPUs, GPUs, and NPUs. On-
device training features continue to be
incorporated for private-data security
and device personalization.
Wired and wireless links continue
to increase in bandwidth, with a trend
of 10 times higher data rates every
five years (Figure 20). The changes are
modest this year at ISSCC 2020 rela-
tive to last year. mm-wave and massive
efficiency and performance, lowering PVT margins and enabling circuit-
the cost/design effort, and enhancing driven, chip-level performance gains.
security. Classic technology scaling A trend toward application-specific
has slowed, and circuit-design efforts accelerators is leading to the devel-
are exploiting technology features opment of new circuit techniques
such as body biasing and passive- that benefit a range of emerging ap­­
device ­advancements to enable circuit plications, including navigation in
innovation. In addition, variation mit- microrobotics, deoxyribonucleic-acid-
igation has become a major trend in sequencing engines, and annealing
digital circuits to improve robustness processors for solving large combina-
and power efficiency across process, torial problems. Some of these accel-
voltage, and temperature (PVT). Spe- erators leverage compute-in-memory
cifically, all-digital sensors and adap- (CIM) strategies, while others rely on
tive (clocking) techniques continue to circuit operation in nonconventional
be proposed to mitigate these effects modes/domains, including time-and
on chip, with the goal of reducing the charge-domain computation.
10,000
Transistor Count (Millions)

MIMO technologies are being actively

studied to realize 5G communication.
1,000
The first 5G mobile device was com-
mercialized in 2019. The explosion
of Internet of Everything (IoE) devices 100
will require the evolution of narrow-
band, wide-area networks.
10

Circuits for Hardware Security

With the growing risk and cost of infor- 1
mation theft, hardware-implemented 14
92

94

96

98

00

02

04

06

08

10

12

16

18

20
20
19

19

19

19

20

20

20

20

20

20

20

20

20

20
security has become a common circuit Year
component. Alt­hough the focus on
cryptographic implementation contin- FIGURE 17: Chip-complexity-scaling trends (the red diamond designates a multichip module).
ues, cost-effective physically unclon-
able functions (PUFs) (Figure  21) are
now a focus area in, for instance, smart
400
cards, consumer devices, and automo-
tive applications. True random-number 350
generators are also commonly lever-
aged to strengthen secret-key genera- 300
tion in cryptographic applications.
Cache Size (Mb)

250

Digital Systems: Digital Circuits 200

Subcommittee Chair: Edith Beigne, 150

Facebook, Menlo Park, California 100
The demand for higher performance
across ubiquitous, connected, and 50
energy-constrained platforms, rang-
ing from the IoE to cloud data centers, 0
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
continues to drive innovations in all Year
CMOS digital-circuit building blocks,
with the goals of improving energy FIGURE 18: On-die cache-size trends (the red diamonds designate a multichip module).

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 17

 OpenGL OpenGL/VG/MAX
Graphics (ES1.1) (ES2.0) AR VR Vulkan

VGA WVGA SXGA WQXGA /WQXGA+ WQXGA /WQXGA+ WQXGA /

Display at 60 f/s at 60 f/s at 60 f/s at 60 f/sx2 (VR) WQXGA+at 120 f/s

Camera 5–8 M 10 M 16 M 20 M 24 M 12 MxDual 16 MxDual 80 M

360° VR 3D Depth/AR Triple

Image/Video H.264/AVC H.264/AVC H.264/AVC H.264/MVC H.265/VP9 H.265/VP9 AV1

(VGA) (D1) (Full HD) H.264/SVC HDR HDR10+
Audio WMA Dolby DSD TWS
AAC AAC Plus Dolby 5.1 TrueHD/Digital+ Dolby Atmos Truly Wireless
Accelerator SMID Multicore Heterogeneous Neural-Net 5 TOPS
FPU Multicore (2–4) (4–8) Multiprocessing Processor
Downlink LTE-A LTE-A 5G
UMTS HSPA HSPA+ LTE LTE-A
(Mb/s) 0.4–2 1.8–7 7–42 100 150–750 1,600 2,000 5,000
CPU (MI/s) 300 500 800 2,400 6,000 12,000 13,000 19,000 22,000
500 800 2,400 6,000 12,000 100,000 112,000 162,000 180,000

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

FIGURE 19: AP trends in smartphones. OpenGL: Open Graphics Library; VG: vector graphics; MAX: media acceleration; AR: augmented
reality; VR: virtual reality; VGA: video graphics array; WVGA: wide VGA; SXGA: super extended GA; WQXGA: wide quad-extended GA;
fps: frames per second; AVC: advanced video coding; HD: high definition; MVC: multiview video coding; SVC: scalable video coding; HDR:
high dynamic range; AV1: Alliance for Open Media Video 1; AAC: advanced audio coding; WMA: Windows Media Audio; DSD: direct-
stream digital; TWS: true wireless stereo; FPU: floating-point unit; SIMD: single instruction, multiple data; TOPS: tera operations;
UMTS: universal mobile telecommunications service; HSPA: high-speed packet access; MI/s: million instructions per second; M: megapixel.

There is a recent movement toward

Data Rates Over Time Short Links, 1 Mb/s making these digital LDOs synthesiz-
100-Gb Ethernet 400-Gb Ethernet able, reducing the design effort and
100 Gb LAN, 10 Mb/s easing portability. Another trend is
10-Gb Ethernet IEEE 802.11ax toward hybrid LDOs that incorporate
10 Gb USB 3.0
PCI Express the best features of analog and digital
IEEE 802.11ad 5G
USB 2.0 IEEE 802.15.3c designs. Figure  22 shows the conver-
1 Gb
IEEE LTE-A
Data Rate (Hz)

UWB sion efficiency and current density of

IEEE 802.11ac Cellular, 100 Mb/s
100 Mb IEEE 802.11ag 802.11n these integrated voltage regulators,
IEEE 802.11b LTE which continue to improve.
HSPA
10 Mb
USB 1.0 HSDPA
Synthesizable Digital PLLs
1 Mb IEEE 802.11 WiMAX
for Low-Jitter Applications
3G R99/EDGE PLL trends include the migration from
100 Kb
analog to digital to include more function-
GSM
GPRS ality, cope with variability, and ease
10 Kb
1995 2000 2005 2010 2015 2020 scaling to finer geometries. Demand
Year for compact, low-jitter PLLs is increas-
ing. The use of more automated digital
FIGURE 20: Data-rate trends in wired, wireless, and cellular communication. UWB: ultrawideband; design flows (such as synthesis and
GSM: Global System for Mobile Communications; GPRS: general packet radio service; HSDPA: high- automated placement and routing) dra-
speed-downlink packet access; WiMAX: Worldwide Interoperability for Microwave Access. matically reduces development costs
but can degrade the jitter, requiring
Integrated Voltage Regulators even inductor-based buck-voltage new compensating techniques. Figure 23
At ISSCC 2020, energy reduction re­­ regulators (LCVRs) are integrated in highlights the metrics for PLLs and
mains a top priority as power density scaled process nodes to enable faster digital PLLs (DPLLs) published at ISSCC
continues to increase. ­Voltage regula- and fine-grain dynamic voltage and over roughly the past 10 years. The plot
tors, while traditionally being off chip, frequency scaling (DVFS) of individual shows the relationship between the
have increasingly been integrated on functional blocks. In turn, the low reference (input) frequency and FOM,
chip to reduce cost. Low-dropout (LDO) voltages supported in DVFS systems demonstrating the tradeoff between
linear regulators, switched-capaci- necessitate a move from analog-based cost (a higher reference frequency) and
tor voltage regulators (SCVRs), and LDOs to digital implementations. overall PLL performance.

18 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Machine Learning and AI
14,000 10
Subcommittee Chair: Marian Verhelst,
KU Leuven, Heverlee, Belgium 12,000
1
Owing to the worldwide trend of deep-
10,000
learning enthusiasm in recent years,

Bit Error Rate

ISSCC 2020 has established a dedi- 0.1

Area/Bit (F2)
8,000

(%)
cated subcommittee on machine learn-
ing and AI. As deep neural networks 6,000
0.01
succeed in achieving better accuracy
4,000
in a wide variety of tasks, their com-
0.001
putational complexity rises. For data 2,000
center, mobile, and IoT workloads, this
results in continuous demand for more 0 0.0001
2013 2014 2015 2016 2017 2018 2019 2020
energy-efficient and higher-through- Year
put neural-network computing. This
year’s submissions have targeted those FIGURE 21: Area/bit and bit-error-rate trends for the PUFs published recently at ISSCC. F2:
objectives across a broad power spec- feature squared.
trum, ranging from 0.5-nW always-
on accelerators to 276-W data center efficiency. A particular challenge
AI processors. in this context is to combine the
It is important to note that the met- exploitation of sparsity with in-
rics that matter at the system level are memory computing, a topic that 100
energy/inference and inference/s for will also be addressed. 95
a specific task and a given inference 3) At ISSCC 2020, it can be noted, in 90

Peak Efficiency (%)

accuracy. This year’s submissions again
significantly push the state of the art of
these efficiency and throughput num-
bers by combining multiple enhance-
ment techniques in tandem within a
single chip, implemented in the most
advanced technology (Figure 24):
1) Support for different levels of
computational precision is now
almost omnipresent to efficiently
allow multiple tasks. In addition
to fixed-point accuracies between
2 and 8 b, some architectures sup-
port floating-point (FP)8 and FP16
for training as well as pixel-ma-
nipulation workloads.
2) It is clear that the exploitation of
general, that machine-learning pro- 85
80
cessors are increasingly realized in
75
the most advanced technology, with 70
chips exploiting 7 and 12 nm. 65
LDO
As different chipsets are often char- 60
SCVR
acterized on a different set of tasks, 55 LCVR
network topologies, and accuracy lev- 50
0 10 1,000 100,000
els, comparing the true system-level Current Density (mA /mm2)
benchmarking metrics, such as energy/
inference and inference/s, is not always
straightforward. It is, therefore, inter-
esting to look at the achieved low-level FIGURE 22: The integrated voltage regula-
metrics of operations/s and energy/ tors (large LDO symbols represent 2020
operation within the neural network, papers).
–250
FOM10*(Power/1 mW*Jitter/1 ps)

sparsity has become a common –245

log M)
theme; it boosts throughput be- –240 = 10* ref/10
0 F
tween two and four times and en- –20 ps*
–235 M T = Jitter/1
F o *
ergy efficiency up to an order of –230 mW
magnitude. In fact, more than 50% wer/1
o
–225 (P
of the techniques at ISSCC 2020
–220
specifically leverage input, out-
–215 200
put, and/or weight sparsity as one T =–
of their key innovations. We fur- –210 FoM Pre-2013 2013 2014 2015
ther see an increase in the num- –205 2016 2017 2018 2019 2020
ber of approaches concerned with –200
10 20 40 80 160 320 640
multibit, in-memory computing, Fref (MHz)
gradually perfecting resolution
and accuracy as well as energy FIGURE 23: PLL and multiplying-delay-locked-loop trends. FoMT: FOM with tuning.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 19

 technique and a synergetic on-
Continuing to aggressively scale the I/O die scheme
bandwidth is essential for the industry, but the ■■ An 8.5-Gb/s/pin, 12-Gb LPDDR5
tradeoffs among bandwidth, power, area, cost, synchronous DRAM with a hybrid
bank architecture, skew-tolerant
and reliability are extremely challenging. and low-power schemes, and speed-
boosting techniques
■■ A 128-Gb, 1-b/cell, 96-word-line-lay-
as illustrated in Figure 25 for new data- (MAC) operations in 7-nm SRAM as er 3D flash memory to improve ran-
points from ISSCC 2020 compared to well as in a leading-edge, 22-nm resis- dom-read latency with t PROG = 75 ns
the state of the art in 2018 and 2019. tive RAM (ReRAM). In dynamic RAM and t R = 4 ns
Yet one should be well aware that (DRAM), the performance of high- ■■ A 32-Gb/s, digital-intensive, single-
these tera operations (TOPS)/W and bandwidth memory evolution (HBM2E) ended PAM-4 transceiver for high-
TOPS/s are strongly dependent on the is extended to 640 GB/cube and speed memory interfaces with a
exercised neural-network topologies, 8.5 Gb/s for low-power double data two-tap, time-based decision-feed-
computational precision, and network rate 5 (LPDDR5) components. For back equalizer
sparsity. Going forward, as the field NAND, the lowest latency is reported ■■ An 8-nm, 18-Gb/s/pin graphics dou-
matures, we believe that a common as well as a quad-level cell NAND with ble-data-rate type-six synchronous
benchmarking methodology must be the highest program bandwidth ever dynamic random-access memory
established, accounting for the appli- publicized. For span-transfer-torque (GDDR6) PHY with a transceiver-
cation context. But, without any doubt, magnetic RAM (STT-MRAM), the high- bandwidth extension and receiver-
the clever combination of sparsity, vari- est read bandwidth ever is shown as training technique
able precision, and in-memory comput- well as the first near-memory STT- ■■ A 22-nm, 2-Mb ReRAM CIM macro
ing technologies enables continued MRAM. The growing number of papers with 121–128 TOPS/W for multibit
enhancement of deep-learning proces- on high-speed memory interfaces MAC computing for tiny AI edge
sor efficiency and throughput. emphasizes the trend to push mem- devices
ory bandwidth limits further. ■■ A 22-nm, 1-Mb, 1,024-b read and
Memory Papers of note at ISSCC 2020 include near-memory-computing, dual-mode
the following: STT-MRAM macro with a 42.6-GB/s
Subcommittee Chair: Jonathan ■■ A 5-nm, 135-Mb SRAM in extreme read bandwidth for security-aware
Chang, TSMC, Hsinchu, Taiwan ultraviolet lithography (EUV) and mobile devices.
The demand for high-density, high- high-mobility-channel FinFET tech-
bandwidth, and low-energy mem- nology, with metal coupling and SRAM
ory systems continues to grow charge-sharing, write-assist cir- Scaling in SRAM continues, and the
­everywhere, from high-performance cuitry schemes for high-density first 5-nm FinFET EUV SRAM is being
computing to SOCs, wearables, and and low-VMIN applications presented. Innovations in SRAM sup-
the IoT. ISSCC 2020 presents the first ■■ A 351-TOPS/W and 372.4-GOPS CIM port high densities, CIM, high energy
5-nm FinFET static random-access SRAM macro in 7-nm FinFET CMOS efficiencies, and applications with
memory (SRAM). CIM boosts the per- for machine-learning applications very low latency requirements. Shift-
formance and energy efficiency of ■■ A 1.1-V, 16-GB, 640-GB/s HBM2E ing computation inside the memory
multiplication-and-accumulation DRAM with a data-bus-extension array (CIM) is a leading approach

System-Level
Benchmark
Low-Level
Benchmark INT1 INT2 INT4 INT8 FP8 FP16 Energy/
Inference
Strongly Dependent On

Adaptive Precision
Keyword Spotting at 93, 6%
Energy/
Operation
Sparse I/O/Weight Sparsity Dense Inference/s ImageNet at 80%
Adaptive Sparsity ResNet50
MobileNet
Operations/s InceptionV3
7 nm 12 nm 28 nm 40 nm 65 nm Inference
Accuracy at ...
Silicon Technology
(Task, Data Set)

FIGURE 24: Various parameters impacting the low- and system-level benchmarking metrics. INT: integer.

20 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

enabling breakthroughs in energy
efficiency and throughput. Four SRAM 1.E+3
(with CIM) papers are being presented,
with the potential of enabling further

Energy Efficiency (TOPS/W)

breakthroughs for AI and deep-learn- 1.E+2
ing applications, featuring low-power 16 bit
and/or high-performance operation; 8 bit
high-accuracy, in-memory, multibit 1.E+1 4 bit
MAC operation; and the ability to run 1 bit
forward as well as backward calcula- 2019 16 bit
tions for inference and training. Fig- 2019 8 bit
1.E+0
2019 1 bit
ure  26 shows the SRAM bit-cell area
2020 8 bit
and VMIN scaling trend.
2020 FP8
1.E–1
High-Bandwidth and Low-Power 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6
DRAM Throughput (GOPS)
To keep pace with the ever-increas-
ing performance requirements in FIGURE 25: Deep-learning processor throughput and efficiency. GOPS: giga
various applications from mobile to operations/s.
supercomputing, DRAM continues
to scale in density, form factor, and
bandwidth. ISSCC 2020 will include 0.999
1 1.2
benchmarks for the latest interface
standards, e.g., an 8.5-Gb/s LPDDR5 0.525 1
1.00 0.346
for high-speed mobile and a 640-GB/s 0.9
0.85
HBM2E for the highest performance 0.242 0.8
Bit Size (µm2)

applications (cloud and AI). Three 0.171 0.75

VMIN (V)
0.127
papers focus on improvements for 0.1 0.6
0.081
very-high-speed interfaces, such as 0.092
0.073
a PAM4 32-Gb/s transceiver and an 0.05 0.4
0.04
18-Gb/s GDDR6 PHY. Figure 27 illus-
trates DRAM bandwidth scaling over 0.027 0.2
the past 12 years. 0.021
0.01 0
Nonvolatile Memory 90 65 45 40 32 28 22 20 16 14 10 7 5
During the past decade, significant Technology Node (nm)
investment has been put into the
FIGURE 26: The bit-cell area and VMIN scaling trend for SRAM.
emerging-memories field to find an
alternative to floating-gate-based non-
volatile memory (NVM). The emerging
NVMs, such as phase-change memory 1,000 DDR3
(PCM), ferroelectric RAM (FeRAM), HBM
DDR4
STT-MRAM, and ReRAM, exhibit the DDR5
Data Bandwidth (GB/s)

potential to achieve a high cycling GDDR3

capability and lower power per bit in 100 GDDR5
GDDR(x)
read/write operations. At ISSCC 2020, GDDR6
a 22-nm, 1-Mb STT-MRAM macro dem- LPDDR(x) LPDDR2
onstrates a high read bandwidth LPDDR3
10
of 42.67 GB/s, while a 4-b/cell NAND DDR(x) LPDDR4
improves the write bandwidth up LPDDR5
to 30 MB/s. Figure  28 highlights the WIO2
achievement of MRAM read bandwidth HBM
1
HBM2
as well as improvement of the 4-b/cell 2008 2010 2012 2014 2016 2018 2020
NAND flash write throughput. Such Year
high densities are achieved through
advancements in 3D vertical bit-cell FIGURE 27: DRAM data-bandwidth trends. WIO: wide I/O.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 21

stacking and multibits (2–4 b) per bit- which achieves an 8.4-Gb/mm 2 area life interference and under stringent
cell technologies. Figure  29 presents capacity. On the other hand, fast-speed power and size constraints. These new
the trend in NVM capacity. 3D NAND with a 75-ns program time SOCs and corresponding techniques
and 4-ns read latency was developed. for wireless power/data transfer pave
NAND Flash Memory With a flexible suspend operation for the way toward robust microdevices
NAND flash memory continues to program and erase, a smaller random- that involve direct sensing, multisen-
advance toward a higher density and read latency of fewer than 50 ns is sor fusion, and implantable closed-
lower power, resulting in low-cost stor- achieved. Figure  30 describes the loop sensor/actuator systems. These
age solutions that replace traditional observed trend in NAND-flash capaci- advancements enable multimode phys-
hard disks with solid-state disks. In the ties at ISSCC during the past 20 years. iological recordings from nearly every
semiconductor industry, 3D-memory major organ system.
technology has been the mainstream Innovative Topics: Medical The state of the art in biomedical ICs
for NAND flash memory in mass pro- and systems is being advanced at ISSCC
duction. At ISSCC 2020, there are two Subcommittee Chair: Chris Van Hoof, 2020, with miniaturization, higher
papers demonstrating improvement IMEC, Leuven, Belgium sensitivity, higher dynamic range, and
of the write bandwidth of 4-b/cell, 3D As illustrated during ISSCC 2020, sen- interference mitigation presented as
NAND flash at 1-Tb capacities. One is a sor and actuator systems for on-body major trends in implantable and in
92-stacked-word-line, 3D vertical NAND wearable and in-body implantable vivo diagnostic devices at the same
(VNAND) flash memory featuring 5G use continue to evolve toward more time that power efficiency continues
technology with 1.2-Gb/s high-speed robust, functionally complex, and to improve. High-dynamic-range sens-
interfaces. Another exhibits a 30-MB/s energy-efficient solutions as well as ing systems (2100 dB) improve toler-
program throughput utilizing the highly closed-loop operation. Wearable and ance to large amplitude interference and
area-efficient technology of peripheral implantable SOCs record weak biopo- motion artifacts, while new techniques
circuits under the memory cell array, tential signals in the presence of real- are introduced to sense physiological

10,000
Cond. >1 Mb
ISSCC, VLSI
ASSCC (2001–2017)
FeRAM STT-MRAM
(ISSCC’09) (ISSCC’17) r
tte
Be
eMRAM VNAND-SLC
1,000
(ASSCC’07) (ISSCC’18)
ReRAM
MRAM (ISSCC’11)
(ASSCC’06)
Write Bandwidth (Mb/s)

FeRAM, MRAM ReRAM

(ISSCC’06) (ISSCC’11)
(SLC, VNAND-TLC
100 NAND-SLC ISSCC’20) (ISSCC‘19)
(ISSCC’08)
VNAND-TLC
NAND-MLC (ISSCC’16,’17,’18)
(ISSCC’14)
VNAND-TLC VNAND-QLC
(ISSCC’15)
VNAND-QLC STT-MRAM
10 PCM (ISSCC’18) (ISSCC’20)
(ISSCC’07,’10)
PCM
(ISSCC’11) eNOR SG-MONOS
(ISSCC’07) (ISSCC’15)
NOR
(ISSCC’05,’07)
1
100 1,000 10,000
Read Bandwidth (Mb/s)

FIGURE 28: A comparison of read/write bandwidth for NVMs. VLSI Circuits: Symposia on VLSI Technology and Circuits. SLC: single-level cell;
TLC: triple-level cell; MLC: multilevel cell; eMRAM: embedded MRAM; PCM: phase-change memory; SG-MONOS: split-gate metal-oxide–nitride-
oxide–silicon; QLC: quad-level cell; NOR: an inverted NAND; eNOR: embedded NOR.

22 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

signals, such as photoplethysmograms
and electrocardiograms. Miniaturiza-
tion combined with a high level of
integration enables minimally invasive
implants with low tissue displacement
for interfacing with the body. Multi-
modal physiological sensors have the
potential to offer improved monitoring
and diagnosis of a number of chronic
conditions. The form factor of a low-
cost, easy-to-use wearable device will
enable continuous monitoring of mul-
tiple vital signs, facilitating health
tracking outside the hospital. These
advances offer tremendous market
potential in the medical and consumer
market spaces.
Innovative Topics: Imagers
Subcommittee Chair: Chris Van Hoof,
IMEC, Leuven, Belgium
CMOS image-sensor business remains
one of the fastest-growing segments of
the semiconductor industry, expected
to reach US$18 billion in 2024, up
from US$11.8 billion in 2018. Image
sensors are essential components in
mobile devices and are found in many
consumer-electronics products. Strong
demand for automobile driver assis-
tance and autonomy propels progress
in time-of-flight sensors as well as
high-performance 2D imagers. Backside
illumination and 3D-stacked process-
ing offer improved performance with
increased on-chip functionality and new
features integrated at the pixel level.
At ISSCC 2020, four of the 10 image
sensors were designed for direct and
indirect time-of-flight imaging. Prog-
ress has been made in spatial and
depth resolution compared to previ-
ous designs, leading to a longer range
and higher accuracy. In Toshiba’s lidar
chip, circuit optimizations facilitate a
2# higher channel density in the same
die size. Four other image sensors
being presented at ISSCC 2020 target
mainstream applications with improve-
ments in pixel size, global shutter, low
noise, and high dynamic range.
Samsung has scaled down the pixel
pitch to 0.7 nm while improving or
maintaining critical performance para­
meters. Robust backside-illuminated
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 23
global shutter pixels with –105-dB pa­­ Innovative Topics: Technology
rasitic-light sensitivity have been Directions
announced. Sony reports noise-level
improvements and selectable in-pixel Subcommittee Chair: Makoto ­Nagata,
gain without adding transistors. A sin- Kobe University, Japan
gle-exposure, 132-dB dynamic range Technology innovations bring the
that maintains a high signal-to-noise promise of enabling new system func-
ratio across the full range is presented. tionalities and substantially increasing
Finally, two image sensors are intended the efficiency of existing ones. Harness-
for low-power/low-data-rate applica- ing such innovations for solving tangi-
tions, with always-on imaging and ble real-world problems requires novel
event-based dynamic vision. Improve- system-level solutions. With a focus on
ments in the architecture and data con- envisioning the future, emerging trends
version have continued to drive down in technology directions presented at
power consumption while providing the ISSCC 2020 cover a wide range of topics,
necessary compression, image quality, including quantum engineering; embed-
and detection for targeted applications. ded NVM-based computing devices
10,000,000
NAND Flash 1.33 Tb
1,000,000
Cond. 1 Mb
ISSC, VLSI, ASSCC, IEDM 1 Tb
Storage Capacity (Mb)
100,000
32 Gb
8 Gb
10,000
ReRAM
4 Gb
PCM
1,000
128 Mb
FeRAM
100
10 MRAM
1
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Year
FIGURE 29: The memory-capacity trend for emerging NVMs. IEDM: IEEE Electron Devices Meeting.
1,000
100
MB/mm2
10 1 b/cell (SLC)
2 b/cell (MLC)
3 b/cell (TLC)
4 b/cell (QLC)
1
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Year
FIGURE 30: NAND flash-memory trends.

Multimodal physiological sensors have the
potential to offer improved monitoring and
diagnosis of a number of chronic conditions.
for next-generation AI architectures;
low-power circuits for IoT and health
technologies; and biomedical sensing,
stimulation, and harvesting. ISSCC 2020
features four sessions representing the
latest technological innovations in the
following areas.
Quantum Engineering
Quantum technologies are emerging
as a major multidisciplinary research
topic, including computing, sensing,
telecommunications, information tech-
nology, and security. Common to these
technologies are properties typical of
quantum mechanics, such as super-
position and entanglement. Recently,
engineers have developed techniques
to exploit these properties using solid-
state circuits, employed to control and
observe a growing number of quantum
devices. Since most quantum devices
must be operated at deep cryogenic
temperatures, circuits must also oper-
ate at those or comparable tempera-
tures to ensure compact, reliable, and,
especially, scalable systems. Lever-
aging more than 60 years of CMOS-
technology development, researchers
are increasingly engaged in cryogenic
CMOS (cryo-CMOS) circuits and systems
to fill this gap. Cryo-CMOS technologies
will serve a range of quantum devices
that can be used in several quantum-
engineering problems. ISSCC 2020 will
feature a session devoted to some of
these topics, including a cryo-CMOS
controller for spin and superconduct-
ing qubits and an integrated system for
the control of a double quantum dot
that is also integrated in CMOS.
Next-Generation Nonvolatile D
­ evices
Nonvolatile devices are enabling novel
architectures with improved energy
and area efficiencies. A relentless push
to intersect evolving AI applications
embodies larger-scale NVM-based CIM
implementations featuring neural-net-
24 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
work processors. The trend continues
this year with CIM support for multi-
bit inputs/weights/outputs and low-
power, parallel-data-path operations.
ISSCC 2020 highlights two ReRAM-
based energy-efficient silicon chips
using analog in-memory operation: one
with a reconfigurable dataflow and the
second with fast, parallel multibit com-
putation enabled by a signed-weighted
ReRAM array.
Low-Power Circuits for the
IoT and Health
The papers from ISSCC 2020 in this
area push the frontiers of lower-power
solutions in IoT and health applica-
tions. One paper presents an ultralow-
power IC designed for communicating
with commodity Wi-Fi transceivers via
backscattering. Another introduces
a nanowatt-class (54-nW) always-on
wake-up chip for general-purpose IoT
devices. A third describes an elec-
tronic nose with very accurate limit
of detection. In addition, advances in
silicon for 3D localization based on
magnetic-field-gradient sensing for
surgical implants is presented.
Biomedical Sensing, Stimulation,
and Harvesting
ISSCC 2020 includes innovative and
emerging biomedical systems for wear-
ables and implantable components for
timely medical intervention. The devel-
oping trends encompass advances in
implantable sensors and stimulators,
human-body coupled communication,
ambient energy harvesting, and novel
magnetoelectric effects for power and
data transfer. The technologies demon-
strate the promise to advance cancer
therapy, neurostimulation, retinal pros-
thesis, and diagnostic devices.
Summary
According to the Semiconductor Indus-
try Association, the industry gener-
ated US$468.8 billion in sales in 2018,
an increase of 13.7 percent compared
to 2017! In this environment, ISSCC
continues to be the premier technical
forum for presenting advances and
predicting trends in solid-state cir-
cuits and systems. Beyond this arti-
cle, a complete trends document will
be available at www.isscc.org. These
trends will be highlighted in papers
presented at the 67th ISSCC, being
held at the San Francisco Marriott Mar-
quis on 16–20 February 2020. Atten-
dance at ISSCC 2020 is expected to
be around 3,000. Corporate attendees
from the semiconductor and system
industries typically represent about
60% of attendees. We look forward to
seeing you there!
Acknowledgments
We would like to acknowledge the
ISSCC 2020 Technical Program Com-
mittee for providing original content
for this article and each of the 12
subcommittee chairs as referenced in
each of the trends sections for their
leadership role. Without their collec-
tive efforts, this article would not
have been possible.
About the Authors
Denis C. Daly (denis.daly@gmail.com)
is senior vice president of High-Perfor-
mance Data Conversion at Omni Design
Technologies and the press coordinator
for ISSCC 2020.
Laura C. Fujino (lcfujino@aol.com),
ISSCC director of publications and
presentations, is associated with the
Department of Electrical and Com-
puter Engineering at the University
of Toronto, Canada, where she is a
member of the Board of Advisors for
Engineering Science.
Kenneth C. Smith is a ­p rofessor
emeritus and serves as chair of the
Board of Advisors for the Division
of Engineering Science, University of
Toronto, Canada. Since 1975, he has
volunteered for ISSCC in various capac-
ities, including as a member of the
Program Committee, in press-related
roles, and, for 40-plus years, as chair of
the Awards Committee.


Basics of Clock and
Data Recovery Circuits
Exploring high-speed serial links
T
he choice of clock
and data recovery
(CDR) architecture
in serial links dic-
tates many of the block-
level circuit specifications (specs).
Block-level specs ultimately determine
the energy efficiency of the system.
Therefore, to design energy-efficient
serial links, it is important to under-
stand the basics of CDR operation,
CDR’s main performance metrics, and
the relationship between circuit-level
Digital Object Identifier 10.1109/MSSC.2019.2939342
Date of current version: 23 January 2020
IEEE SOLID-STATE CIRCUITS MAGAZINE
1943-0582/20©2020IEEE
parameters and system-level perfor-
mance metrics.
Basic Principles
High-speed serial links find applications
in many electronics devices where
gigabits per second of data must be
transferred over one or several lanes.
Figure  1 depicts some of these use
cases. In televisions, high-data band-
width (BW) must be delivered to the
integrated circuits that drive the pixels
on the display screen. In a smartphone,
e.g., the front and back cameras, touch
controller, memory, and USB connector
all deploy serial links.
Amir Amirkhany
A serial link consists of a transmitter
(Tx) and a receiver (Rx). Figure 2 shows the
typical building blocks of a high-speed
link. The Tx includes a clock source, such
as a phase-locked loop (PLL), serializer,
and driver circuit for driving the output.
The Rx comprises an analog front end, a
CDR circuit to recover a clock and sample
and recover the incoming data, and a
deserializer. The focus of this article is
the CDR circuit at the Rx in terms of three
main questions:
1) How can an Rx generate a clock
to sample the data?
2) What impacts the performance
of CDR?
W I N T E R 2 0 2 0 25
 Panel Front Back
Camera Camera

65 in Pixel Drivers
Rx Touch Display

Film

CPU

Tx
Controller
PCB
Memory

USB
(a) (b)

FIGURE 1: The high-speed links applications in (a) a television and (b) a smartphone. PCB: printed circuit board.

Rx that deploys a 100-ppm oscillator,

RN, PSIJ
Tx Rx
SER DESER
AFE
PLL CDR
RJ, DJ PSIJ ISI, XTALK RJ, DJ
FIGURE 2: The serial link building blocks. RJ: random jitter; DJ: deterministic jitter; PSIJ:
power supply-induced jitter; ISI: intersymbol interference; XTALK: cross talk; SER: serializer;
DESER: deserializer ; AFE: analog front end; RN: random noise.
3) How does a CDR spec impact the on design tradeoffs through the use
rest of the system, such as the Tx PLL of various design examples, will be
spec or the Tx and Rx noise budget? covered. The same notation as past
This article is an abridged version tutorials will be referenced where pos-
of a tutorial given at the ISSCC in Feb- sible, and readers are referred to the
ruary of 2019 [27]. In the past years, past tutorials for some of the detailed
there have been two other tutorials on derivations. In-depth information on
this topic. A tutorial in 2011  [1] spe- jitter definition and measurement is
cifically focuses on digital PLL-based included in [3] and may be used as
CDRs and includes in-depth analysis of a companion.
digital phase-interpolator-based CDRs, When considering CDRs, a fair
their theory of operation, and design question to ask is “Why not just include
examples. Another tutorial [2] covers at the Rx a clock source, such as a crys-
CDR fundamentals as well as various tal oscillator, that matches the Tx’s clock
CDR architectures. In this article, the source?” The answer is that all crystal
theory of operation, with an emphasis oscillators have limited accuracy. An
e.g., slips 100 unit intervals (UIs) in only
1 million bits. For a 10-Gb/s serial link,
that equals merely 0.1 s. Another practi-
cal reason is that a clock source may not
be available at the Rx side due to system
cost considerations.
Figure 3 depicts a basic CDR archi-
tecture. Data recovery mainly involves
techniques such as continuous-time
or decision-feedback equalization. In
this article, the focus is primarily on
the clock recovery portion. In particu-
lar, the article discusses how to gen-
erate a stable clock source for the Rx
(functionality) and how to maximize
the data recovery margin (quality).
The quality of data recovery is
directly related to jitter. Jitter refers to
the deviations of a clock or data wave-
form’s transitions from an ideal clock,
as shown in Figure  4(a). In some lit-
erature, jitter may be represented by a
jitter sequence diagram. Various jitter
measurement metrics, such as period,
cycle to cycle, and so on, have been
introduced over the years [4]. The spe-
cific metric of interest for CDR charac-
terization is the relative jitter between
the received data stream and recov-
ered clock at the Rx. Figure 4(b) depicts
a data stream with jitter and a recov-
ered clock with zero jitter. Because
clock transitions in this figure do not

26 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

track data transitions, the clock edge
may deviate from the center of the data
symbol, resulting in lost data recovery
margin. Conversely, if the clock tran-
sitions fully track data transitions, the
clock edge can always be centered with
respect to data transitions, leading to
the best data recovery performance. Full
jitter tracking is one of the major goals
of a good CDR circuit.
Jitter in serial links can be catego-
rized into three types: data dependent,
source, and CDR jitter. In Figure 2, data-
dependent, i.e., channel-induced, jitter
is caused by intersymbol interference
(ISI) or cross talk. Mitigating the impact
of data-dependent jitter is primarily
the domain of data recovery circuits.
The role of clock recovery circuits is
to suppress this jitter as much as pos-
sible in most CDR implementations.
Source jitter includes the effect of the
Tx PLL, clock distribution random jit-
ter (RJ) and deterministic jitter (DJ),
as well as Tx power-supply-induced
jitter (PSIJ). Source jitter is data inde-
pendent (to the first order), and the
role of clock recovery circuits is to
track this jitter as much as possible.
CDR self-generated jitter includes
the RJ and DJ from clock recovery
blocks, such as a voltage-controlled
oscillator (VCO) and charge pump as
well as Rx clock and data path PSIJ. A
good CDR creates only negligible self-
induced jitter.
One alternative architecture to a
CDR-based system is a forwarded-clock
system. In a forwarded-clock system,
the Tx forwards a clock to the Rx at
Ideal
Clock
Jittered
Clock
Jitter
Sequence
Data UI: Width of 1 b in NRZ or a Symbol in PAM4
(a)
FIGURE 4: (a) Jitter definition and (b) jitter tracking. NRZ: nonreturn to zero; PAM: pulse amplitude modulation.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 27
Mitigating the impact of data-dependent
jitter is primarily the domain of data
recovery circuits.
the expense of an extra lane. In many
implementations, the circuits between
the clock and data paths are matched
as much as possible to achieve maxi-
mum jitter tracking between the data
and clock. Figure 5 displays the block
diagram of such a system where for-
warded-clock frequency is half the
bit rate. In this type of system, data-
dependent jitter does not exist, source
jitter tracking can be maximized with
proper circuit architecture, and self-
generated jitter can be very small due
to the simplicity of the clock path in
the Rx. Forwarded-clock systems are
popular in many standards, such as
DDR2-5, MIPI D-PHY, and High-Defini-
tion Multimedia Interface, where one
Data Recovery
Input
Data
AFE
Clock Recovery
PD
FIGURE 3: A simple CDR architecture. PD: phase detector.
Data
Recovered
Clock
Data: 101010
Zero-Jitter Clock
Time Clock With Jitter Tracking
forwarded-clock lane can be shared
between multiple data lanes. However,
in many applications, adding the extra
lane may not be an option.
Main CDR Performance Metrics
To design a good CDR, it is impor-
tant to have metrics that can quantify
performance. Jitter tolerance (JTOL)
is one such metric adopted in many
standards [6]. JTOL is the measure
of how much sinusoidal source jitter
a CDR can tolerate at a given sinusoi-
dal frequency at a given bit error rate
(BER). JTOL includes the effects of ISI,
cross talk, data recovery performance,
and clock recovery performance. Fig-
ure 6(a) shows a typical JTOL graph.
Data Recovered
DESER Data
Samplers
Recovered Clock
Loop Filter
Lost Margin With
Recovered Zero-Jitter Clock
Data
1 1 1
0 0 0
(b)
At low jitter frequencies, a typical ensure proper domain crossing from To measure JTOL in a lab, the CDR
CDR should be able to track very the CDR to a CDR-independent clock is driven by an ideal Tx [typically a
large amounts of source jitter. In this domain. CDR’s jitter tracking generally BER tester (BERT)], and sinusoidal jit-
region, the practical tracking of jitter degrades at higher frequencies until it ter is injected at various frequencies
is limited by the depth of the data buf- becomes negligible and creates a floor at the Tx while the CDR BER is mea-
fer in the Rx data path provisioned to for the JTOL curve. sured. Jitter amplitude is increased
at every jitter frequency until the
measured BER falls below the target
Tx Rx threshold. Figure 6(b) depicts a typi-
cal JTOL measurement setup [4].
JTOL is employed to ensure that
SER DESER someone’s Rx works with someone
AFE else’s Tx. In other words, JTOL is
a system characterization method
and very important tool for setting
Match
specs in standards. Using JTOL, the
PLL Shared Tx designer can be tasked with guar-
anteeing that the Tx jitter at a given
Clock-Pattern frequency never exceeds the spec.
Generator Conversely, the Rx designer can be
AFE
tasked with making certain that
the receiver achieves target BER if
the transmit data stream meets the
JTOL spec. JTOL is easy to measure;
FIGURE 5: A forwarded-clock system.
however, it is practically impossible
to simulate at the transistor level
In-Band Out-of-Band at a very low BER. Another metric,
Jitter Jitter therefore, is required to guide the
Typically >1 UI clock recovery circuit design.
(S
Limited by FIFO ho The jitter transfer (JTRAN) function
uld J
Jitter Amplitude

Depth Above Tra TOL defines the ratio of the clock recovery’s
Sinusoidal

PHY Layer ck Ma
Ab sk output jitter to input jitter at a given
ov
eT
his sinusoidal jitter injection frequency.
Lin
Timing Margin e) JTRAN is a clock recovery characteriza-
Available for tion metric that does not include BER, is
Untracked easy to simulate at the transistor level,
Source Jitter Sinusoidal Jitter Frequency and is closely related to JTOL. JTRAN
(a) can be used to define parameters such
Jittery
as CDR BW and phase margin to guide
Data the design process. CDR is a feedback
Pattern Check/
BERT CDR system and is often nonlinear; none-
Error Count
theless, a linearized model can often
be used for qualitative analysis with
Frequency
satisfactory precision. Figure 7(a) shows
Jitter Amplitude (UIpp)

Generator
(Jitter Modulator) a typical JTRAN of a CDR. Again, at
low frequencies, all of the source jit-
Fail (BER > 10–x )
ter is transferred to the output of the
Pass (BER < 10–x )
CDR, while some frequency depen-
dence exists at the midfrequencies.
CDR BW is defined as the 3-dB BW of
Jitter Frequency the JTRAN curve, and jitter peaking
JTOL Measurement Setup (Casper) and peaking frequency are defined as
the peak of JTRAN and its associated
(b)
frequency, respectively. Although jitter
FIGURE 6: (a) A typical JTOL graph [6] and (b) a JTOL measurement setup [4]. FIFO: first in/ tracking is good for a CDR, high jitter
first out; PHY: physical; UIpp: unit interval (peak to peak). amplification (i.e., large jitter peaking)

28 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

can be detrimental, particularly for a
relay system where a cascade of CDRs
may be deployed. Figure 7(b) shows a
JTRAN measurement setup that con-
sists of a data generation instrument
with jitter injection capability (such as
BERT) and a spectrum analyzer [4].
As mentioned previously, JTOL
and JTRAN are closely related. Con-
sider a CDR with a timing margin of
T at a given BER when source jitter
is zero (Figure  8): This timing mar-
gin includes the impact of everything
(e.g., ISI, cross talk, CDR self-induced
jitter, and data recovery performance)
except for source jitter. Therefore, this
timing margin T is available for any
untracked source jitter:
JTOL( j~) = T data-dependent jitter and source jit-
JTRACK( j~)
= T .
1 - JTRAN( j~)
A note of caution with this equation.
It may be argued that, for better JTOL,
Jitter Peaking
0 dB
–3 dB
Jitter-Tracking BW
Sinusoidal Jitter Frequency
(a)
FIGURE 7: (a) A typical CDR JTRAN graph and (b) a JTRAN measurement setup [4]. CLK: clock; Gen.: generation.
∆
FIGURE 8: The JTOL and JTRAN relationship [2].
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 29
JTOL is a system characterization method and very
important tool for setting specs in standards.
it is desirable to increase the JTRAN
BW. This argument ignores the fact
that T in the equation is also a func-
tion of JTRAN BW because the CDR BW
has a direct impact on how much data-
dependent jitter gets suppressed.
To summarize so far, as we dis-
cussed in the first section, a good
CDR would filter as much of the data-
dependent jitter as possible, track
as much of the Tx data-independent
jitter as possible, and minimize its
own self-generated jitter. Increas-
ing CDR bandwidth will increase
ter tracking, and thus, it reduces the
impact of both source jitter and self-
generated VCO jitter [2]. Therefore,
the choice of the right CDR tracking
bandwidth is a balancing act between
–fmod
Clk/
Data fc
Gen.
CLKin
f3 dB
JTRACK
JTRAN
CDR
∆ ω PL
JTOL ( jω ) =
JTRACK ( jω )
∆ Assume ∆ = 0.5
=
1 – JTRAN ( jω )
data-dependent jitter filtering and
data-independent jitter tracking (and
self-jitter suppression). To find the
right balance, an accurate system-level
modeling is necessary.
CDR Design Tradeoffs
Figure 9 shows the block diagram of a
simple analog CDR. The phase detector
compares the transitions of the input
data sequence with the locally gen-
erated clock and creates up or down
signals. Because the phase detector’s
operation relies on data transitions,
input data often require transition
encoding schemes such as 8 b/10 b.
Figure  10(a) depicts the block dia-
gram of a Hogge phase detector [11]. For
every rising data transition, both the
DE and DR outputs create a pulse. For
Spectrum Analyzer
∆Pin
∆Pout
+fmod
PLL/ IN
CDR
CLKout
JTF (fmod) = ∆Pout/∆Pin
(b)
HJTRACK(s)
HJTOL(s)
ω PH logω
[Hanumolu]
 JTRAN can be used to define parameters
such as CDR BW and phase margin to guide
the design process.
the DE pulse, the timing of the rising
edge depends on the timing of data
arrival while the falling edge depends
on the clock rising edge. For a DR pulse,
the rising and falling edges depend
solely on clock edge timing. As a
result, subtracting the area under the
DE pulse from the area under the DR
pulse creates an output that is linearly
proportional to data versus clock edge
timing, i.e., the phase error, as dis-
played in Figure 10(b). When the CDR
locks, the data-to-clock-rising time is
equal to the clock’s half-period; there-
fore, data are sampled at the middle
of the UI.
A Hogge phase detector has several
limitations. First, most systems today
are low swing due to power consid-
erations. Having a low-swing signal
directly driving combinational logic
creates some challenges. Second, the
flip-flop clk-q output delay causes a
IUP
D UP
PD
DN
IDN
FIGURE 9: A simple CDR architecture.
D –π
CLK
(a)
FIGURE 10: (a) A linear phase detector [11] and (b) the Hogge phase detector’s response. KPD: phase detector gain.
30 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
systematic offset in the locking phase
and is better to be matched in the D
input of the DE logic. Third, the half-
cycle delay between the DE and DR
pulses creates DJ in the CDR output.
All of these issues can be solved by
proper circuit design, but designers
often opt for the simpler, but non-
linear, bang–bang (Alexander) phase
detector (described in the “CDR Archi-
tectures” section).
Figure 11 shows the phase-domain
model for the CDR with a linear phase
detector. Using this model, we can
derive a number of important ana-
lytical equations for the CDR that
will help us with understanding the
design tradeoffs:
H JTRAN (s) = 1 + sRC
1 + sRC + s 2
K VCO K PD I CP
~z = 1 ,
RC
VCO
CLK
R however, to maintain stability, we
C
DE
tdata t clk(0→1)
DR
t clk(0→1) t clk(1→0)
~ PL . 1
RC
~ PH . K VCO .K PD .I CP .R,
JTRAN BW . ~ ug . ~ PH,
U M = tan -1c m,
~ ug
~Z
Jitter Peaking . 8.686~ Z .
~ ug
In these equations, ~ Z , ~ PL, and ~ PH
are the zero, lower pole, and higher
pole frequencies, respectively, of the
JTRAN function and { M is its phase
margin. These approximations are
accurate when ~ PL % ~ PH .
To gain a sense of its design trad-
eoffs, let us design a 10-Gb/s CDR with a
tracking BW of 5 MHz. For calculations,
let’s assume a linear phase detector with
a gain of KPD = 1/(2pi), and a ring VCO
with a gain of KVCO = 16 GHZ/V. Table 1
lists the CDR BW, phase margin, peak-
ing, and zero frequency as functions of
choices for I CP, loop-filter resistance (R),
and capacitance (C). Note that the values
in Table 1 are obtained from accurate
, formulas rather than the approxima-
C
tions discussed earlier to maintain accu-
racy when the two poles of the system
are comparable.
In the first trial, for reasonable values
of 100 µA, 1 kΩ, and 60 pF for the CDR
components, the CDR BW significantly
exceeds the target spec. The simple, ana-
log CDR offers two knobs for reducing
the BW. We can reduce R by eight times;
must increase C while being conscious
of the required area. Although using
this knob gets us closer to the target
of a 5-MHz BW, the system requires
a large capacitor with considerable
+1
+π
ΦE
–1
1 α
KPD =
π
α Is the Transition Density
α = 0.5 for Random Data
(b)
peaking and marginally acceptable let us assume the up and down sig- bit (LSB) current digital-to-analog
phase margin. Alternatively, we can nals are binary (Table 2). Therefore, converter (DAC). But, in fact, it is
reduce I CP to 12 µA; however, we are the output current I OUT has a range slightly worse because of the cur-
left with large peaking and a modest of - 4I Unit   # I OUT   # +4I Unit , where rent subtraction. In any subtrac-
phase margin. It is only by using both I Unit   = 12 µA. Therefore, the block tion, although signals subtract, the
knobs together that we can achieve shown in Figure  12(a) is really a errors can add. For example, there
the target BW with good stability. We 2.5-GS/s, ~3-b, 12-µA least significant are exactly 19 UP/DN combinations
should remember, however, that if
any of these variables change due to
process, voltage, or temperature vari- Φ in Φe Φ out
ations, both the tracking BW and jitter – KPD ICP R + 1/(sC ) KVCO/s
peaking of the system would at least
increase proportionally.
Now, let us assume that the fourth (a)
configuration with 400-pF loop capac- HJTRAN(s)
itance and 12-µA charge-pump current
is acceptable. Let us now consider
Peaking
how difficult it is to create the 12-µA
charge pump current.
In most process nodes, a straight
10-G sample/sec charge pump is not
easy to implement. Alternatively,
ωz ω PL ω PH logω
log
the phase detector and the charge
pump can be parallelized to operate (b)
at a lower rate. A four-way parallel
system is shown in Figure 12(a). The FIGURE 11: A CDR analytical model [2]. ~ PL: zero frequency; ~ PH : lower pole frequency; ~ z:
higher pole frequency. ICP: charge-pump current.
output of the four-way system can
be described as
4
TABLE 1. THE ANALOG CDR BW AND PEAKING AS A FUNCTION OF
I out = / (UP[m]I UP[m] - DN[m]I DN[m]) COMPONENT VALUES.
m =1

4 ICP R C BW PM PK fz
+ / 1(UP[m]TI UP[m] - DN[m]TI DN[m])
44444444424444444443. NUMBER (μA) (Ω) (pF) (MHz) (0) (dB) (MHz)
m =1
Error
1 100 1,000 60 44 86 0.4 2.7
The terms TI UP and TI DN represent 2 100 125 400 8 61 2.5 3.1
a current mismatch in the parallel 3 12 1,000 60 7.4 64 2.2 2.7
charge pumps. Thus far, this article
4 12 1,000 400 4.9 85 0.5 0.4
has discussed a linear phase detec-
tor, but for the immediate argument PM: phase margin; PK: peaking; fz: zero frequency.

UP_EN
IUP IUP
D UP[3:0] IOUT D UP[3:0] Adder IOUT
PD PD or CODE[2:0]
+ +
DESER (1:4) R DESER (1:4) Major R
DN[3:0] DN[3:0] Vote
C C
2.5 Gb/s IDN IDN 4X
DN_EN
2X
1X
4 4
IOUT = (UP[m]IUP[m] – DN[m]IDN[m]) Code [2:0] = (UP[m] – DN[m])
m=1 m=1
(a) (b)

FIGURE 12: (a) A four-way parallelized PD and charge pump (CP) and (b) a four-way parallel CP with digital subtraction.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 31


TABLE 2: SOME UP/DOWN (UP/DN)
COMBINATIONS THAT RESULT IN
ZERO IOUT.
NUMBER UP[3:0]−DN[3:0]
1 4’b0000−4’b0000
2 4’b0010−4’b0001
3 4’b0100−4’b0001
4 4’b1000−4’b0001
5 4’b1001−4’b0110
that should create zero I OUT but due
to the error term, some can current
a positive IOUT and some can create
a negative IOUT. Similarly, there are
many ways to get IOUT = +IUnit and
IOUT = –1 IUnit. As a result, the overall
charge pump may not even be mono-
tonic with respect to UP/DN input
code if it is not designed carefully.
To simplify the design of the par-
allelized charge pump, some CDRs
move the subtraction logic to the digi-
tal domain, as shown in Figure 12(b).
This change relaxes the monotonicity
requirements on the charge pump and
greatly simplifies its design; however,
the digital logic will introduce some
latency into the loop. Some CDRs push
this idea further, using only the sign
of the final subtraction result and a
simple 1-b charge pump instead. This
operation is equivalent to a majority
vote, makes the system nonlinear,
JTRAN
10
0 20 ns
–10
–20
–30
105 106
Frequency
(a)
FIGURE 13: The effect of loop latency on the jitter-transfer function. (a) Jitter transfer functions for various loop latencies. (b) CDR BWs and
phase margins for various loop latencies.
32 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
and reduces the BW, but sometimes it
is a good tradeoff to make.
Thus far, we have neglected loop
latency in our CDR modeling; how-
ever, with the introduction of digi-
tal logic to the loop, which is often
implemented in the lower frequency
domain at the register transfer level
(RTL), we must be cognizant of the
effect of latency on the loop parame-
ters. The loop phase-margin equation
in the presence of loop latency of D is
U M = tan -1 c m - D~ ug .
~ ug
~Z
Therefore, loop latency becomes im­­
portant when D~ ug is not negligible,
e.g., for jitter-tracking BW of 5 MHz,
D % 30 ns. Figure 13 plots the jitter-
transfer function for various values
of loop latency. As shown, even loop
latencies in the nanosecond range
can noticeably change the system
phase margin and, consequently,
its jitter peaking. One nanosecond
is a pipeline stage for a 1-GHz syn-
thesized logic. Therefore, not many
pipeline stages are allowed for any
digital implementation.
To summarize this section, the sim-
ple analog CDR has many limitations:
a linear PD has mismatch issues and
other design issues. It requires a large
cap and small currents to ensure sta-
bility. In particular, the choice of loop
R = 1 KΩ, C = 400 pF, KVCO = 16 GHz/V
0 ns
10 ns
30 ns
107 108 109
resistor impacts both the BW and sta-
bility. Moving elements of the opera-
tion to the digital domain may relax
some design constraints, but it intro-
duces latency issues.
CDR Architectures
To address the limitations of analog
CDR, various architectures have been
developed. Each has its own benefits
and limitations, and the choice of archi-
tecture depends on power and perfor-
mance specs, as well as the process
node in which CDR is implemented.
Alexander (Bang–Bang)
Phase ­Detector
An Alexander phase detector is a non-
linear phase detector used in most
CDR implementations. Figure 14 shows
the block diagram. This phase detec-
tor takes two samples per symbol (bit)
period: a data sample (dn) and a cross-
ing sample (xn). When there is a transi-
tion in data sequence (dn ! = dn+1), the
xn sign determines whether the clock
is early or late. A CDR with this type
of phase detector locks onto the data
crossing point and “assumes” that the
optimal data sampling point is a half-bit
period away. This leads to a suboptimal
operation when the data eye shape is
not symmetric.
The bang–bang phase detector (BBPD)
is a nonlinear circuit; therefore, the
CDR loop gain and BW are dependent
KPD = 1/2 π, ICP = 12 µA,
D (ns) CDR BW PM (°)
(MHz)
0 5.4 85
2 5.8 82
4 6.2 78
6 6.7 75
8 7.4 71
10 8.3 67
(b)
 dn xn dn+1

D +1
dn+1
DL
xn –π +π ΦE
CLK
–1

dn
DE KPD = ∞

xn (Assuming Zero Jitter)

Useful Range = [–π, π ]
dn xn dn+1
CLK

FIGURE 14: The Alexander (bang–bang) phase detector.

on data jitter, and CDR stability should

be verified with different assumptions +1 + α
about jitter distribution. For a 50% +1 – α
+1
transition density, the BBPD gain can α
be expressed [1] by
–1 + α
1 –1 –1 – α
K PD = (Gaussian jitter),
v 12 dn xn dn+1 xn+1 dn xn dn+1 xn+1
(a) (b)
K PD = 1 (uniform jitter).
v 2r
FIGURE 15: The signal transition diagram for (a) an NRZ no-ISI and (b) an NRZ 1+ az−1 channel.
Because BBPD locks onto the data tran-
sition point, if channel ISI creates
deterministic deviations in the transi-
tion point from the half-symbol point, +1
the CDR can lock onto the suboptimal +2/3
phase or exhibit deterministic jitter. +1/3
The best way to analyze such issues is 0
with the help of the signal transition –1/3
diagram (or trellis) at the Rx input. Fig- –2/3
–1
ure 15 illustrates the trellis diagram for
dn xn dn+1 xn+1 Major Minor Intermediate
nonreturn-to-zero (NRZ) signals over
Transition Transition Transition
no-ISI and 1 + az -1 channels. Let us
consider the latter: the channel out-
FIGURE 16: Transition classification in a PAM4 system for BBPD-based clock recovery.
put at time n can be either +1 - a or
+1 + a if the data transmitted at time
n were +1 and the data transmitted also includes crossing slicers placed up/down generation would lock with a
at time n - 1 were -1 or +1, respec- at +a and -a . As the trellis in Fig- slight phase offset. This issue is more
tively. If the data bit for time n is +1, ure 15 shows, however, only the tran- pronounced in PAM4 Rxs, as shown
the channel output at time n + 1 can sitions from +1 + a to -1 + a and in Figure 16 [7]. Although the optimal
be only +1 + a or -1 + a, depending the transition from -1 - a to +1 - a crossing thresholds are at 0, !1/3,
on whether the transmitted bit at time pass through the half-UI point at the and !2/3, the right transitions should
n + 1 was +1 or -1, respectively. A +a and -a threshold, respectively. be selected for each slicing threshold.
loop-unrolled decision-feedback equal- The other two transitions (+1 - a to A CDR with an Alexander phase
izer with samplers placed at +a and -1 + a) and (-1 + a to +1 - a) pass detector has a natural oscillation
-a thresholds is often used at the the aforementioned thresholds at an frequency determined by its limit
front end to cancel the first postcur- offset from the midpoint. Therefore, a cycle. The period and amplitude of
sor ISI tap a. In such systems, the PD CDR utilizing all of the transitions for this oscillation is proportional to the

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 33

 ever, these CDRs gained popularity
In general, MM CDRs are not as robust only over the last decade as a low-
as oversampled CDRs and should be power alternative to oversampled archi-
deployed with care. tectures. The updated equation for an
MM CDR is given by

CDR loop latency. Figure  17 demon-
strates this relationship. When the
limit-cycle oscillation frequency falls
within or is close to the tracking
BW of the CDR, it adversely affects
the jitter peaking and CDR perfor-
mance. This issue can be addressed
by reducing the loop latency or add-
ing a feed-forward path to the VCO
with small latency, as discussed fur-
ther in this section.
The BBPD is effectively a two-times
oversampling system and doubles the
number of clock phases and front-end
samplers in the CDR. As the complex-
ity of serial links grows and especially
Φe (t)
D
up/dn
ΦCLK(t)
FIGURE 17: The effect of limit-cycle dependency on loop latency.
because designs started deploying
analog-to-digital converters at the
front end, the power overhead of a
two-times oversampled front end
have become prohibitive. Therefore,
lately, many designs have begun using
baud-rate CDRs instead.
Baud-Rate CDRs
Baud-rate CDRs take only one set of
samples per UI and, therefore, require
half the clock phases of BBPD-based
CDRs. A Mueller–Muller (MM) CDR is
the most popular form of baud-rate
CDR. The original paper that describes
the CDR algorithm dates to 1976; how-
Φe(t)
D of the algorithm are proposed in [7]
up/dn
ΦCLK(t)
Tx k = e k d k - 1 - e k - 1 d k
= y k d k - 1 - y k - 1 d k,
where the sampled received data are
y k = R m d mh(mT + x) and the sampled
error is e k = y k - d k h(x).
For an uncorrelated input sequence
dm, it can be shown that
E (Tx k) = E (d 2k) ([h (T + x) - h (-T + x)]) .
Therefore, the timing error is mini-
mized where the postcursor ISI tap
is equal to the precursor ISI. Fig-
ure  18 depicts one implementation
of an MM phase detector for an NRZ
link [16]. The implementation is a
sign-sign variation of the MM algo-
rithm and requires the VREF level to
be adjusted to match h0, the main
tap of the channel. Other variations
and [17] to tune the locking point of
the CDR in favor of the precursor
or postcursor ISI taps. In general, MM
CDRs are not as robust as oversam-
pled CDRs and should be deployed
with care.

CLK
VREF– + errm Error
– Sampler ERR = +1
DFF Dn–1
+VREF
ERRn Target
Sampling
+ errp Point
VREF+ – 0 ERR = –1
DFF

Phase Early: DN = 1 Dn
Data Dn –VREF
Data
Phase Late: UP = 1 ERR = +1
Sampler
CLK
Phase Error:
∆Tn UP DN
∆Tn = Dn × Dn–1 × (ERRn – ERRn–1)
+1 1 0
(a)
PD 0 0 0
Output Truth Table –1 0 1
(b)

FIGURE 18: An MM CDR implementation: (a) PD architecture and (b) early and late regions [16]. ERR: error.

34 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Proportional-Integral CDR
As discussed previously, in the sim-
ple analog CDR, the resistor R value
controls both the BW and stabil-
ity of the CDR loop. Therefore, to
reduce BW, we have to either reduce
R and increase C or reduce I CP . Fig-
ure 19 shows a redrawn model of the
analog CDR that is mathematically
equivalent to the model in Figure 11.
However, viewing the CDR in this
framework allows us to conceptu-
alize an alternative implementation
of a CDR where the proportional
and integral gains are independent
variables. Physically, this requires a
VCO that has two control inputs: one
directly driven from the phase detec-
tor and the other driven by the inte- The following are a few important
grator in the integral path. Figure  20 points to note, based on the equations
displays one example implementation in this section:
of this type of CDR [21]. The equations 1) Proportional gain (K P) determines
for the poles, zeroes, and BWs of this the jitter-tracking BW. It can there-
type of CDR are given as fore be used to trade off ISI-in-
duced jitter for source jitter.
1+ s 1 2) For a fixed K P, integral gain (K I) de-
~z
H JTRAN (s) = , termines open-loop ~ z; therefore,
1+ s 1 + s2 1
~ PL ~ PL ~ PH a lower K I increases the phase
~z =
KI , margin and reduces jitter peak-
KP ing. However, K I determines ~ PL
~ PL .
KI , as well, which sets the CDR’s loop
KP
time constant. As a result, a lower
~ PH . K P , K I increases the CDR locking time.
JTRAN BW . ~ ug . K P , 3) Also, K I is the term that makes the
CDR loop second order; ­therefore,
U M = tan -1c m.
~ ug
~Z CDR cannot track frequency change

KPDICPRKVCO
Φ in Φe Φout
1/s In simple-analog CDR, R controls
both BW and stability.
KPDICP(1/C )KVCO 1/s
Reducing BW Requires:
Small R and Large C
(a) Or Small I
Can Re-Architect the Loop to
Have Independent Knobs:
KP Proportional Path: KP
Φ in Φe Φout Integral Path: KI
1/s
With the proper VCO
Kl 1/s architecture, it will have a different
set of knobs to optimize.

(b)

FIGURE 19: (a) An equivalent model of an analog CDR. (b) The model of a proportional-integral CDR.

20-GHz LC-OSC
Samplers
Phase- 20-Gb/s, 2-b Microstrip
Detection Recovered
40 Gb/s UP0+
Logic Data DN0–

CK1 CK0 UP1+ CK2 CK3

Four-Phase, Proportional UP1/DN1 DN1–
20-GHz Clock Control Path UP0/DN0
20-GHz
QVCO INT-ctrl

Integral
Proportional Path
Control Path
Directly From PD
Vbias
CPINT

Vbias_q
Integral Path (No R)

FIGURE 20: An example implementation of a proportional-integral CDR [21].

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 35

 10 10
0 ns 0 ns
10 ns 10 ns
0 20 ns 0 20 ns d

30 ns 30 ns

–10 –10

Dp DI
–20 –20

–30 –30
105 106 107 108 109 105 106 107 108 109
Frequency Frequency
(a) (b)

FIGURE 21: The proportional-integral CDR’s sensitivity to loop latency. (a) The effect of delay in the proportional path and (b) the effect of
delay in the integral path on the CDR’s JTRAN function.

Digital CDR
DCO A proportional-integral CDR architec-
ture lends itself very well to a digi-
KP PDAC tal implementation, the concept of
D
CLK
PD which is shown in Figure  22. Here,
the integrator is replaced by an accu-
KI + IDAC
mulator, thus eliminating the need
Z –1 for a large capacitor, and the integral
and proportional paths are merged
with a digitally controlled oscilla-
tor (DCO). Because the integral path
FIGURE 22: A digital (hybrid) DCO-based CDR. PDAC: proportional path DAC. is less sensitive to delay, it is often
implemented in the RTL.
Although this architecture does
DCO not require a charge pump, it does
require a high-resolution DAC in the
KP PDAC
D CLK integral path, which can have chal-
PD lenging specs. To better understand
∆Σ the requirements on the integral-path
KI + IDAC
Modulator DAC (IDAC), let us perform some calcu-
Z –1 lations using the CDR parameters we
have been using all along. In the digi-
tal CDR, each phase-detector update
Signed Unsigned Signed
Saturate would change the oscillator’s control
M+D D D+1 Carry M+1
+ + + voltage (i.e., current) by K I # LSB IDAC .
D Therefore, to match the analog CDR
Z –1 M Z –1 M
example with I CP  = 12 µA, C = 400 pF,
IDAC_in
∆Σ_State and UI  = 100 ps, LSB IDAC  1 12 µA #
Integ_out
100 ps/400 pA  = 3 µV. This means
that the digital CDR requires a 3-µV,
FIGURE 23: Enhancing resolution with a TR modulator. 10-GS/s DAC, instead of the 12-µA,
10-GS/s charge pump required by the
(e.g. sinusoidal jitter) with zero K I . paths on the CDR’s JTRAN for the same analog CDR. Fortunately, we can use
As a result, there is a limit to how CDR parameters, as depicted in Fig- TR techniques to achieve the desired
small K I can be, a value that is set ure 13. The plots demonstrate that this resolution without much complex-
primarily by the JTOL spec. type of CDR can tolerate significant ity overhead.
Figure 21 shows the impact of delay latency in the integral path without Figure  23 shows a model of the
in the CDR’s proportional and integral much impact on the CDR’s stability. digital CDR with TR modulator in the

36 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

integral path [1]. The TR modula-
tor toggles the LSB at the DAC input
with the proper duty cycle to create
a high-resolution DAC output. Borrow-
ing an example from [1] with a minor
modification, let us assume that the
accumulator is 7’b00011_00 (M  = 5
and D  = 2) and the phase detector
generates a series of “1” outputs. The
accumulator, TR state (initial condi-
tion 3’b0_00), and DCO input would
change as follows over multiple phase
detector updates:
■■ TR _state = 3’b0_01, IDAC_in =
3 + 0 = 3
■■ TR _state = 3’b0_10, IDAC_in =
3 + 0 = 3
■ ■ TR _state = 3’b0_11, IDAC_in =
3 + 0 = 3
■■ TR _state = 3’b1_00, IDAC_in =
3 + 1 = 4
■■ TR _state = 3’b0_01, IDAC_in =
3 + 0 = 3
■■ f.
The pattern repeats, with a “1” generated
every fourth cycle. The gain of the inte-
gral path in this architecture is K I /2 D.
Although TR helps with the DAC
resolution problem, the integral path,
including the accumulator and DAC,
still operates at one sample per phase-
detector update. This could lead to high
complexity and power consumption. In
many implementations, the output of
the phase detector is decimated before
it is passed to the integral path. Deci-
mation by N reduces the integral gain
of the CDR by a factor of N. An example
implementation of such a CDR can be
found in [20].
Np
D
PD
NI
FIGURE 24: A fully digital PI-based CDR.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 37
In many implementations, the output of
the phase detector is decimated before it is
passed to the integral path.
In cases where a local precision oscil-
lator is available at the Rx, it is possible
to remove the oscillator from the CDR
loop and instead use a phase interpola-
tor (PI), as depicted in Figure 24. In this
architecture, the phase-accumulation
logic together with the PI effectively
form a DCO. In such architectures,
the phase-interpolator’s integral non-
linearity and differential nonlinearity
are important for CDR performance. A
detailed analysis of such architectures
is provided in [1], and a design example
can be found in [23].
Summary and Conclusions
This article covered various aspects of
CDR design through the use of exam-
ples. This concluding section reviews
the CDR design flow and provides
brief references to a few topics not
previously covered.
CDR design typically begins by
defining the JTOL spec for the sys-
tem. If the design has to comply with
a standard, the JTOL spec is often
already specified.
JTOL is essentially a means by which
to negotiate the jitter spec between
the Tx and Rx and between the data
recovery and clock recovery circuits
at the Rx. JTOL specifies how much jit-
ter the Tx is allowed to generate and
External Clock Source
PI Phase Select
KP
+ +
∆Σ
NI + Z –1
Modulator
Z –1 PI
at what frequencies. It also specifies
how much of the budget can be taken
by equalization and how much by
clock recovery.
The next phase in the design is to
create a JTRAN spec for the CDR using
the JTOL spec to guide the transistor-
level design.
A high-level model of the CDR is often
the best way to iterate through architec-
ture choices and derive the block-level
specs. The CDR model should include
everything that impacts the CDR BW
and dynamics. In particular, all poles,
zeroes, and latencies in the loop must
be properly modeled.
An analog bang–bang CDR may be
adequate if a large loop capacitor and
two-times oversampled front ends
(slicers and clocks) are acceptable.
A proportional-integral architec-
ture may provide more flexibility if a
VCO with two frequency adjustment
knobs can be designed.
A baud-rate CDR may reduce the
number of required clock phases,
but it is more sensitive to channel
response. There is also more interac-
tion between the CDR and equaliza-
tion circuits in a baud-rate CDR.
Hybrid architectures may lead to
more optimized designs, but it is impor-
tant to watch for latencies. Often it is a
PI Clock Source
CLK
PI
good idea to include a fast proportional
path (i.e., small delay, no decimation).
When optimizing the CDR archi-
tecture, it is important to budget
for CDR’s self-generated jitter. The
budget can determine the choice
between LC versus ring VCO, and cur-
rent mode logic versus CMOS clock
distribution, or may force a dedi-
cated regulated supply for the clock
path. Power-supply-induced jitter may
sometimes be a large portion of the
self-generated jitter.
CDRs have limited locking range,
and, although gear-shifting the CDR
settings during initialization can
increase the range, it is often not
enough. Therefore, when architecting
the CDR, it is important early on to
determine the initial frequency-acqui-
sition method (Note that frequency
acquisition was not covered in this
article.) Many systems allocate an ini-
tialization state, during which a clock
signal is sent over the data line by the
Tx and can be used by the Rx for the ini-
tial frequency acquisition. Other stan-
dards require the Rx to acquire a lock
without any special training sequence.
Examples of some CDRs with broad
capture range techniques can be found
in [24]–[26].
Clock recovery circuits often inter-
act with the equalization circuits, as
the choice of sampling phase deter-
mines the sampled channel response
of the system. Therefore, it is impor-
tant to simulate clock recovery with
data recovery.
Many of today’s systems require
fast transitions between the power-
down state and the active state. In
such cases, fast wake-up CDR archi-
tectures are required. In digital CDR
architectures, frequency information
may be stored and recovered between
states; however, phase information
must still be acquired after every
state transition. Some examples of
fast wake up CDR architectures can be
found in [2].
Acknowledgments
I thank Dr. Valentin Abramzon, Dr.
Anup Jose, Prof. Sam Palermo, and
Prof. Ali Sheikholeslami for their
38 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
valuable feedback and help with pre- [19] T. Shibasaki et al., “A 56 Gb/s NRZ-electri-
cal 247mW/lane serial-link transceiver
paring this article. in 28 nm CMOS,” in Proc. IEEE Int. Solid-
State Circuits Conf. (ISSCC), 2016, pp.
64–65.
References [20] D. Oh, D. Kim, S. Kim, D. Jeong, and W.
[1] J. Stonick, “DPLL-based clock and data re-
covery,” ISSCC Tuts., Feb. 2010.
Kim, “A 2.8 Gb/s all-digital CDR with a 10
b monotonic DCO,” in Proc. IEEE Int. Solid-
[2] P. Hanumolu, “Clock and data recovery ar- State Circuits Conf. (ISSCC) Dig. Tech.
chitectures and circuits,” ISSCC Tuts., Feb.
2015.
Papers, 2007, pp. 222–598.
[21] J. Kim, J. Kim, G. Kim, and D. Jeong, “A ful-
[3] N. Da Dalt and A. Sheikholeslami, “Under- ly integrated 0.13-um CMOS 40-Gb/s Serial
standing Jitter and Phase Noise: A Circuits
and Systems Perspective,” Cambridge,
Link Transceiver,” IEEE J. Solid-State Cir-
cuits, vol. 44, no. 5, pp. 1510–1521, 2009.
U.K.: Cambridge Univ. Press. [22] J. L. Sonntag and J. Stonick, “A digital
[4] B. Casper and F. O’Mahony, “Clocking anal-
ysis, implementation and measurement
clock and data recovery architecture for
multi-gigabit/s binary links,” IEEE J. Sol-
techniques for high-speed data links—A id-State Circuits, vol. 41, no. 8, pp. 1867–
tutorial,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 56, no. 1, pp. 17–39, 2009.
1875, 2006.
[23] J. Liang, A. Sheikholeslami, H. Tamura, Y.
[5] M. Perrott, 6.976 High Speed Communica- Ogata, and H. Yamaguchi, “6.7 A 28 Gb/s
tion Circuits and Systems (lecture 21). Spring
2003. Massachusetts Institute of Technol-
digital CDR with adaptive loop gain for
optimum jitter tolerance,” in Proc. IEEE
ogy: MIT OpenCourseWare. [Online]. Avail- Int. Solid-State Circuits Conf. (ISSCC), 2017,
able: https://ocw.mit.edu
[6] Agilent Technologies, “Jitter Fundamen-
pp. 122–123.
[24] A. Pottbacker, U. Langmann, and H. Sch-
tals: Jitter Tolerance Testing With Agilent reiber, “A Si bipolar phase and frequency
82250 ParBERT,” Santa Clara, CA, 2003.
[Online]. Available: http://literature.cdn
detector IC for clock extraction up to
8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27,
.keysight.com/litweb/pdf/5989-0223en no. 12, pp. 1747–1751, 1992.
.pdf
[7] H. Zhang, B. Jiao, Y. Liao, and G. Zhang, “A
[25] R. Inti, W. Yin, A. Elshazly, N. Sasidhar,
and P. K. Hanumolu, “A 0.5-to-2.5Gb/s
tutorial on PAM4 signaling for 56 G serial reference-less half-rate digital CDR with
link,” DesignCon, 2016.
[8] R. C. Walker, “Designing bang–bang PLLs
unlimited frequency acquisition range
and improved input duty-cycle error tol-
for clock and data recovery in serial data erance,” in Proc IEEE Int. Solid-State Cir-
transmission systems,” in Phase-Locking
in High-Performance Systems, B. Razavi,
cuits Conf. (ISSCC), 2011, pp. 438–450.
[26] S. B. Anand and B. Razavi, “A 2.75 Gb/s
Ed. Piscataway, NJ: IEEE Press, 2003, CMOS clock recovery circuit with broad
pp. 34–45.
[9] J. Lee, K. S. Kundert, and B. Razavi, “Analysis
capture range,” in Proc IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers,
and modeling of bang–bang clock and data 2001, pp. 214–215.
recovery circuits,” IEEE J. Solid-State Circuits,
vol. 39, no. 9, pp. 1571–1580, 2004.
[27] A. Amirkhany, “Basics of clock and data re-
covery circuits,” presented at the Int. Solid-
[10] M. Verbeke, P. Rombouts, A. Vyncke, and State Circuits Conference (ISSCC), San Fran-
G. Torfs, “Influence of jitter on limit cy-
cles in bang–bang clock and data recov-
cisco, CA, Feb. 17–21, 2019.
ery circuits,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 62, no. 6, pp. 1463–1471,
2015.
About the Author
[11] C. Hogge, “A self correcting clock recov- Amir A m i rk h a ny (a.amirkhany@
ery circuit,” J. Lightw. Technol., vol. 3, no.
6, pp. 1312–1314, 1985.
samsung.com) received his B.S. degree
[12] J. D. H. Alexander, “Clock recovery from from Sharif University of Technology,
random binary signals,” Electron. Lett.,
vol. 11, no. 22, pp. 541–542, 1975.
Tehran, Iran, his M.S. degree from the
[13] M. Verbeke, P. Rombouts, X. Yin, and G. University of California, Los Angeles,
Torfs, “Inverse Alexander phase detector,”
Electron. Lett., vol. 52, no. 23, pp. 1908–
and his Ph.D. degree from Stanford
1910, 2016. University, California, all in electrical
[14] K. Mueller and M. Muller, “Timing recov-
ery in digital synchronous data receiv-
engineering. He is a senior director
ers,” IEEE Trans. Commun., vol. 24, no. 5, of engineering at Samsung Electron-
pp. 516–531, 1976.
[15] V. Balan et al., “A 4.8–6.4-Gb/s serial link
ics, in charge of the development of
for backplane applications using decision future generations of high-speed inter-
feedback equalization,” IEEE J. Solid-State
Circuits, vol. 40, no. 9, pp. 1957–1967,
faces for Samsung displays. Prior to
2005. Samsung, he was a design manager at
[16] F. Spagna et al., “A 78 mW 11.8 Gb/s se-
rial link transceiver with adaptive RX
Ramus Inc., where he led the devel-
equalization and baud-rate CDR in 32 nm opment of proprietary high-speed
CMOS,” in Proc. IEEE Int. Solid-State Cir-
cuits Conf. (ISSCC), 2010, pp. 366–367.
memory interfaces. He won the best
[17] R. Dokania et al., “10.5 A 5.9pJ/b 10Gb/s student paper award at the 2008 IEEE
serial link with unequalized MM-CDR in
14nm tri-gate CMOS,” in Proc. IEEE Int.
Global Communications Conference,
Solid-State Circuits Conf. (ISSCC) Dig. Tech. has authored or coauthored over 25
Papers, 2015, pp. 1–3.
[18] P. Upadhyaya et al., “A fully adaptive 19-
IEEE conference and journal papers,
to-56 Gb/s PAM-4 wireline transceiver and has more than 40 issued U.S. pat-
with a configurable ADC in 16 nm FinFET,”
in Proc. IEEE Int. Solid-State Circuits Conf.
ents. He is a Senior Member of the IEEE.
(ISSCC), 2018, pp. 108–110. 
Stephan Weber and Cândido Duarte

A
high production yield,
Y = 1 - p fail, and thus
a low failure rate, p fail,
is a key requirement for
successful chip design
and the design of many other technical
products and systems. We focus on
IC design in the analog and mixed-
signal domains, where Monte Carlo
(MC) techniques have been a stan-
dard method for many years (see
“Important Monte Carlo Rules
Engineers Should Know”). Cir-
cuits have to be reliable under
certain ranges of environmental
parameters, such as supply volt-
age (V) and temperature (T ) .
Furthermore, the set of semicon-
ductor technology parameters
(P) varies significantly, from die
to die (global variations) to device
to device (local variations, called
mismatch). Many circuit tricks are
mismatch
known to minimize all of these influ-
ences (for example, using cascodes for
a high power-supply rejection, differen-
tial pairs to cancel out threshold voltages,
special layout techniques, and so on), but at
some point problems become hard to antici-
pate, and further improvements are difficult to
achieve. We must accept such variations and need
to analyze their impact on production yield, which is a

Yield Analysis for

Electrical Circuit Designs
Many problems and some recent developments
in electronic engineering

Digital Object Identifier 10.1109/MSSC.2019.2939341

Date of current version: 23 January 2020

1943-0582/20©2020IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2020 39

 about which problems are simple and
We focus on IC design in the analog and mixed-
which are not. The classical shortcut
signal domains, where Monte Carlo techniques to verify 6v or 1 part per billion loss
have been a standard method for many years. is to run an MC analysis, calculate n
and v from the simulated data point
set X (for this, we may need only a few
function of these parameters and the specification limit x spec is 6v beyond hundred MC points), and check the
specifications (such as design topology the mean n , then the yield becomes specification distance: Is it $ 6v or
and component sizes, among others). approximately 99.9999999%, or sim- not (with some safety margin)? How-
Dealing with many variables can ply 6v. In this way, we use sigma as ever, using such a simple approach of
be difficult, and mathematically the distance to specification, or speci- just inspecting the normalized speci-
there is a general troublemaker: the fication margin, but also indirectly as fication distance (x - n) /v is risky,
curse of dimensionality. We discuss the yield measure. In principle, we and it will become very inaccurate for
which aspects are causing the most could use other distance measures, nonnormal distributions [3], [4].
headaches and which topics will mat- but for the normal distribution, the The alternative brute-force method
ter more and more when applying standard deviation v gives the most is still possible in any situation: cal-
advanced technologies (such as fin stable fit, so specification distance or culate the sample yield, Y, and p fail
field-effect transistors and others). distance method are simply more gen- directly from the number of pass
eral names for this sigma method. and fail samples. Unfortunately, for
Design Complexity This is similar to decibels in using good high-yield designs, a too-short
A general trend in design is com- not the logarithmic function but MC run (for example, using “only”
plexity. A state-of-the-art device, such another—indeed, not that exotic— 10,000 points) would usually still give
as a system on chip built from hun- compressing function. Instead of using no fail sample with an output value
dreds (or even millions) of blocks, the effective sigma, it is also popular X beyond specification x spec; thus,
can have a high yield, Y = (number of to use a process capability index, such Y = 100%, and in terms of sigma this
good or conforming devices)/(total as the well-known C pk [1], [2], which, would be infinite. This is obviously
number of devices) = 1 - p fail, beyond for an upper specification limit, is sim- incorrect, because all real designs
90% only if all blocks (which tend to ply v/3. This gives even more simple will start to fail at some point in the
become more complex as well) have numbers, because C pk $ 1.0 is a typi- statistical variable space. The count-
a very high individual yield, such as cal minimum design requirement. For ing-fails method is usually already
greater than 99.8% or even far beyond simpler blocks, this target is usually very inefficient (see Table 1) and time
99.99%. Engineers want simple num- achievable with moderate effort, but consuming for verifications beyond
bers, so, in quality engineering, it is 4.5v (or C pk = 1.5) is often a challenge 4v ^C pk = 1.333h because then such
very common to express the yield for critical blocks. fail events are very rare and will not
simply in terms of sigma, according produce a very stable statistic! If we
to an equivalent normal Gaussian Yield Verification With MC use fewer than N = 1/p fail points,
distribution (Table 1). If we have a Many experienced designers of tech- we would typically see one fail, but
Gaussian distribution and the (upper) nical systems have good intuition even observing a fail sample (often
in hundreds of hours) does not auto-
matically give a good statistic. The
N min reported in Table 1 is derived
Important Monte Carlo Rules Engineers Should Know
•• Always inspect your data visually.
•• In case of problems, follow common sense, and do not overinterpret your MC results, TABLE 1. LOSS VERSUS SIGMA AND
CPK (SINGLE-SIDED), INCLUDING
such as using C pk, if data do not look like a Gaussian bell curve.
MINIMUM REQUIRED MC COUNT IF
•• Counting fails and using p fail = fail/N makes no assumptions on the distribution shape, USING THE COUNTING METHOD.
but the sigma or C pk method works correctly only for purely normal distributions.
MINIMUM
•• Use approximations based on assuming normal data only if you have good arguments for
LOSS SIGMA CPK COUNT
doing so—for example, because the statistical variables themselves are normal and the
circuit behaviour is almost linear. 50% 0.0 0.0 e.g., 50
•• A 2× reduction of the random standard variation from one Monte Carlo run to another 0.135% 3.0 1.0 ≈2,000
Monte Carlo run requires four times more points. 0.016% 3.6 1.2 ≈19 × 103
•• If no fails can be observed, the lower confidence interval limit is approximately 3/N. 0.00034% 4.5 1.5 ≈900 × 103
Guaranteeing a loss lower than 0.1% requires 3,000 points.
0.99 ppb 6.0 2.0 ≈3 × 109
•• Getting reasonably stable estimates for µ and v requires approximately 50 to 200 points.
ppb: parts per billion.

40 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

from the 90% confidence interval (CI)
and for observing no fail. On the one
hand, the CI gives us some safety mar-
gin, but, if the design is close to the
yield target, we may need many more
MC points. The counting method is
mainly good for proving that a design
still needs improvement, so it is very
useful in the initial design phases,
usually in parallel with the faster spec-
ification-margin (sigma) method.
Both methods are standard MC tech-
niques, so why is the n-and-v method
so efficient and the counting method
very inefficient for high yields? The
good news is that, in both methods,
the complexity of the design on which
we run MC does not matter at all. When
looking at histograms by using the
mean and sigma or counting fails and
so on, it does not matter if your sys-
tem consists of a few transistors or bil-
lions; only the histogram and output
samples themselves matter. In both
cases, we will typically observe that
the MC accuracy (for example, in terms
of standard deviations or CI width),
roughly improves by 10 times if we use
100 times more points. This makes MC,
compared to other numerical methods,
such as Simpson’s rule for integra-
tion or the Newton-Raphson method
for solving nonlinear equations, very
slowly converging.
However, as MC works even in the
most complex situations, it will remain
extremely useful. MC works even if the
number of variables itself is a random
number, and any statistical distribu-
tion is possible, even those that have
no mean value at all (such as the Cau-
chy distribution).
The general wide applicability of
the counting method to both normal
and nonnormal data usually does not
matter so much because most techni-
cal designs are quite well behaving;
that is, they are not too nonlinear.
Methods exploiting smoothness or
linearity can easily outperform the
counting method. For small blocks
and moderate yield levels (such as 3v
or C pk = 1.0; that is, p fail . 0.2%), the
runtimes with the counting method
are usually still no issue, but, for
more difficult verifications, it makes
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 41
Dealing with many variables can be difficult,
and mathematically there is a general
troublemaker: the curse of dimensionality.
sense to inspect other methods, and
there are many of them.
MC in Math
So far, we have given no clear definition
of what MC actually is. Engineers would
say, “We run simulations in a computer,
with values of variables coming from
random-number generators, which fol-
low statistical models created by clever
people. We just inspect how the circuit
would behave in production, looking
at specification margins, histograms,
correlations, yield, and so on.” MC is a
kind of time machine, because nothing
else puts the design into a scenario as
close to reality as possible. One hun-
dred nominal or corner simulations are
only a type of proof of concept, but a
single MC simulation point can tell if
a new design has a chance to work in
real hardware.
However, mathematically, MC is
nothing more then a (simple) numeri-
cal integration method in which we
approximate an integral (for example,
defining the expected value, E, of a
certain statistic or the volume of a geo-
metric shape) by a sum (1). MC does
nothing very clever; the samples X i
are created randomly, not at all well
distributed along the variable ranges
(which would be the case if using Rie-
mann’s sums); also, no weights are
used (as in Simpson’s rule or Gauss-
ian integration):
# f (X) dX . 1/N $ / f^X i h for i = 1 to N. worse. The advantage of roughly
(1)
We use an uppercase X to indicate
that MC can also be used for multi-
variate functions.
Purely random MC is the only method
in which we magically do not really face
the problem that complex designs lead
to a much more difficult yield analysis.
The pure count of variables per sample
(the dimension d) does not matter. One
price to pay is a slow convergence.
Obviously, a big improvement
can be expected if we place the MC
samples for our statistical variables
not randomly, but “dedicatedly.” For
example, in the special case of a single
variable with uniform distribution, a
set of equally spaced points would fit
much better. We would get rid of ran-
domness in the results, and we would
get roughly 1/N convergence speed;
we could use fewer points for the
same accuracy.
Several improvements are pos-
sible, and, by common sense, almost
anything dedicatedly designed should
be better than a random process. How-
ever, usually these ideas for improve-
ments tend to fail as more variables
are present. Many problems become
exponentially more difficult with the
number of dimensions, which is called
the curse of dimensionality. Numeri-
cal integration is just one important
example. Hard to believe? No—already
for two dimensions we can see the
onset of this curse, when using Rie-
mann’s sum (or Simpson’s rule, or
any other) for integration. If we have
one variable and a range from 0 to 1
and we want to use N = 100 samples,
then the optimum 1D spacing 3 X
would be approximately 1/N = 0.01.
However, to cover the 2D unit square,
we would need a 10-by-10 grid; thus,
within each dimension we can only
achieve a sample spacing of rough­
­ly 1/:100 = 0.1, which is 10 times
1/N versus 1/√N speed in MC would
almost disappear!
A second aspect is also interest-
ing: with dedicated spacings, we can
derive hard error bounds related to
function properties, such as their
derivatives f ’ or f ” or the functional
variation, but random MC provides
only statistical error limits, such as
CIs. In an MC analysis for real tech-
nical systems, we usually must deal
with dozens or hundreds (sometimes

Many problems become exponentially more
difficult with the number of dimensions, which
is called the curse of dimensionality.
millions) of statistical variables, and
this makes most non-MC techniques
surprisingly inefficient. In fact, this
aspect becomes more and more impor-
tant in modern designs. Electronic
engineering and electronic design
automation (EDA) tools are increas-
ingly cursed.
An interesting math aspect of
dimensionality is that things are often
easy to prove for an arbitrary sample
point count N (for example, by induc-
tion) but not for an arbitrary dimen-
sion d. For instance, dense packing of
spheres or balls [5] in a box is easy in
d = 1 or 2 but quite hard for d = 3, and
there are special dimensions (such as
eight and 24) in which exact solutions
have been found and proven but not
many others. Quite often, experiences
from lower dimensions are not so
easy to transfer to high-dimensional
problems. For instance, systematic
ball packing should lead to a higher
density than random packing, but,
at higher dimensions, the poten-
tial advantage becomes smaller and
smaller, and we simply do not know
what the densest packing looks like
in, for example, d = 100.
Comparing Two Key Techniques
Let us come back to our two native
random MC techniques: counting fails
and getting Y directly versus calculat-
ing n and v and applying a Gaussian
fit. Equation 2 connects the sample
yield Y to the sigma method via the
cumulated distribution function (CDF)
of the normal distribution:
Y = p ^X < x h = CDFnorm (x, n, v) . (2)
CDF(x) is, in general, the integral
(from –∞ to x) of the probability den-
sity function (PDF). For the normal
Gaussian distribution, the PDF is
the well-known bell curve accord-
ing the exp (- x 2) law, whereas the
CDF is related to the so-called error
42 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
function. Both the PDF and CDF of a
normal distribution are available in
advanced pocket calculators or in
most math libraries.
Using both methods (pass–fail and
sigma), we can double-check our re­­
sults, but why is the sample-yield-
counting method so inefficient? It is
because it exploits only the informa-
tion of whether a sample point mea-
surement result X is above or below
the specification limit x spec (not how
much above or below)! This method
is clearly wasting information. On the
other hand, using the sigma method is
almost the best possible method for
normal Gaussian data. A consequence
is that using further tricks will not
help much: calculating the average n
and the standard variation v is almost
the best you can do; indeed, this sim-
ple method exploits all information in
the data (in a Gaussian case).
In the sigma method, we take the
(hopefully correct or best-suited) model
and apply a fit according to our cur-
rent MC results (sample data); using
the CDF, we can calculate a yield
value from the fit. This fitting method
is not easy to improve because quite
often the data are almost Gaussian,
and one can hardly use a better fitting
model than the true data-generating
model. Here, the intuition of most
people is correct.
The remaining uncertainty is that
we do not know the true mean and
true sigma values; we only estimate
them by using the MC sample val-
ues, based on a finite point count
N. There is one little trick to men-
tion: use “' ^N - 1h” to calculate your
sigma estimate, not “ ' N. ” Without
Bessel’s correction, we introduce a
small systematic error, especially if N
is not large. Luckily, this finite-sample
bias error is small and proportional
to 1/N, so it quickly becomes much
smaller than the statistical variations
(decreasing with 1/√N). Using “' N ”
would make the v too small; thus,
the normalized specification distance
and C pk would become too large, as
would the yield. Too-optimistic yield
estimates bring the designer to an
unsafe situation, and there can be sev-
eral other reasons for such estimates.
Nonnormal Data
Checking for sample yield and deter-
mining specification distance are core
techniques, and most designers already
use them, but how, for example, can we
treat nonnormal data or speed up MC
further, at least moderately?
A native attempt to model nonnor-
mal data would be to try another fit.
In many electrical problems, a lognor-
mal model could be a basis, having at
least some deeper physical justifica-
tion. Often, we know that all data sam-
ples are positive, and we know that
exponential functions are involved in
our design (which is often the case for
leakage currents or bipolar devices). A
lognormal model is suited for asym-
metric data; if we have both positive
and negative samples, then a native
extension would be an extended log-
normal distribution model, which
also includes a shift and, if needed,
(scaled) mirroring. This model would
further include the usual lognormal
distribution and pure normal distribu-
tion, and it requires three parameters
to fit, not just n and v. Such a com-
plex three-parameter model would
lower the systematic errors arising
from a simple normal fit to asym-
metric data. Unfortunately, this more
complex fit will often be statistically
less stable, so it might be not easy to
decide for one of the models if the
data asymmetry is quite small. More-
over, the extended three-parameter
lognormal model would still not fit
well to uniform data or to data having
multiple modes (such as a mix of two
normal distributions shifted against
each other). This means that sev-
eral further extensions are required
to model difficult types of data. In a
normal distribution of samples, x can
range from –∞ to +∞, but the standard
deviation sigma is still finite, because
the PDF values lower very quickly for
large values of x. However, this is not
the case for many other technically
important distributions; for some, the
standard deviation might not exist, so
we need to use other scale measures
and, for example, measures for asym-
metry, tail shape, and so on.
Mathematically, this is possible in sev-
eral ways. One recent solution attempt
called generalized C pk can be found in
[4], or, alternatively, one could simply
try out many distribution models and
take the best-fitting one.
How to Be on the Safe Side?
“All models are wrong” is a common
saying. When multiple models are
used, two further problems will pop
up. First, our extended lognormal
model will almost surely better fit a
normal Gaussian data sample than
the Gaussian model itself. However,
the more complex model will be less
stable, which means that our yield
estimate will be less stable against
random variations. Model selection
is not a simple thing, and a second
problem is that quite often the data,
just by chance, might indicate a too-
high yield. Figure 1 reflects this situ-
ation: we applied the three-parameter
fit many times to Gaussian MC data
with N = 512 but with different seed
values. The median value is very close
to the true value, but, of course, there
will be some variation, which exhib-
its a long tail on the right (high-yield)
side. If we aim for the best fit purely
in terms of probability, we may often
get, surprisingly, yield estimations
that are far too optimistic. We would
also get yield estimates that are too
pessimistic, but, here, strong outliers
are less likely; that is, there is a kind
Quite often, experiences from lower
dimensions are not so easy to transfer
to high-dimensional problems.
infinity, we can make the error as
small as we want. However, for finite
N, even with averaging across infinite
MC runs, there would be the already
mentioned finite sample bias. One
can show, if we create our estimates
by maximizing the probability to get
the given data, that such estimates
would only be asymptotically maxi-
mally efficient and unbiased. Mean
and standard deviation are such max-
imum likelihood estimates (MLEs) for
a normal distribution and, thus, are
usually preferable over other estima-
tors for the model parameters (such
as median or location of maximum
density for parameter n ).
Luckily, the MLE finite sample bias
is usually of order 1/N, so it decreases
much faster than the random varia-
tions. However, this bias is only one fac-
tor leading to overoptimism, and it is
not as easy to correct as for the normal
case. This problem becomes quickly
critical as you fit more parameters.
Too Pessimistic Median Too Optimistic Far Too Optimistic
Cpk Histogram
1.1
1
0.9
0.8
0.7
0.6
(y)
From a designer’s perspective a
somewhat conservative yield estimate
is desirable. C pk is not conservative
and is often highly optimistic on
lognormal data; for example, with
a test case having a true yield of 3v
and data with skew of one (giving an
asymmetry as in Figure 1), we get a
+50% sigma error if using the normal
Gaussian C pk . For 6v verification,
even very mild deviations from nor-
mality can have a significant impact.
Many methods for model selection
have been developed since the 1970s,
and model averaging is possible too,
allowing a smooth transition from
a simple model to a more complex
model. (Even more than two models
can be used.) Using such model-infer-
ence techniques, we treat each model
not as something that is hopefully
correct but for being able to make
reliable predictions. These are pos-
sible, even if the used models are not
100% correct. The random sampling

of asymmetry. 0.5
Only if we run a very long “golden”
0.4
MC analysis will the problem of asym-
metry and yield optimism disappear 0.3
(slowly). Such highly asymmetric dis- 0.2
tributions and CIs are very typical for 0.1
good-fitting but too complex models.
0
Random MC itself, as an integration 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5
method, has no systematic errors, Cpk
and this is also true for our extended
lognormal fit. However, discussing FIGURE 1: The distribution and CI (yellow bars) of the estimated effective C pk based on an
errors is a bit tricky. For N going to extended lognormal fit. N = 512, and true yield is 4v.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 43

error can be often quantified, but the
quantification of systematic errors is
somewhat more difficult.
Conservative Yield Estimation
Techniques for conservative yield
estimation have been well known for
some time. For instance, [6] describes
that using the normal model fit (used
in the sigma method and C pk ) does
not lead to conservative estimations,
even if the underlying data are gener-
ated from an ideal Gaussian random-
number generator. Luckily, this effect
is important only if your sample point
count is simply too small, but, if more
complex models are used (such as the
shifted lognormal model or the gener-
alized C pk ), the minimum point count
will increase significantly. Figure 1
has been created from an extended
three-parameter lognormal fit, but,
at 4v, the histogram of the classical
Gaussian two-parameter C pk would
also look as nonnormal as Figure 1
if we used only 30 points. The gen-
eralized version, C gpk, would require
approximately 2,000 points in this
situation, but it would work with
very low bias even for difficult data
(such as data that are neither normal
nor lognormal).
In [6], different methods are des­­
cribed for modifying the yield esti-
mation for normal data to achieve
an acceptable level of conservativity
without being overly pessimistic. Of
course, by avoiding too optimistic esti-
mates, we introduce some yield pessi-
mism in general. In the ideal case, we
can achieve almost symmetric distri-
butions for the effective C pk, leading to
CIs that are much easier to handle and
nearly symmetric. Being too optimistic
would be approximately as likely as
being too pessimistic.
One approach to achieve this is
use of so-called bootstrap techniques.
Normally, behind each MC result there
is a (quite long) circuit simulation.
Bootstrap executes a kind of fake MC
analysis without running new circuit
simulations. Imagine we run 100 MC
points and get a vector for number of
bit errors as the result. The mean bit
error rate would depend slightly on
Comments on Artwork Regarding the Curse of Dimensionality
A multidimensional standard normal distribution looks like a ball whose density fades out slowly
from the center to the outer space. This means that outer samples are rare; this is already true in
1D but even more so in many dimensions. One similar effect occurs when looking at a sphere
inside a cube.
Unit Cube Versus Touching Sphere
We inspect a unit cube, so its edge length is 1.0 unit on dimension d. The sphere has fixed radius
r = 0.5 to just touch the cube planes. Obviously, the volume of the cube is larger than that of the
sphere, but it is interesting to inspect what the additional volume looks like and how the volume
ratio behaves versus d.
2D (d = 2)
The “cube” in 2D has four edges, and the distance from the center to an edge point is
0.5 # :2 = 0.707 according to Pythagoras. At the cube edges, the cube reaches points more
away, by 0.27 or 0.5 # ^:2 # 1h, than the sphere (Figure S1).
3D (d = 3)
The center-to-edge distance is now 0.5 # :3 = 0.866 according to Pythagoras. The extension
beyond the circle is increased to 0.366. This means the extension no longer looks like a slightly
distorted triangular but is somewhat spikier if we plot a kind of 2D projection of this 3D arrangement.
In addition, we would, of course, have eight such extensions, each spanning not 90° but
only 45° (because these extensions do not overlap). Such 2D visualization has similar distortions
as you would find on a world map, but it helps provide an understanding for higher dimensions.
The calculation for one edge is shown in Figure S2, and the full picture of the 3D case pro-
jected to 2D is shown in Figure S3.
0.366
0.27
0.5
0.707
FIGURE S1: A unit cube and unit sphere FIGURE S2: The calculation for one edge
in 2D. in 2D.
chance; to estimate the variance, we bootstrap MC run would be almost the
could do this MC analysis 50 times, same as for the original bit-error-rate
which would be, unfortunately, very MC run. Most people would probably
time consuming. However, alterna- not recognize the switch at all, and the
tively, we can apply a trick: we run “new” results would still look almost
MC only once, then use an integer random. For instance, over a long
random-number generator to pick an period, we can assume that each num-
existing sample by its MC index. If we ber appears roughly with the same
do this, for example, again 100 times, probability, and this would still be the
we might get a few values twice, and case for the new bootstrap results.
some original values would be miss- With such techniques, we can also
ing; but many statistics (such as mean get CIs for statistical estimates, even
value and standard deviation) of that for nonnormal data. For instance, by

44 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

 true yield of 5.3v and your MC result
has, for example, CI = 64.8; 5.8@, then
n-Dimensional you should run more MC points if you
n-Dimensional Ball Within
Unit Cube of the Cube want to verify 5v (for a given confi-
Volume 1 (Radius 1/2)
dence level, such as 90%). An MC run
with the same point count, on a simi-
2n “Spikes”
lar design but now with a true yield of
of Length
n1/2/2 ≈ ∞ 5.8v, shows a typical result, such as
CI = (5.3, 6.5) . This means that, with
the same point count, we would have
FIGURE S4: The cube and sphere in
already verified 5.3v. The larger the
higher dimensions.
design margin, the easier the verifica-
tion, but, of course, much overdesign
is sometimes not possible because it
FIGURE S3: The 3D case projected to 2D.
would come with other problems (such
as increased chip area, more heat dis-
If we created a similar picture but, for example, sipation, and so on).
in 3D style from the 4D scenario, then the blue
spikes would be not only around the circle but dis- Improving Space Filling
tributed across the full sphere surface. The spike Up to now, we have discussed random
length in the 4D case is 0.5 # :4 = 1, and sampling, but isn’t there something
the extension beyond the circle is further in- beyond random or grid sampling?
creased to 0.5. Yes, there is, and it is called low-dis-
At d = 5, the spike length is larger than 1.0 crepancy sampling (LDS).
and so goes beyond the cube planes, which is FIGURE S5: The E8 lattice plotted as a An older better-than-random
strange. In general, we get the image shown 3D projection. method is so-called Latin hypercube
in Figure S4. sampling (LHS) (see “Comments on
The unit ball volume tends to zero, and almost all volume is moving into the spikes. This means Artwork Regarding the Curse of
that the normal distribution loses its center tendency; in high dimensions, even the center would Dimensionality”). However, LHS fills
be sparsely sampled. the space well only for each variable
The general equation for the spiky extension is l = 0.5 # d - 0.5, as mentioned. For d = 4, it X j but not, for example, for multivari-
already becomes 0.5, that is, as long as the radius of the sphere, and it will increase without limit for high- able terms, such as X j + X k - 2X i . A
dimensional spaces. The volume of the cube will remain 1 unit d, but the volume of the touching sphere second problem is that LHS cannot be
will decrease as d approaches zero. All of the missing volume is in the spikes, and putting samples into easily extended; for example, the vec-
each spike to verify a design requires an exponentially increasing number of samples. This effect makes tor X = (0.1, 0.3, 0.5, 0.7, 0.9) is an LHS
a full corner analysis very time consuming for design verification. set for N = 5, but how can we place
Another nice high-dimensional image can be created if we plot the E8 lattice as a 3D projection a sixth sample without losing the
(Figure S5). Such an 8D lattice offers many more symmetries than typical 3D figures. Very beautiful! equidistant spacing? LDS solves these
A similar structure is the E24 lattice. Its symmetry group has 8,315,553,613,086,720,000 elements. problems, with minor degradation
This is beyond any picture a human could fully understand. for the one-variable terms. In 1D, one
extendable method would be to use a
sequence such as X = (0.5, 0.25, 0.75),
so we toggle to fill the gaps. Then, the
creating many MC fake results, we too small. In this way, we can avoid next extensions are nonperfect, but
can get stable statistics in millisec- getting overly optimistic, unrealistic we can go for X next = (0.125, 0.625,
onds because no circuit simulations yield estimates. For this reason, boot- 0.375, 0.875) to again achieve a very
are required. We can check how many strap techniques are often a part of good distribution, and the intermedi-
results are beyond a certain limit or more complex algorithms beyond ate sets are still much better than ran-
determine the interval in which we random MC. dom sampling. This scheme is quite
can find 90% of the results. Such inter- Model averaging and conservative old, and, for a long time, mathema-
vals could lead at least to an accuracy yield estimation can also be combined, ticians were not very active in this
estimation and to conservative yield and this can improve the reliability of field. However, in recent decades,
estimates. In [6], different methods yield estimates without requiring a huge often for financial mathematical mod-
are compared, and bootstrap is one number of MC points. The required els, LDS has become popular. This is a
of the preferable methods, at least number of MC points depends on the nice example of how math and appli-
if the original MC point count is not desired accuracy. If the design has a cations influence each other.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 45

 The random sampling error can be often
quantified, but the quantification of systematic
errors is somewhat more difficult.
In Figure 2, we compare sets cre-
ated by different sampling methods
regarding 2D space filling, mathemat-
ically quantified by the discrepancy
(D). D is directly connected to the
integration error f if this set is used
for MC sampling. A random set has
very bad space-filling characteristics
because all samples are independent,
so random gaps or crowds are quite
likely. In this context, LDS has much
better characteristics and much lower
discrepancy, but, unfortunately, these
advantages will almost disappear if
we inspect high-dimensional point
sets. With a typical MC point count,
such as N = 1,000, LDS would not be
significantly better for d ≥ 20. For this
point count, LDS behaves well approx-
imately up to d = 10; due to the curse
of dimensionality, there is no hope
that this will improve much in the
future. One method would help use of
the typically good lower dimensions
for the most important statistical
variables; however, most simulators
simply follow a random variable
assignment, and usually no reliable a
priori knowledge is available.
One such LDS problem can already
be seen in very low dimensions if the
point count is not very la’rge. Fig-
ure 3(c) nicely shows that, in many
variable combinations, we get much
better, smoother, and less erratic his-
tograms, as you would normally see
in random MC with such a low point
count. However, some combinations
still look very bad; the only way
to make them better is to use more
points or degrade other combina-
tions. This always happens because
the number of possible combinations
grows exponentially in dimension.
However, for engineers, something
beyond these qualitative descriptions
and concepts matters more, and
this, unfortunately, is not a strength
of mathematicians. Concepts do not
matter much until you are able to
present hard numbers: for example,
how much can we improve MC on cir-
cuits with LDS, or how big is the dif-
ference between the sigma method
and the counting method? Engineers
need this information for realistic
use cases. Such numbers depend
on the application and implementa-
tion of an algorithm, but there are
clear fundamental limitations: in
random-sampling processes, in LDS
due to the curse of dimensionality,
in modeling based on sampled data,
and so on.
One limitation is that, even if you
use a model able to give an almost
perfect fit, the information you collect
in your statistical analysis is limited.
Therefore, in all random-sampling
techniques, entropy comes into the
game. Interestingly, using the normal
Gaussian distribution as a model is
quite a good assumption regarding
entropy. Not only does the central
limit theorem justify its use; along
with the fact that, in the foundry-pro-
vided models, normal distributions
are often coded, it is also the kind
of model that makes, besides given
mean and sigma (standard deviation),
the “fewest further” assumptions.
The normal distribution is the
maximum-entropy model for a given
variance ^V = v 2h . More general maxi­­
mum-entropy techniques have be­­come
popular, such as fitting nonnormal
data. MLE entropy estimates are always
biased for finite N; that is, the sampled
data for fix N can range only up to a
certain number, whereas a true Gauss-
ian distribution extends to infinity. The
choice of feature might be a bit arbi-
trary, but entropy-based methods are
at least a good building block for con-
servative estimations.
What happens if we make too-
strong or wrong assumptions? You
could easily end up with yield esti-
mations that are far too optimistic.

1 1 1
0.9 0.9 0.9
0.8 0.8 0.8
0.7 0.7 0.7
0.6 0.6 0.6
x2

x2

x2

0.5 0.5 0.5

0.4 0.4 0.4
0.3 0.3 0.3
0.2 0.2 0.2
0.1 0.1 0.1
0 0 0
0
1
2
3
4
5
6
7
8
9
1

0
1
2
3
4
5
6
7
8
9
1

0
1
2
3
4
5
6
7
8
9
1
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.

x1 x1 x1
(a) (b) (c)

FIGURE 2: Different 2D point sets with N = 20. (a) A random set. (b) An LHS set. (c) An LDS set.

46 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

 XY Scatter Plot YZ Scatter Plot XZ Scatter Plot
1 1 1
0.9 0.9 0.9
0.8 0.8 0.8
0.7 0.7 0.7
0.6 0.6 0.6
y

z
0.5 0.5 0.5
0.4 0.4 0.4
0.3 0.3 0.3
0.2 0.2 0.2
0.1 0.1 0.1
0 0 0
0
1
2
3
4
5
6
7
8
9
1

0
1
2
3
4
5
6
7
8
9
1

0
1
2
3
4
5
6
7
8
9
1
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
x y x

(a)

Normalized 1D Projected Gaussian Data

4

1
Data y

–1

–2

–3

–4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Projection
(b)

Variable Itself Typical 1D Projection Bad Projection

1 1 1
0.9 0.9 0.9
0.8 0.8 0.8
0.7 0.7 0.7
Frequency

Frequency

Frequency

0.6 0.6 0.6

0.5 0.5 0.5
0.4 0.4 0.4
0.3 0.3 0.3
0.2 0.2 0.2
0.1 0.1 0.1
0 0 0
–2.5
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2

–3
–2.5
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
2.5
3

–2.5
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
2.5

2.5

x x x
(c)

FIGURE 3: A highly optimized nine-point 3D LDS set and some histograms and scatterplots based on it. (a) We can find three sample points in
almost any such red boxes, so the distribution is highly uniform. (b) The set converted to a 3D normal distribution and corresponding scatter-
plots (including different combinations). Only the variables themselves (green) lead to almost perfect normal distributions. (c) Some histograms
and kernel density estimation fits from the 3D set.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 47

 Concepts do not matter much until you are
able to present hard numbers.
For instance, fitting a uniform distri-
bution to your data could lead to an
ideal yield of 100% if your specifica-
tion value x is beyond the corner of
your uniform fit. Maximum-entropy
fits can avoid this in a systematic
way. Using the counting method,
you use no parametric model or a
model with as many parameters as
data points. Unfortunately, looking
only to pass and fail is acting like a
1-b analog-to-digital converter (ADC),
which is not famous for high resolu-
tion: it adds quantization noise, you
lose signal-to-noise ratio, and the CI
becomes wide.
Models are seldom right; usefulness
is a better criterion. Often an assump-
tion, such as normality, can lead to
almost correct results, although we
may know for sure that the underlying
true model is not Gaussian. However,
engineers should be skeptical because
a wrong model can also lead to com-
pletely overoptimistic or far too pessi-
mistic results. For instance, using C pk
in lower yield regions is not far from
using a kind of interpolation method,
but using C pk in higher regions (such
as C pk >1.5) is usually equivalent to a
risky extrapolation method.
An interesting question is whether
we can make a statistic of “nothing”—
for example, if our MC analysis shows
no fail event at all. This is obviously
a frequent problem when it comes
to high-yield verification, and many
special methods are known for these
kinds of rare-event problems.
Having no fails provides at least
some information, so we can make a
statistic out of “no fail”; for this and
other standard situations in MC result
interpretation, engineers should fol-
low common sense (being skeptical
if very little information is available),
apply basic rules (such as how many
points are required for a meaningful
MC analysis according to Table 1), and
have a certain quantitative feeling—
such as when electrical engineers
48 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
have a feeling for the charge of a
capacitor, the power dissipation in
resistors, or Ohm’s law and circuit-
simulator convergence problems.
Nonlinearity and MC
So far, we focused on problems aris-
ing from high dimensionality and
having many variables, but what
about nonlinearity? Obviously, a non-
linear transfer function will distort
the MC results, and, in such cases,
the assumption of normality should
not be used.
Often, designers can still make
good guesses on the resulting distri-
bution. For example, leakage currents
are generally related to exponential
functions, and that will often lead to
lognormal distributions, which are
almost as easy to treat as normal dis-
tributions; you need to deal with two
parameters but apply all calculations
to the log of the data.
However, here complexity can al­­
ready cause further problems, because
it is not only one variable that matters
but the sum or the worst-case scenario
of many; for example, the sum of two
independent lognormal random vari-
ables is not lognormal again! Another
example can be found in an ADC. The
offset voltage of a comparator usually
follows a normal distribution, but, for
a flash ADC and its differential nonlin-
earity differential nonlinearity (DNL),
the worst comparator in the ADC
matters, so the DNL of an 8-b ADC
is connected to the max 1f255 ^Voffseth,
and this gives an asymmetric distri-
bution; continuing to use a normal
approximation can lead to overop-
timistic estimations regarding yield
and DNL. The more complex a sys-
tem, the more specifications need
to be checked, and the higher the
probability that we must deal with
very difficult nonnormal data. Some
methods suffer quite a lot under non-
normality (such as C pkh, others only a
bit (such as the C gpk [4]), and, often,
less efficient methods do not suffer
at all (such as the counting method).
For more advanced methods, not only
does the histogram matter (and the
nonnormality we can see there) but
also the type of nonnormality, such
as how many variables with impact
on a certain performance histogram
behave nonlinearly and how differ-
ently they behave.
Only in a very few cases can non-
linearity be compensated for with a
transformation, such as using exp(X)
instead of X. Not all cases with asym-
metric histograms and exponential
functions involved lead to lognormal
data. The use of decibels on a simple
normal distribution leads to nonnor-
mal data, but, although the log func-
tion is used and although the data
become asymmetric, the data are still
not lognormal. This is another type of
distribution—a much uglier one.
Statistical Techniques Beyond
Verification
There is a certain gap between MC as
a mathematical integration method
and MC analysis used by engineers,
because not only integrals, yield, and
performance verification matter. If
there are problems, they need to be
analyzed, and the design needs to be
improved. In this light, a further disad-
vantage of the specification-distance
method becomes obvious: even if we
could prove or disprove a certain yield
level, we may have no MC sample that
shows how the design behaves when
it starts to fail. For debugging pur-
poses, having such a corner sample is
extremely helpful.
Random MC is not so cursed, but
LDS-based MC is cursed, and, unfor-
tunately, many other advanced tech-
niques also suffer from dimensionality
as well, such as finding such corners.
The usual meaning of corners in electri-
cal engineering terms is a combination
of parameters, such as maximum tem-
perature, lowest supply voltage, and
maximum load capacitance. That might
be the worst-case setting for a cer-
tain performance, such as delay time.
Also, certain process and mismatch
variables can be related to worst-case
performances. A major difference
between these statistical parameters
and the environmental ones is that
statistical parameters often follow a
Gaussian distribution, ranging from –∞
to ∞, so they have no fixed finite range,
such as VDD = ^1.8V, 2.2V h . However,
statistical corners can also be defined
if we assign a yield level, so we can cre-
ate, for example, 6v corners, a full set
of statistical variables, in which we just
touch the specification limit and have
6v yield. Usually, there are infinite
variable combinations that can exactly
hit the specification limit, but one of
these has the highest probability den-
sity: this is called a statistical corner.
These can be used for debugging and
testing circuit improvements, as we
can use normal environmental corners.
The yield depends not only on statis-
tical parameters but on full combination
with the environmental parameters. A
good way to make sure that a design
can be manufactured with high yield
is to inspect the design behavior at the
complete worst-case combination. Usu-
ally, these combined corners are quite
different for each specification; for
example, VDD max + Tmax +  FastProcess
might be the worst-case for leakage
current, but for dynamic range it might
be VDDmin + Tmax + SlowProcess.Some
performances are usually dominated
by mismatch, and here we can hardly
anticipate them; we would require indi-
vidual tool-created statistical corners.
Besides running an MC analysis
and hoping to hit such corners with
acceptable accuracy, we can also run
a dedicated search algorithm for this
task. A key technique following this
statistical corner idea is called the
worst-case distance method (WCD) [7].
Searching is mathematically related
to optimization, and MC can be
regarded as brute-force global optimi-
zation, in an inefficient random style.
Obviously, there is a good chance that
dedicated optimization algorithms be
can run much faster.
The speed of an optimization tech-
nique depends on the starting point,
but a short MC analysis can often pro-
vide quite a good one. A second factor is
important too: the number of variables,
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 49
WCD can deliver quite accurate statistical
corners, but it suffers, at least mildly,
from dimensionality.
and here we still must fight a bit against
dimensionality. The major advantage of
WCD is that at least there is no strong
exponential relation between the num-
ber of variables, which is the dimension
d of the search space and WCD vector
(the statistical corner), runtime t, and
point count N. Often, N increases “only”
quadratically with d.
Another characteristic of many
designs can help as well: d might
be huge, such as much greater than
500, but usually only a few variables
are important and contribute to the
WCD. A variable screening can speed
up the optimization part a lot, and
it also can also be done based on a
(midsize) MC run.
A further WCD advantage is that the
optimization time does not depend
much on the yield target, so even a 7v
WCD can be found almost as quickly
as a 5v WCD. This makes WCD a well-
suited method for high-yield verifi-
cation and for a full yield analysis
and optimization.
Why can WCD outperform MC so
well? Again, it is because WCD makes
better use of the data: WCD exploits
exactly how the statistical variables are
set, whereas, in MC, there is no need
for this for counting or specification-
distance evaluations; the variable set-
tings are completely ignored in all of
these histogram-based yield-verifica-
tion methods! In principle, WCD could
even skip the initial MC part and run
an optimizer and the statistical vari-
able setting directly. Unfortunately,
this would reduce reliability because
fast local optimizers will usually find
the true global optimum only if a good
starting point is used.
However, the situation might change
negatively in the future, with more
complex designs in which the number
of variables increases significantly;
the circuit blocks tend to have more
transistors (to implement calibration
structures or support multiple system
standards), and the transistor mod-
els become more complex as well. In
WCD, we could improve different parts
of the algorithm, such as the variable
screening or optimizers, but at some
point improvements will become very
hard, and you will simply need (much)
more simulation time, even for the
same kind of circuit (such as a band-
gap or active filter). Therefore, alter-
native methods have been created to
allow yield analysis beyond 5v. WCD
can deliver quite accurate statistical
corners, but it suffers, at least mildly,
from dimensionality.
One such technique is performance
modeling in combination with standard
MC [8]. To verify 6v, we would need
to simulate roughly 3 billion points
or more with random MC. However,
we can split this task: we first run an
MC analysis of moderate size (such
as 1,000 points) and create a perfor-
mance model that relates the statistical
input variables to the simulated circuit
performances. If we have an accurate
enough model, we could pass all the
remaining MC samples (that is, 3 bil-
lion – 1,000) to the model, and that, of
course, requires much less simulation
time. If we see fails, then we can double-
check this by passing only these critical
samples to the full circuit simulation.
In this way, such a model-based MC can
overall be much faster, and it would not
depend too much on the initial perfor-
mance models. The tricky part remains
the modeling task, but, like WCD, this
type of “sorted MC” works quite well for
electrical circuits if the implementation
is done very carefully.
Both methods still suffer signifi-
cantly from the curse of dimensional-
ity, and we need to run them for each
output individually; the more perfor-
mances that must be checked, the
smaller the advantage over MC. One
may wonder, are there methods that
suffer from complexity but not more
than random MC itself?

The promise of optimization is that it can be
performed in a more efficient way than just
running multiparameter sweeps.
Indeed, there is no completely
free lunch, but one successful trick
is to scale up MC. If we double the
sigma values of all input statisti-
cal variables, then the specification
distance in sigma will roughly go to
half. For a linear circuit and Gauss-
ian variables, this is an even, accu-
rate relation for any scaling factor s.
We can run an MC analysis with a
certain up-scaling factor (such as
s = 2.0) and obtain a certain yield
in sigma, such as Y ^s = 2h = 3.5v.
Then, we can calculate the potential
true, unscaled yield by correcting the
result, just by multiplying by s to get
Y ^s = 1h = 2 # 3.5v = 7v) .
Scaled-sigma sampling (SSS) [9],
[10] is another type of extrapolation
method, such as C pk, but it often
works very well, even for many non-
linear cases where C pk becomes very
misleading. For both techniques and
in general, a careful error estima-
tion needs to be implemented, and
we should not work too much in the
extrapolation region. In SSS, we have
a kind of intrinsic error checking by
comparing the yield estimates from
two (or more) different scale factors.
WCD is based not so much on extrap-
olation but, clearly, on approxima-
tion because we hope that the length
of the WCD vector b gives the yield
in sigma. This might be inaccurate,
especially if multiple fail regions
exist. In this case, most methods, such
as WCD, SSS, or sorted MC, become
problematic, and which one remains
at least somewhat accurate is highly
dependent on the test case. A small
parameter tweak can easily let one or
another method win.
A certain advantage of the scaled
MC technique is that we can extract
not only the yield regarding each indi-
vidual performance but also the overall
yield, taking all of our specifications
into account. If WCD or the sigma
method (C pk, C gpk, and so on) is used,
50 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
this is more difficult. For example, if
there are five specifications and we
get a vector of worst-case distances
b = (6.0, 6.5, 7.0, 6.5, 4.0), then the
total yield is obviously dominated by
the worst-case, or lowest, b, which
is 4.0 here. Often, one performance
dominates, but not always, and if we
have two critical, small WCDs such as
b = 4.0, then the overall yield would
certainly not be greater than 4.0, but
how large it really is depends on the
correlation between these two perfor-
mances. If they are correlated (as rise
time and bandwidth often are), then
b overall = min ^ bh is a good approxi-
mation; but, if these specifications are
fighting each other, then we should
calculate the loss p fail of both and
add the two losses to obtain the over-
all loss. This would give a somewhat
smaller value.
More general solutions are avail-
able, such as multivariate C pk and
even mixes of the sigma method and
the binomial pass–fail method [11].
However, these are more difficult to
calculate (even more so when extended
to nonnormal distributions). All sam-
pling-based methods have a natively
limited accuracy (for random sampling
represented by CIs), whereas WCD
works directly in the variable domain
and has almost no variance (but has
other disadvantages, such as from
multiple failure mechanisms or non-
linearity, difficulties in optimization,
and so on).
All In: Dimensionality
and Nonlinearity
A famous maxim of modern statistics
is “Let the data speak.” Assuming a
linear model, you often do not need
much data; even with a quadratic
model (often used in optimizations),
the onset of the curse of dimension-
ality is quite moderate. Our small 2D
and 3D examples are easy to under-
stand but probably do not fully illus-
trate how terrible the curse can be.
The ugly face pops up when we have
high-dimensional problems and non-
linearity, as in many designs. This can
break almost any algorithm.
When people try to break algo-
rithms, they typically use test cases
with known difficult functions, such
as x 2 or exp(x), 1/(1 – x), |x|, sin(100x),
and so on. On many of these, MC will
behave excellently because nonlin-
earity does not matter; only the varia-
tion in function f over the integration
region counts. However, often you
do not need difficult functions. For
example, you can pick a simple con-
tinuous function, such as x 1 + x 2 or
max (x 1, x 2), but increased in dimen-
sion to realistic values occurring in
electrical circuits.
Already, very simple counterexam-
ples can break great methods, such as
WCD [4], not because these methods
are bad but because they are based on
approximations; if you know how a
method works, you can easily break it.
In one dimension, the WCD worst-case
error on failure probability is just a
factor of two (because it can be left and
right sided). For high-sigma problems,
this is still a small error in sigma, such
as < 0.1v at 6v. However, in higher
dimensions, the error can reach up to
100% in absolute terms (so no limit
in terms of sigma!). Usually, you can
trust WCD results, and, in real-world
designs, the errors are generally fully
acceptable. However, we already saw
that WCD is a method that can suf-
fer considerably from dimensionality
because it has to deal directly with all
statistical variables, unlike random or
LDS-based MC.
What about competing high-yield
methods? SSS was patented in 2013
[9]; in 2015, some fuzziness in the
original algorithm was removed; and,
in 2016, [10] was awarded best paper
from preceding two years for qual-
ity, originality, subject matter, and
influence. However, in 2017, SSS was
falsified in [12]: a famous blog battle
in the EDA industry, it reads like a
crime novel for people with unlimited
IQ. What went wrong? The curse of
dimensionality!
 SSS runs like MC, and the individ-
ual scaled yield estimates are unbi-
ased. However, for the overall SSS
yield estimate, unbiased simply does
not exist for nonlinear functions; any-
thing can be only an approximation.
“Let the data speak” is often great if
you have a huge amount of data and
discrete features—for example, to
correctly identify a person based on
his/her habits—but it is impossible
here. Still, the assumed model has a
big impact on your estimates. Each
trick, such as WCD, SSS, or response
modeling, has its benefits and limi-
tations. Applying a single trick usu-
ally fits for electrical circuits; when
it comes to difficult circuits or to
making an algorithm robust, how-
ever, multiple mechanisms need to
be implemented to provide engineers
with correct error estimates or hints
on how the setup can be improved.
Further Key Design Topics
We have seen that yield v ­ erification
and analysis can easily become cursed,
difficult, and time-consuming tasks,
so they should be done in a system-
atic and efficient way. Verification
must include the full environmental
variable space, making a complete
verification even more cursed than
a pure statistical analysis. Focusing
on critical cases is the most efficient
way, but it is still a computation-
intensive task.
Based on overall worst-case cor-
ners, the design can be analyzed
further and improved. The latter is
mathematically an optimization task,
which also can be automated. Math-
ematical optimization is equivalent to
functional minimization of a function
f (or maximization of –f), but which
function? And isn’t this complex task
even more cursed?
Indeed, local and global optimiz-
ers have been available in many IC
design environments for many years,
but they are not very popular in IC
design—“driving” them is not easy.
The optimization result, the set of
circuit design parameters, depends
on which optimization goal func-
tion the user defines. The promise
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 51
The trend in circuit design is complexity, but
the key elements and number of key variables
will remain quite limited.
of optimization is that it can be per-
formed in a more efficient way than
just running multiparameter sweeps.
For instance, if we have 10 vari-
ables, such as the length and width
of important transistors, and we use
10 values for each parameter, we
could cover the search space with
a 10-by-10 sweep, which requires
10 10 simulations! Such a huge setup
would deliver many combinations
that surely are not optimum in any
way, whereas a clever adaptive search
engine, may require only a few hun-
dred simulations. In short, full global
optimization is cursed, but local
optimization not as much so; many
optimizers have proven quadratic
convergence and can find the opti-
mum of a quadratic function in n vari-
ables with approximately n 2 function
evaluations. In addition, the trend in
circuit design is complexity, but the
key elements and number of key vari-
ables will remain quite limited. For
instance, for an operational amplifier
of the same gain we may use struc-
tures that are a bit more advanced
(such as active cascodes), but there
are also constraints that limit the
complexity. For any stable feedback
system, we need a dominant pole,
and increasing the number of stages
too much will lead to more parasitic
poles so that, at some point, the sys-
tem might become unstable.
For optimization, the simple classi-
cal way is to define a single real-num-
bered goal function f, for example, as
the weighted sum of individual perfor-
mances (or their differences to a uto-
pian optimum performance). In this
way, the user receives a somewhat opti-
mized circuit, but the results depend
on the weighting factors, which usually
need to be set up front.
The more advanced method is to
allow the weight definition to select
the desired best compromise after-
ward, and this is possible with Pareto
optimization techniques. Many algo-
rithms were invented in the 1960s for
non-Pareto optimization, but good
techniques have also been developed
over the years for Pareto optimization
and applied to (small) circuit blocks
[13]—only their implementation in
the commercial EDA environment
is lacking. Figure 4 shows how a
designer can work with a Pareto opti-
mizer: the optimization result is a full
front of Pareto optimum circuit siz-
ings (green curve), and each point of
such a Pareto front is optimum in the
sense that it cannot be improved any
more without impairing other perfor-
mances. A simpler standard optimizer
would require setting the weights
up front; often, a somewhat good,
but nondesired, optimum would be
selected (such as the blue star in Fig-
ure 4). In a Pareto optimization, the
user can select the desired point (such
as the green star in Figure 4) directly
after the optimization, whereas a nor-
mal optimizer would require restart-
ing the optimization procedure with,
for example, a higher weight-for-noise
value. Of course, Pareto optimization
requires more runtime than a single
standard optimization, but, taking
into account restarts with different
weights, Pareto optimization often com-
petes and obviously offers a higher
level of automation.
IDD
Utopian Point NF
(NF Lowest and
IDD Lowest)
FIGURE 4: Pareto optimization of noise
figure (NF) and current consumption ^ I DDh .

Can we expect to find such highly advanced
methods as Pareto yield optimization soon
in commercial tools?
Can we expect to find such highly
advanced methods as Pareto yield opti-
mization soon in commercial tools?
Isn’t optimization always something
on top of verification and other design
steps? Yes, it is, but, once the overall
worst-case corners are found (although
the curse of dimensionality works
against us), then the optimization
part is no longer too difficult. In some
articles, even topology optimization
has been demonstrated successfully
[9]. This works best for well-defined
design problems, such as filters, oper-
ational transconductance amplifiers
or operational amplifiers. Of course,
the same algorithms can be applied
to almost all arbitrary designs, and
the engineer must make them well
defined: providing all specifications
relevant to find a good tradeoff, find-
ing a good starting point, and becom-
ing trained on such tools.
Conclusions and Outlook
After the introduction of transistor-
level circuit simulators in the late
1960s and their widespread adoption
in the 1980s, many tasks have been
made available in design environ-
ments, such corner and MC analy-
ses, automated search techniques for
worst-case corners and statistical cor-
ners, and circuit optimization. How-
ever, the quiver of math techniques is
still not empty. Many researchers have
demonstrated much higher levels of
automation and generality, especially
regarding optimization.
In addition to these big topics,
other little tricks can also help design-
ers. For instance, often a test bench
does not run well for all MC points;
for example, the simulation stop time
has been set too small to observe an
event, such as “output voltage ramped
up.” This leads to a mixed data set: for
many points you can extract correct
values for t startup, but for others the
data are not available, and we know
52 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
only that t startup $ t sim . Luckily, this is
enough information to create a reli-
able estimate. The so-called censored
MLE is often used in other fields of
science and engineering but not yet
in circuit design. There is no need
to extend the simulation time and
rerun the whole MC analysis. Thanks
to the maximum likelihood principle,
a small censorization will usually
degrade the accuracy only very little.
For many problems, we see that
there is indeed no almost-free lunch
because fundamental mathematical
limits exist, especially when it comes
to complexity. In these cases, math
cannot deliver results that go too far
beyond common sense. If something
is too good to be true, then it is often
not true.
Acknowledgments
We thank Michael Pronath from
MUNEDA (Munich, Germany) for the dis-
cussions on difficult algorithm aspects
and Cadence Design Systems R&D.
References
[1] S. Kotz and N. Johnson, Process Capability
Indices, New York: Taylor & Francis, 1993.
[2] M. R. Coglio, J. M. Coglio-Flórez, and A. Ren-
don, “Estimating process capability indices
for inaccurate and non-normal data: A
systematic literature review,” Quality Ac-
cess to Success, vol. 18, no. 158, pp. 50–59,
June 2017.
[3] H. Schmid and A. Huber, “Measuring a small
number of samples, and the 3v fallacy:
Shedding light on confidence and error in-
tervals,” IEEE Solid-State Circuits Mag., vol.
6, no. 2, pp. 52–58. 2014. doi: 10.1109/
MSSC.2014.2313714.
[4] S. Weber and C. Duarte, “Yield prediction
with a new generalized process capability
index applicable to non-normal data,” IEEE
Trans. Comput.-Aided Des. Integr. Circuits
Syst., vol. 35, no. 6, pp. 931–942, June 2016.
doi: 10.1109/TCAD.2015.2481865.
[5] N. J. A. Sloane, “The packing of spheres,”
Sci. Amer., vol. 250, no. 1, pp. 116–125, Jan.
1984.
[6] V. Picheny, N. H. Kim, and R. T. Haftka, “Ap­­
plication of bootstrap method in conser-
vative estimation of reliability with lim-
ited samples,” Structural Multidisciplinary
Optimization, vol. 41, no. 2, pp. 205–217,
2010.
[7] K. J. Antreich and H. E. Graeb, “Circuit op-
timization driven by worst-case distances,”
in The Best of ICCAD, A. Kuehlmann, Ed.
Boston, MA: Springer, 1991, pp. 585–595.
[8] A. Singhee and R A. Rutenbar, “Statistical
blockade: a novel method for very fast Mon-
te Carlo simulation of rare circuit events,
and its application,” in Proc. 11th DATE Conf.,
Mar. 2007, pp. 10–14.
[9] S. Jallepalli, E. K. Hunter, E. A. Maalouf, V.
M. Mooraka, and S. R. Parihar, “Scaled sigma
sampling,” U.S. Patent 8 806 418, Aug. 12,
2013.
[10] S. Sun, X. Li, H. Liu, K. Luo, and B. Gu, “Fast
statistical analysis of rare circuit failure
events via scaled-sigma sampling for high-
dimensional variation space,” IEEE Trans.
Comput.-Aided Des. Integr. Circuits Syst.,
vol. 34, no. 7, pp. 1096–1109. July 2015.
doi: 10.1109/TCAD.2015.2404895.
[11] A. Amiri et al., “A process capability index
for mixed binary-normal quality character-
istics,” Int. J. Qual. Eng. Technol., vol. 4, no.
1, 2014, pp. 66–79.
[12] M. Pronath, “MunEDA mocks both Solido
HSMC and Cadence SSS for lame Monte
Carlo,” Aug. 25, 2017. [Online]. Available:
http://www.deepchip.com/items/0575-02
.html
[13] T. McConaghy, P. Palmers, M. Steyaert, and
G. Gielen, “Trustworthy genetic program-
ming-based synthesis of analog circuit to-
pologies using hierarchical domain-specific
building blocks,” IEEE Trans. Evol. Comput.,
vol. 15, no. 4, pp. 557–570. Aug. 2011.
About the Authors
Stephan Weber (weberconnect@
freenet.de) received his master’s and
Ph.D. degrees in electrical engineering
from the Technical University Berlin. In
1990, he moved to the Hahn-Meitner
Institute for Nuclear Physics, where he
focused on the modeling of discrete
semiconductors and integrated circuits.
In 1995, he moved to Siemens/Infineon
Technologies, where he worked on
radio-frequency receivers and power
amps, among other things. He holds
more than 20 patents on analog circuits
and system topologies.
Cândido Duarte (candidoduarte@
fe.up.pt) received his Licenciatura and
Ph.D. degrees in electrical and com-
puter engineering (ECE) from the Fac-
ulty of Engineering of the University
of Porto (FEUP), Portugal. Since 2009,
he has been with the ECE Department
at FEUP as a lecturer in courses on
electronics, sensors, and instrumen-
tation. He is also a researcher at the
Institute for Systems and Computer
Engineering, Technology and Sci-
ence (INESC TEC) (formerly INESC
Porto). His research interests include
wireless transceiver architectures,
low-power mixed-signal design, and
CMOS circuits for mobile communica-
tion systems.

 CHAP TERS

IEEE SSCS Kolkata Chapter Holds Summer Activities

T
The IEEE Solid-State Circuits Society
(SSCS) Kolkata (India) Chapter spon-
sored two events last summer. On
25 July 2019, the Chapter along with
the IEEE Meghnad Saha Institute of
Technology, Kolkata Student Chapter,
jointly organized the lecture “An Over-
view of Analog VLSI Industry.” Priyanko
Mitra of Sankalp Semiconductor spoke
Digital Object Identifier 10.1109/MSSC.2019.2939446
Date of current version: 23 January 2020
about design flow and challenges in
analog circuit design. Students asked
questions, which led to a productive
discussion at the end of the lecture.
On 26 July 2019, the Department
of Electronics and Communication
Engineering, RCC Institute of Informa-
tion Technology, Kolkata, organized
a technical competition on circuit
design. The SSCS Kolkata Chapter and
the Institution of Engineers (India)
Student Chapter of the Electrical and
Computer Engineering Department
sponsored the event, with 34 students
participating. Students were tasked
with explaining their circuit designs
to the judge, Prof. C.K. Sarkar, chair
of the SSCS Kolkata Chapter. The top
three designs were presented awards.
Following the competition, Sarkar
gave a talk on current technological
trends in semiconductor research.
—Sagar Mukherjee

Students present their circuit designs during the competition. Audience members and judges of the circuit design competition.

Priyanko Mitra gives his lecture on the analog very-large-scale

Prof. Sarkar (left) with competition winners. integration industry.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 53

IEEE SSCS Bordeaux Chapter Organizes SSC Day

O
On 28 June 2019, the IEEE Solid-State
Circuits Society (SSCS) Bordeaux
University Student Chapter held SSC
(Solid-State Circuits) Day, a day of
technical talks, at the Integration:
From Material to Systems Labo-
ratory. The Chapter was happy to
welcome three eminent research-
ers: Prof. Asad Abidi from the Uni-
versity of California, Los Angeles;

The SSCS Bordeaux

Chapter organized
Prof. Abidi gives his talk “A Tripled Loop CMOS PLL That Synthesizes Frequencies With Low
SSC Day to promote Jitter and Spurs, Without Calibration.”
international
collaboration
on ICs.

Prof. Ramesh Harjani from the Uni-

versity of Minnesota, Minneapolis;
and Dr. Stefano Pellerano from Intel
Labs, Hillsboro, Oregon. Abidi, Har-
jani, and Pellerano delivered techni-
cal talks on three topics of interest
to the SSC community: “A Tripled
Loop CMOS PLL That Synthesizes Fre-
quencies With Low Jitter and Spurs,

Digital Object Identifier 10.1109/MSSC.2019.2939700

Date of current version: 23 January 2020 Dr. Pellerano presents “Quantum Computing: An IC Design Perspective.”

Prof. Harjani (front row, fourth from left), Prof. Abidi (fifth from left), and Dr. Pellerano (sixth from left) with attendees of SSC Day.

54 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Without Calibration,” “Integrated dc–
dc Converter Designs,” and “Quantum
Computing: An IC Design Perspec-
tive,” respectively.
The SSCS Bordeaux Chapter orga-
nized SSC Day to promote interna-
tional collaboration on ICs. The
day attracted more than 30 people,
including students, professors, and
local IEEE Members.

David Gaidioz, SSCS Bordeaux University Student Chapter chair (right), introduces Prof. Harjani. —Romane Dumont, David Gaidioz

IEEE SSCS Kansai Chapter Technical Seminar

Given by DL Keith Bowman

O
On 14 June 2019, IEEE Solid-State Cir-
cuits Society (SSCS) Distinguished
Lecturer (DL) Dr. Keith Bowman from
Qualcomm gave the tutorial “Adap-
tive and Resilient Circuits for Pro-
cessors” for the SSCS Kansai (Japan)
Chapter. B ow m a n’s w ide spr e a d
knowledge about designing adap-
tive and resilient circuits made for
an informative talk.
Dynamic device, circuit, and sys-
tem parameter variations degrade Keith Bowman from Qualcomm gives his talk in Kyoto.
processor performance, energy effi-
ciency, and yield across all market seg-
ments, ranging from small embedded
cores in an Internet of Things device
to large multicore servers. Bowman
introduced the primary variations
during the processor operational
lifetime, including supply voltage
droops, temperature changes, transis-
tor and interconnect aging, radiation-
induced soft errors, and workload
fluctuations. He also talked about the
Bowman (front row, center), SSCS Kansai Chapter officers, and lecture attendees.
negative impact of these variations on
processor logic and memory across a
wide range of voltage and clock fre- design techniques for implement- Integration Symposium in Kyoto,
quency operating conditions. To miti- ing adaptive and resilient circuits and Japan. More than 30 people attended
gate the adverse effects from dynamic highlighted the key desig n trad- and participated in thoughtful dis-
variations, he proposed many circuit eoffs and testing implications for cussion after the lecture.
product deployment.
Digital Object Identifier 10.1109/MSSC.2019.2939447 Bowman’s lecture was held fol- —Kazutoshi Kobayashi
Date of current version: 23 January 2020 lowing the 2019 Very Large Scale Vice-Chair, SSCS Kansai Chapter

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 55

The University of Limerick Holds Oversampled
Data Converter Design Course

T
The Circuits and Systems Research
Group (www.csrc.ie) of the Depart-
ment of Electronics and Computer
Engineering, University of Limerick
(UL), Ireland (www.ul.ie), held its fifth
annual two-day short-course “Selected
Topics in Mixed-Signal IC Design” in
Limerick on 24–25 June 2019. The
2019 course focused on oversam-
pled data converters, building blocks,
topologies, and limitations.
Course instructor Prof. Johns talks about mixed-signal IC design in Limerick, Ireland.
Eighty-six participants from the
Czech Republic, Switzerland, Spain,
England, Ireland, and other Euro-
pean countries attended the course.

The 2019 course

focused on
oversampled data
converters, building
blocks, topologies,
and limitations.

The course instructor, Prof. David A.
Johns from the University of Toronto,
has over 35 years of expertise within
the semiconductor sector, both at the
academic research level in industry.
His research interests include equal-
izers, amplifiers, line drivers for high-
speed digital communications, data
converters, phase-locked loops, and
general analog ICs.
The first half of the seminar focused
on operational amplifier design, spe-
cifically regarding stability, optimiza-
tion, low-power analysis, and biasing.
Digital Object Identifier 10.1109/MSSC.2019.2939448
Date of current version: 23 January 2020
The lecturers, organizers, and participants of the “Selected Topics in Mixed-Signal
IC Design” course.
Switched-capacitor circuit design was
also covered. The second half of the
course was devoted to oversampled
data converters [such as analog-to-dig-
ital converters (ADCs) and digital-to-
analog converters] used across a range
of speeds and resolutions. Particular
emphasis was placed on bandpass del-
ta–sigma ADCs and incremental ADCs
for sensor designs, with a final focus
on circuit-noise limitations.
Participants offered positive feed-
back and said that the course was rel-
evant to their work and research.
Building on the tradition of inviting
two guest speakers to present postlunch
lectures during the course, this year’s
theme was the topical subject Artificial
Intelligence and Machine Learning. Daire
McNamara, cofounder of Emdalo Tech-
nologies (www.emdalo.com), presented
“Real World AI Applications,” while Dr.
Tony Scanlan, senior research fellow at
the Circuits and Systems Research Cen-
tre, UL (www.csrc.ie), gave the lecture
“Computation for Deep Learning.”
—Hooman Reyhani

56 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

IEEE SSCS Oregon Chapter Hosts DL Sudhakar Pamarti

O
On 26 June 2019, the IEEE Solid-State
Circuits Society (SSCS) Oregon Chap-
ter held a technical seminar at the
Intel Hawthorn Farms Campus in Hill-
sboro, Oregon. SSCS Distinguished
Lecturer (DL) Dr. Sudhakar Pamarti,
University of California, Los Angeles,
delivered his lecture “Stable, Low-
Energy Clocking for IoT Applications”
to over 20 SSCS and IEEE Members.
Pamarti gave audience members an Sudhakar Pamarti delivers his talk to the IEEE SSCS Oregon Chapter at the Intel Hawthorn
in-depth overview of state-of-the- Farms Campus.
art start-up techniques for ultralow-
p o w e r c r y s t a l o s c i l l at o r s , t h e
dominant energy-consuming block
in Internet of Things devices. Attend-
ees asked many questions, creating
a lively discussion during and after
the talk.

—Richard Dorrance
Vice-Chair, SSCS Oregon Chapter

Digital Object Identifier 10.1109/MSSC.2019.2939449

Date of current version: 23 January 2020 Pamarti answers questions from attendees.

IEEE SSCS DL Zhihua Wang Visits Lehigh Valley Chapter

I
IEEE Solid-State Circuits Society
(SSCS) Distinguished Lecturer (DL)
Prof. Zhihua Wang from Tsinghua
University, Beijing, presented the
seminar “Binaural Hearing Aid Sys-
tem and the Intelligent Acoustic Sig-
nal Processing” at the SSCS Lehigh
Valley Section at Lehigh University,
Bethlehem, Pennsylva nia, on 21
August 2019.
Wang opened his presentation
by comp a r i ng t h e semiconduc-
tor and medical device industries.
Digital Object Identifier 10.1109/MSSC.2019.2939450
Date of current version: 23 January 2020
In some ways, the two sectors are
similar, such as in market volume. In
other ways, they are different: semi-
conductor companies do business
worldwide, whereas medical device
businesses are not yet strongly rep-
resented in China, so there is an op-
portunity for significant growth in
the future. In addition, the medical
devices sector is not dominated by a
small number of companies, so there
are opportunities for start-up enter-
prises to enter the market. Hearing-
aid technology is an important part
of the medical devices industry, and
it has used every advancement in
electronics including vacuum tubes,
transistors, integrated operational
amplifiers, and, as discussed in Wang’s
talk, the smartphone.
Wang presented some of the con-
straints involved in making a binau-
ral hearing aid, such as power con-
sumption, size, and communication
between two ears. For a hearing aid
to be effective, it must not simply
amplify all sound coming into the
ear but, rather, only the range of fre-
quencies where hearing has dimin-
ished for the individual. This means
that the hearing aid must be adapted
to the individual, at least initially.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 57

Wang described how this can be done
continuously using a novel adaptive
approach. As hearing-aid technology
advances, there is a need for reduced
size and much lower power consump-
tion, while advanced signal process-
ing is still required. Wang discussed
an approach that he is using: perform-
ing the power consuming signal pro-
cessing in a remote device while the
hearing aids broadcast the analog-to-
digital converted audio signals and
receive the processed result. Betty Nelson (left) with Prof. Wang at the SSCS Lehigh Valley Chapter. (Photo courtesy of
In this case, the remote device Dale Nelson.)
is a smartphone with an additional
plug-in device. The broadcast chan- way, performance becomes better on aid is a medical device, these concerns
nel must have very low latency and a day-to-day basis. must be weighed against the positive
high resolution, which means that a After the discussion, questions benefits of using the device.
specially designed wireless interface included concerns about privacy, wire-
is required. To fit the hearing aid, the less power levels, and how the device
smartphone is adapted to recognize may interact with the human body. —Richard Booth
voice cues from the user regarding These apply to many devices, includ- Webmaster,
the hearing aid performance. In this ing the smartphone. Since the hearing SSCS Lehigh Valley Section

IEEE SSCS Switzerland Chapter Hosts

Prof. Armin Tajalli at ETH Zurich

T
The IEEE Solid-State Circuits Society
(SSCS) Switzerland Chapter orga-
nized a lecture on circuits and sig-
naling co-design for ultrawideband
communications at ETH Zurich on
18 June 2019.
Prof. Armin Tajalli of the University
of Utah, Salt Lake City, gave a tutorial
on industrial problems in wireline
communication from the signaling
and circuit design perspective. The
meeting started with a brief introduc-
tion by Prof. Taekwang Jang, chair of
SSCS Switzerland.
Tajalli began his lecture began
by considering the requirements
of high-bandwidth links. Modern

Digital Object Identifier 10.1109/MSSC.2019.2939451

Date of current version: 23 January 2020 Prof. Jang (right) introduces Prof. Tajalli.

58 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE


Attendees listen intently to Tajalli’s lecture on high-speed data communication.
Tajalli lectures on circuits and signaling co-design for ultrawideband communications.
computing systems rely on high-band-
width data communication between
different units. From a computing
perspective, CMOS technology scaling
was successful until 2005 [1], when
heat dissipation began to limit the
single-core frequency, provoking the
development of multicore processors.
More recently (in approximately
2015), a study based on cost and fab-
rication yield reached the conclusion
that the optimal number of cores in a
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 59
multicore processor is eight and that
further integration should be per-
formed by including multiple chips in
a computing platform. In such a dis-
tributed system, chip-to-chip commu-
nication over very short distances is
a highly demanding topic of research.
According to Tajalli, many com-
panies are moving toward multichip-
module systems-on-chip because of
heat, yield, and performance concerns
[2]. This is where the data rate, as well
as energy consumption, is extremely
crucial. Due to a stringent power bud-
get, industry is seeking new design
methodologies to implement very
dense and energy efficient links.
The most critical limitation of
high speed is intersymbol interfer-
ence and equalization. The main
Due to a stringent
power budget,
industry is seeking
new design
methodologies to
implement very
dense and energy
efficient links.
focus of Tajalli’s talk was on archi-
tectural design and circuit tech-
niques that overcome this challenge
using data encoding on a many-
wire parallel bus and optimal bi­­
nary decoders.
The meeting was closed after ques-
tions by the audience on channel
crosstalk, linearity, speed limit, and
circuit topologies were answered.
—Taekwang Jang
Chair, SSCS Switzerland Chapter
—Michel Bron
Vice-Chair, SSCS Switzerland Chapter
—Mathieu Coustans
Secretary, SSCS Switzerland Chapter
References
[1] M. Horowitz, E. Alon, D. Patil, S. Naffziger,
R. Kumar, and K. Bernstein, “Scaling, pow-
er, and the future of CMOS,” in Proc. IEEE
Int. Electron Devices Meeting, 2005.
[2] N. Beck, S. White, M. Paraschou and S.
Naffziger, “Zeppelin’: An SoC for multichip
architectures,” in Proc. IEEE Int. Solid-State Cir-
cuits Conf. (ISSCC), 2018.
IEEE SSCS Kansai Chapter Hosts Technical Seminar
by DL Meng-Fan Chang

O
On 22 August 2019, IEEE Solid-State
Circuits Society (SSCS) Distinguished
Lecturer (DL) Prof. Meng-Fan Chang
from National Tsing Hua University
(NTCU), Hsinchu City, Taiwan, gave
the talk “Computing-in-Memory for AI
Chips: Trends and Challenges” for the
SSCS Kansai Chapter in Osaka, Japan.
Chang has served on many technical
conference committees in the past,
including for the IEEE International

DL Prof. Chang lectures in Osaka, Japan.

To mitigate the
bottleneck, beyond-
von Neumann
architecture is
required.

Solid-State Circuits Conference (ISSCC)

and the IEEE International Electron
Devices Meeting (IEDM).
Chang began his lecture by intro-
ducing several IC chips, such as non-
volatile memories [resistive random-
access memory (RAM), phase-change
memory, and spin-torque-transfer
magnetic RAM], nonvolatile logics, 3D
memories, low-power static RAM and
computing in memory (CIM), smart
memory, and CIM-based processors.
Chang noted that he has fabricated
more than 40 chips in 10 years. The
results were submitted to ISSCC, the
Digital Object Identifier 10.1109/MSSC.2019.2939452
Date of current version: 23 January 2020
Prof. Chang (fourth from left), SSCS Kansai Chapter officers, and lecture attendees.
Very Large-Scale Integration Sympo-
sium, the IEEE Asian SSC Conference,
the IEEE Design Automation Confer-
ence, and IEDM. He explained that
the von Neumann bottleneck limits
computer performance due to the
latency and bus widths between the
processor and memory. To mitigate
the bottleneck, beyond-von Neumann
architecture is required. Chang’s
research group at NTCU proposed a
concept of CIM using resistive RAM
for the Internet of Things (IoT) and
artificial intelligence (AI) chips. He
also introduced edge devices (such
as AI–IoT) using nonvolatile memory.
Chang concluded by stating that
interaction among devices, circuits,
systems, software, and applications
is needed to develop semiconductor
chips for the IoT and AI.
—Kazutoshi Kobayashi
Vice-Chair, SSCS Kansai Chapter

60 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

IEEE SSCS Seoul Chapter Hosts DL
Prof. Makoto Takamiya

D
Distinguished Lecturer (DL)
Prof. Makoto Takamiya, from
the University of Tokyo, Japan,
visited the IEEE Solid-State
Circuits Society (SSCS) Seoul
Chapter on 12 April 2019, pre-
senting his talk “Integrated
Power Management Circuits for
Energy-Efficient IoT Systems”
at Korea University, Seoul,
South Korea. The lecture cov-
ered the various challenges
and circuit design solutions of
integrated power management Prof. Takamiya presents “Integrated Power Management Circuits for Energy-Efficient IoT Systems.”
circuits. More than 40 attend-
ees, including graduate and
undergraduate students, researchers, mains, large current transients, and put buck converter, and a sub-0.1-V
and professors, enjoyed the lecture wide dynamic ranges. He also exam- input boost converter for thermoelec-
and follow-up Q&A session. ined recent issues in Internet of Things tric energy harvesting.
Takamiya first reviewed integrated systems that need high-power efficien- This talk provided a great oppor-
power management circuits with an cy at ultralow input voltage and output tunity to consider recent trends and
emphasis on several challenges, such current conditions. For design solu- development of integrated power
as the large number of voltage do- tions, he introduced several circuit ex- management circuits and was well
amples, including a sub-0.5-V digital received by attendees.
Digital Object Identifier 10.1109/MSSC.2019.2939453 low-dropout regulator (LDO), digital-
Date of current version: 23 January 2020 to-analog hybrid LDO, a sub-0.5-V in- —Hyung-Min Lee

Prof. Takamiya (middle behind the flag) with attendees of his talk.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 61

Kang, Sheikoleslami, and Aflatouni Deliver
IEEE SSCS Seminars in San Diego

T
This past quarter, the IEEE Solid-State integrated electronic-photonic co- categorized into two groups: electronic-
Circuits Society (SSCS) Webinar Program design and how it can profoundly assisted photonics, where integrated
and San Diego SSCS Chapter hosted impact data communication, signal analog, radio frequency (RF), millimeter-
three seminars at the Qualcomm cam- processing, imaging, and sensing. wave (mm-wave), and terahertz (THz)
pus in San Diego, California. Examples of such a co-design may be circuits are employed to improve the
On 8 August 2019, Dr. Seung Kang
from Qualcomm delivered his seminar
“Emerging Memories and Pathfinding
for the Era of Sub-10-nm System-on-
Chip.” He presented a broad overview
of phase-change memory, magnetore-
sistive random-access memory (RAM),
resistive RAM, and ferroelectric RAM
from the perspectives of device, design,
integration, reliability, and applica-
tions. Kang also provided insights on
the potential incorporation of these
emerging technologies in the Internet
of Things, security, automotive, and
machine-learning space. Alvin Loke (right) presents Dr. Kang with a certificate of appreciation.
On 23 August 2019, SSCS Education
Chair and Distinguished Lecturer Prof.
Ali Sheikholeslami from the University
of Toronto delivered a fundamentals
seminar, “Basics of Jitter in Wireline
Communications.” Sheikholeslami
reviewed the basic definitions of jit-
ter and its properties, the relationship
between jitter and phase noise, and the
effects of jitter on a wireline system. He
then described jitter transfer, genera-
tion, and tolerance and the methods
for characterizing, modeling, and sim-
ulating jitter before covering his recent
work on jitter measurement and miti-
gation techniques. Sheikholeslami also Prof. Sheikholeslami (front row, fourth from right) with attendees of his lecture at the
gave an afternoon lecture at the Univer- Qualcomm campus.
sity of California, San Diego, “Circuit
Intuitions: Looking Into a Node,” based
on his quarterly contributions to IEEE
Solid-State Circuits Magazine. The talk
was hosted by Prof. Ian Galton.
On 30 August 2019, Prof. Firooz
Aflatouni visited from the University
of Pennsylvania, Philadelphia, to pres-
ent “Electronic-Photonic Co-Design:
From Communication to Optical Phase
Control.” He made the case for an

Digital Object Identifier 10.1109/MSSC.2019.2939701

Date of current version: 23 January 2020 Prof. Aflatouni with attendees of his lecture at the Qualcomm campus.

62 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. Sheikholeslami accepts a certificate of appreciation from Alvin Loke at the University of California, San Diego.

performance of photonic systems; and grated RF, mm-wave, and THz systems. —Alvin Loke, Jeff Shi, Mohamed
photonic-assisted electronics, where Aflatouni proceeded to describe his Abouzied, Albert Chou,
photonic systems and devices are used group’s recent work on optical synthe- Alan Islas-Cital
to improve the performance of inte- sis and low-power laser stabilization.

2019 IEEE SSCS Summer Camp—HKUST ICDC Annual Symposium

T
The IEEE Solid-State Circuits Society
(SSCS) Hong Kong Student Chapter is
dedicated to creating an ideal plat-
form for researchers, engineers, and
young scholars to exchange ideas
and gain inspiration on potential
future technologies such as artifi-
cial intelligence (AI) and the Internet
of Things (IoT).
The SSCS Hong Kong Student
Chapter, together with the Hong Kong

Digital Object Identifier 10.1109/MSSC.2019.2939915

Date of current version: 23 January 2020 Prof. Cheng gives the opening remarks.

SSCS Summer Camp speakers and participants.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 63

University of Science and Technol-
ogy (HKUST) Electronic and Com-
puter Engineering Integrated Circuits
Design Center, coorganized the 2019
SSCS Summer Camp—HKUST ICDC
Annual Symposium on 9–10 August
2019. This year’s theme was AI- and
IoT (AIoT)-inspired IC designs.
The summer camp served not
only as a gateway for Student Mem-
bers and engineers to connect with

Twelve world- Prof. Mok presents additional opening remarks.

renowned academic
pioneers and
industry leaders
were invited to
share their insights
covering a wide
range of topics.

academic and industry leaders but

also inspired participants to par-
take in various sports activities.
Twelve world-renowned academic
pioneers and industry leaders were
invited to share their insights covering
a wide range of topics.
The symposium featured two tracks.
Track one focused on academic talks Prof. Lee delivers a lecture.

9 August 2019 SSCS Summer Camp—HKUST ICDC Annual Symposium

MORNING SESSION

9:00–9:15 Prof. Tim Cheng

Dean of Engineering
Prof. Philip Mok
Associate Dean of Engineering and director of ICDC
9:15–10:00 Prof. Patrick Yue “What Is AIoT-Inspired IC Design All About?”
Associate director, ICDC, and director of HKUST-Qualcomm
Optical-Wireless Lab
10:00–11:00 Prof. Hao Yu, SUSTech “Energy-Efficient and High-Throughput AI Edge Computing”
11:00–12:00 Prof. Nan Sun “New Ingredients in the Pot—Rethink Analog IC Design”
University of Texas-Austin
AFTERNOON SESSION

— Prof. Makoto Ikeda “Advanced Sensor Interface Circuit Design”

University of Tokyo
2:30–3:30 Prof. Yan Lu, University of Macau “Power Management IC Design for the IoT”
3:30–4:30 Prof. Zhao Zhang, Hiroshima University “Low-Power Phase-Locked Loops for IoT Applications”
4:30–5:30 Russell Lee
Technical director, Mentor Graphics “AIoT Driven IC Design”
6:00–10:00 Invited speaker and guest dinner (Chinese restaurant on campus)

64 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

 10 August
MORNING SESSION
9:15–10:00 Jeremy Chau “University Tech Transfer and Entrepreneurship in the AI Era”
CEO, Zeegle
10:00–10:45 Wei Wang “Next Generation AI Computing Platform”
Founder and CEO, Moffett AI
10:45–11:30 Prof. Jri Lee “NTU Spin-off MidasMicro Focusing on Energy-Efficient Optical Transceiver
NTU and founder and CEO, MidasMicro ICs for Data Centers”
11:30–12:30 Moderator: Prof. Patrick Yue Panelist: Panel discussion on “AIoT-Applications Inspired IC Startups:
Dr. Simon Law, director of the Technology Transfer Boom or Doom”
Center, HKUST
Dick Wei, PYJ-Dynasty Venture Fund
Jeremy Chau
Mr. Wei Wang
Prof. Jri Lee

1:00–2:00 Prof. Patrick Yue, HKUST Closing remarks on “What IEEE SSCS and ICDC Are Doing
in the AIoT Era?”
Inspiration From Hollywood—Clips From “A.I.” and “Minority Report”
Light lunch for all
AFTERNOON SESSION

3:00–6:00 Sports activities open session

Lab tour: IC Design Center and HQ Optical Wireless Lab
NTU: Nanyang Technological University; CEO: chief executive officer.

Prof. Yue during opening remarks. Prof. Lu presents a speech.

Prof. Yu delivers his lecture to attendees. Prof. Zhang gives a lecture to participants.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 65

Prof. Sun delivers a talk to audience members.
Prof. Ikeda presents a lecture to attendees.
Prof. Ikeda playing badminton with student members.
on the key circuit areas for enabling
the AIoT, such as AI-centric processor
design, low-power analog-to-digital
converters, power management ICs,
high-speed input/outputs, and phase-
locked loops. Track two focused on
industrial talks including AI and deep-
66 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
Jeremy Chau gives a lecture.
Wei Wang delivers a lecture.
learning algorithms for different appli-
cations, cloud versus edge computing
design methodology, and technology
transfers from academic and industrial
research labs to entrepreneurship.
After the technical talks, the orga-
nizing committee arranged a half-day
sporting event for attendees, who
engaged in basketball, ping-pong, and
badminton) at HKUST’s new ocean-
front indoor sport center.
For the first time, summer camp
participants had the opportunity
to use visible light communication
(VLC) technology to receive a copy
of the slides on their mobile devices.
Participants scanned the LED light
with the VLC function installed
in the lecture theater to download
the slides.
More than 50 students and engi-
neers, including 40 SSCS members
and student members, joined the
two-day summer camp.
—Li Wang, Sylvia Xuan Wu,
Patrick Yue
Yogesh Ramadass Delivers Lecture at Fudan University

O
On 23 July 2019, Yogesh Ramadass
gave a talk at the School of Microelec-
tronics, Fudan University, Shanghai,
China. The lecture, “Power Electron-
ics for the Future: Research Trends
and Challenges,” was organized by
the IEEE Solid-State Circuits Society
(SSCS) Shanghai Chapter.
Ramadass received his B.Tech.
degree from the Indian Institute of
Technology Kharagpur and his S.M.
and Ph.D. degrees from the Massa­
chusetts Institute of Technology, all in
electrical engineering. He is currently
Lecture attendees listen intently to Ramadass’ talk “Power Electronics for the Future: Research
the director of power management Trends and Challenges.”
R&D at Kilby Labs, Texas Instruments,
where he is involved in research and
product development efforts that verters, small form-factor converters his ongoing research efforts and the
explore high-power-density and low- for consumer electronics, nanopower challenges that lie ahead.
electromagnetic-interference auto- Internet of Things designs, and high- Prof. Zeng, Prof. Hong, Associate
motive and industrial switching con- voltage power systems. Prof. Chen, Associate Research Fellow
Ramadass’ talk examined trends Cheng, and their students attended
Digital Object Identifier 10.1109/MSSC.2019.2939702 in power electronics across different the lecture.
Date of current version: 23 January 2020 application spaces and described —Yun Chen

Ramadass (back center) with attendees of his lecture at Fudan University.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 67

IEEE SSCS-USTC Chapter Members Organize Autumn Excursion

T
The IEEE Solid-State Circuits Soci-
ety (SSCS) University of Science
and Technology of China (USTC)
Student Chapter arranged a trip to
the mountains in Anhui, China. On
17–18 November 2018, Prof. Fujiang
Lin and Prof. Lin Cheng, along with 30
student members, set out on the trip,
which was sponsored by the Micro/
Nano-Electronics System Integration
Center and the School of Microelec-
tronics, USTC.
The journey started in Hefei, and USTC faculty and students at the Shitai Mountain Town, where they visited natural caves
the first stop was the Shitai moun- and forests.
tain town. After a lunch of special
local dishes, members visited Ciyun, made its way to a forest, replete with ships with one another and allowed
a natural cave with underground riv- mountains, flowers, and waterfalls. members to explore nature and pro-
ers, stalactites, and various rock for- In addition, Chapter members vis- mote physical health.
mations. After the cave, the group ited the Yuanxi Dam, Xing yuetan
Underwater Park, and Suyue Bridge.
Digital Object Identifier 10.1109/MSSC.2019.2939703 The trip gave student members a —Muhammad Hunain Memon
Date of current version: 23 January 2020 chance to strengthen their relation- —Xu Yan

IEEE SSCS/Photonics Society Joint PES Institute of Technology

Bangalore Student Chapter Holds Inaugural Event

T
The People’s Education Society (PES)
Institute of Technology Bangalore Joint
Chapter of the IEEE Solid-State Circuits
Society (SSCS) and IEEE Photonics Soci-
ety held its first event on 16 October
2019, at the PES Electronic City Cam-
pus in Bangalore, India. The event
was organized in collaboration with
the IEEE Bangalore Section and intro-
duced the newly formed Joint Society
to students and promoted enthusiasm
toward future endeavors in the indus-
try. Word was spread prior to the event
The event commenced with an introduction
Digital Object Identifier 10.1109/MSSC.2019.2951638 of the Joint Chapter and its supporting IEEE Prof. Agrawal, Chapter chair, discusses the
Date of current version: 23 January 2020 Societies by Vidyuth, the Society secretary. future agenda for the Society.

68 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

It is a tradition to light a lamp before starting any auspicious event
or ritual. Dr. Kulkarni speaks about the benefits of joining the Chapter.

Dinesh Nair (left) is welcomed by Dr. Kulkarni. Dr. Shankar (left) is thanked for his presentation by Dr. Annapurna.

Dr. Shankar gives a talk about terahertz graphene technology and its challenges.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 69

through social media and classes to
ensure participation.
The event began with a traditional
lighting of the lamp and an invocation
song performed by a student. Dr. Sub-
hash Kulkarni, head of the Electronics
Department, welcomed the speakers
and discussed the benefits of join-
ing the Chapter. He was followed by
Dr. Bhawani Shankar, a student of Prof.
Mayank Srivastava (president of the
IEEE SSCS Bangalore Section) from the
Indian Institute of Science, Bengaluru,
and postdoctoral fellow at Stanford
University. In his presentation, Shan- The event organizers (from left): Dr. Annapurna, Dr. Shankar, Dr. Kulkarni, Dinesh Nair, and
Prof. Agrawal.
kar explained his current areas of
research, the importance of photonics,
and the large scope of this niche area, these technologies are to the next from the attendees. The top eight win-
creating considerable interest among generation of electronic devices. ners were given SSCS items as prizes.
the attendees. He discussed a career in solid-state The event concluded with the an-
Next, Dr. Annapurna, head of the devices and how a society, such as nouncement of the officers of the
Information Science and Engineering SSCS, can help members achieve pro- Society, who were chosen through a
Department and IEEE Student Branch fessional goals. highly selective interview process.
counselor, welcomed Dinesh Nair, The final part of the event included These new officers were told of
deputy director of GlobalFoundries. a technical quiz with basic questions their responsibilities and what the
Nair spoke about the current impor- from the photonics and solid-state Society will expect of them in the
tance of solid-state electronic devices, domains, which provided insight to upcoming year.
the progressive changes in the field these topics. The competitive atmo-
over the years, and how imperative sphere was met with an eager response —Mayank Agarwal

IEEE SSCS-USTC Student Branch Chapter Hosts

Prof. Songbin Gong

T
The IEEE Solid-State Circuits Soci-
ety (SSCS)–University of Science and
Technology of China (USTC) Student
Branch Chapter organized a talk on
17 October 2019. The lecture was
presented by Prof. Songbin Gong,
Department of Electrical and Com-
puter Engineering and the Micro and
Nanotechnology Laboratory, Univer-
sity of Illinois at Urbana–Champaign.
The event was held at the Micro/Nano
Electronic System Integration Center

Digital Object Identifier 10.1109/MSSC.2019.2951639 Prof. Gong leading an interactive question-and-answer session with Chapter members and
Date of current version: 23 January 2020 lecture attendees.

70 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. Gong presenting his lecture, “Radio-
Frequency Microsystems for 5G and
IoT Applications: From Acoustic Filters
and Circulators to Mechanically Driven
Antennas.”
Laboratory, School of Microelectron-
ics, w ith the assista nce of P rof.
Chengjie Zuo.
Gong discussed several new types
of radio-frequency microsystems that
can enable various front-end func-
tions, including filtering, radiation,
nonreciprocity, and equalization,
with unprecedented size, weight, and
performance for 5G and Internet of
SSCS Lehigh Valley Section Hosts Technical Presentation
by Prof. Maurits Ortmanns
P
Prof. Maurits Ortmanns, University
of Ulm, Germany, presented a semi-
nar, “Continuous-Time Delta–Sigma
ADCs for Receiver Applications,” for
the Lehigh Valley Section of the IEEE
Solid-State Circuits Society (SSCS) at
Lehigh University on 7 October 2019.
After a brief introduction to the
SSCS, the city of Ulm, and the Uni-
versity of Ulm, Ortmanns began his
lecture with a technical discussion
about the present-day wireless com-
munications environment, which is
Digital Object Identifier 10.1109/MSSC.2019.2951640
Date of current version: 23 January 2020
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 71
SSCS-USTC Chapter members with Prof. Gong (center).
Things (IoT) applications. Specifically,
the most recent developments in
lithium niobate microelectromechani-
cal systems resonators, filters, delay
lines, and circulators from 100 s MHz
to 30 GHz were presented. He also
spoke about crosscutting acoustics
and electromagnetics to miniaturize
antennas without compromising their
performance. After the talk, an inter-
characterized by a large number of
interfering signals caused by other
users on many adjacent channels.
Indeed, communication traffic is
increasing, and 4G and 5G carrier
aggregation may require (as one
option) wideband channels, neces-
sitating wideband analog-to-digital
converters (ADCs), many mixers, and
many local oscillators.
In a mobile radio receiver, the stron-
gest interfering signal is the onboard
transmitter; however, it is also chal-
lenging to reject strong adjacent chan-
nels. These signals are not rejected
early in the receive path and are, in fact,
active session was held, during which
Gong answered questions and shared
his experiences.
—Muhammad Hunain Memon and
Jiahui Shi
Cochairs, SSCS USTC Student Chapter
—Fujiang Lin and Patrick Yue
Advisors, SSCS USTC Student Chapter
first boosted along with the desired
signal. Therefore, very strong filter-
ing is required before analog-to-digital
conversion. A delta–sigma ADC offers
filtering capability that can reject the
quantization noise involved in the con-
version. Its signal-transfer characteris-
tic, then, is also of interest in the rejec-
tion of unwanted interfering signals. In
fact, a system with a delta–sigma ADC
might use the ADC itself as the final
bandpass and an anti-aliasing filter as
well as the final digitizer.
Ortmanns also discussed two alter-
native architectures in which the sig-
nal is digitized in the radio-frequency
domain and signal processing is done
in the digital domain; these require
bandpass or frequency-translating
delta–sigma converters. To reduce the
number and power of multiple local
oscillators, wide- or multiband ADCs
can be used, so there is much interest
in their development.
The filtering configuration in the
delta–sigma converter can be feedfor-
ward, feedback, or both. Any of these

In a mobile
Prof. Maurits Ortmanns giving his lecture “Continuous-Time Delta–Sigma ADCs for Receiver
radio receiver,
Application” at the SSCS Lehigh Valley Section.
the strongest
interfering signal
is the onboard
transmitter;
however, it is
also challenging
to reject strong
adjacent channels.

systems may produce identical noise-

and signal-shaping characteristics, but
each entails different physical chal-
lenges. For example, a feedforward
structure may offer smaller internal
signal swings, so it is less challenging
to maintain linearity. Because analog
elements dominate the analog inter-
nal signals in the delta–sigma ADC,
strategic scaling of signals within the
architecture as well as proper choice
of sufficiently linear elements is also
important. Feedforward configura-
tions may cause signal-transfer char-
acteristic peaking, which is more chal-
lenging to shape so that out-of-band
signals are sufficiently rejected. Sig-
nal- and noise-shaping functions can
be designed with the Schreier toolbox,
Ortmanns (fourth from left) with lecture attendees.
and Ortmanns demonstrated some
examples of how to use this toolbox.
One fascinating result that Ort-
manns described is the fact that the
filtering function can easily include a
notch to reject the known transmitter
blocking signal. Sampling-clock jitter is
a major problem for continuous-time
delta–sigma converters. The sampling
of out-of-band interferers folds back
into the digitized frequency range.
Moreover, out-of-band harmonics
quantization noise (of the delta–sigma
converter) folds back into the in-band
by way of digital-to-analog converter
phase noise. Once sampling is accom-
plished, jitter becomes less important
for signal corruption. To deal with
these issues, stronger signal-transfer-
function shaping is required. However,
using a filter notch for the transmit-
ter relaxes this requirement, and the
signal-to-noise ratio is improved. Ort-
manns’s talk was a very detailed and in-
teresting tour of the use of delta–sigma
converters in receivers.
— Angelo Mastrocola and
Richard Booth
IEEE SSCS, Lehigh Valley Section

72 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

IEEE SSCS Singapore Chapter and the Institute of Microelectronics
Organize a One-Day Short Course Presented by Prof. Nan Sun

T
The IEEE Solid-State Circuits Society
(SSCS) Singapore Chapter jointly with the
Institute of Microelectronics, Agency for
Science, Technology, and Research (IME
A*STAR), hosted a one-day short course
by Prof. Nan Sun from the Department
of Electrical and Computer Engineer-
ing, ­University of Texas at Austin. The
course, “Advanced ADC Design Tech-
niques,” was held on 16 July 2019 at IME
Science Park II, Singapore.
Digital Object Identifier 10.1109/MSSC.2019.2951641
Date of current version: 23 January 2020
Sun kicked off the short course by
introducing the latest development
trends in successive-approximation-
register (SAR) analog-to-digital con-
verters (ADCs), which mainly appear
in two directions on the roadmap: one
focus is on low-power SAR, and the
other is on high-speed SAR design. Sun
discussed the basics of low-power SAR
ADCs, such as the operation of SAR
and depth noise analysis in the struc-
ture and transistor levels. He provided
many design examples of high-speed
SAR ADCs, from system architecture
to logic circuit and least-significant-
bit correction.
In discussing sparkle-code reduc-
tion, Sun introduced the compara-
tor metastability reason based on
transistor-level analysis. Because
metastability depends strongly on
the time parameter and input sig-
nal value, a tunable clock block
and an even-probability-monitoring
scheme improve ADC performance.
Sun ended this part of his lecture by
introducing a design from his group:
an integrated asynchronous clock,

Prof. Sun presents the short course Approximately 60 participants from local universities, research institutes, and multinational
“Advanced ADC Design Techniques.” companies attended the short course.

Sun (front row, far right) with SSCS Singapore Chapter members and the course participants.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 73

metastability detector, random dither
injection, and background calibra-
tion function.
Recently, SAR ADCs integrat-
ing delta–sigma noise shaping have
become a popular topic, and many
high-performance ADCs based on new
structures have been implemented.
Sun reviewed earlier designs and
divided this technology into two cat-
egories: 1) delta–sigma ADCs using an
SAR quantizer and 2) SAR ADCs with
IEEE SSCS Poland Chapter Connects Engineers
Through Technical Talks
T
The IEEE Solid-State Circuits Society
(SSCS) Poland Chapter coorganized
and hosted several interesting events
at the AGH University of Science and
Technology, Kraków. The sessions
brought together many young people
from throughout Poland; they focused
on microelectronic circuit design and
enhancing the quality of microelec-
tronics teaching.
Digital Object Identifier 10.1109/MSSC.2019.2951642
Date of current version: 23 January 2020
Willy Sansen (left center) and Randy Caplan (right center) with attendees of the three-day course at the AGH University of Science and
Technology, Kraków, Poland.
74 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
noise-shaping capability. SAR is suit-
able to act as a quantizer but must
meet the system’s speed require-
ments. Sun provided a few design
examples illustrating how to achieve
noise shaping in SAR ADCs.
Sun concluded by considering mis-
match error. Mismatch is a generic
problem in feedback digital-to-analog
converters. If used smartly, a dynamic
element-matching structure even sup-
plies noise shaping.
On 9–11 April 2019, Willy Sansen
(Katholieke Universiteit Leuven, Bel-
gium) joined Randy Caplan (Silicon
Creations) to deliver a series of lec-
tures on different aspects of micro-
electronic circuit design. The pre-
senters introduced phase-locked-loop
design and discussed the noise per-
formance of transistor stages, stabil-
ity of operational amplifiers and their
configurations, offset and common-
mode rejection ratio effects, and band-
gap circuits. More than 120 people
Sun’s talk attracted 60 participants
from industry, research institutions,
and the academic community, includ-
ing Broadcom, Infineon, Media Tek,
IME, the National University of Sin-
gapore, and Nanyang Technological
University. Audience members were
very interested in the topic and many
asked questions.
—Jianming Zhao
SSCS SG Committee Member
attended this event, including not only
AGH students in the microelectronics
branch but also employees of Silicon
Creations as well as those of research
institutes and microelectronics com-
panies throughout Poland.
On 30–31 July, more than 80 people
attended a two-day course taught by
Dr. Charvaka Duvvury on the basics,
circuits, and techniques of electrostatic
discharge (ESD). ESD phenomena are
essential for successful microelectronic
product design, and circuit robustness
Attendees of the Kraków Quantum Informatics Seminar with Prof. Bogdan Staszewski (center).

electronic circuits for quantum-com-

puting applications. On 21 May 2019,
Pieter Harpe (Eindhoven University
of Technology, The Netherlands), an

A system-level
approach for an ESD
protection strategy
is essential for
feasible high-speed
designs.

expert on low-power, mixed-signal

Dr. Charvaka Duvvury (front left) with Randy Caplan during the two-day course on ESD in microelectronics, presented “Basics
microelectronics at AGH University of Science and Technology, Kraków, Poland. of Successive-Approximation-Register
Analog-to-Digital Converters: Circuits
and Architectures.”
needs to be addressed at not only the protection. He also addressed ESD Chapter volunteers were also deeply
chip level but also the system level. A aspects for silicon-on-insulator and fin involved during the 49th European
system-level approach for an ESD field-effect transistor technologies. Solid-State Device Research Conference
protection strategy is essential for The SSCS Poland Chapter also (ESSDERC)/45th European Solid-State
feasible high-speed designs. Duvvury sponsored several other activities, Circuits Conference (ESSCIRC), held
discussed multiple aspects of ESD-tar- including a lecture by Prof. Bogdan in September in Kraków. A full report
geted design, beginning with the fun- Staszewski (University College Dub- on the ESSDERC/ESSCIRC appears on
damentals of ESD, electrical overstress, lin, Ireland) on 30 January 2019. Dur- page 87.
and latch-up and moving on to stress ing the Kraków Quantum Informatics
models, test standards and techniques, Seminar, Prof. Staszewski introduced —Krzysztof Kasinski
and design options for advanced ESD topics related to cryo-CMOS micro- Vice-chair, SSCS Chapter Poland

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 75

2019 Baltimore Mini-Colloquium: Next-Generation
Technologies for 5G and Beyond

W
With support from the IEEE Electron
Devices Society’s (EDS’s) Mini-Collo-
quium program (MQ), the EDS and IEEE
Solid-State Circuits Society (SSCS) Balti-
more Joint Chapter hosted its seventh
annual Fall Colloquium on 9 October
2019. The theme was Next-Generation
Technologies for 5G and Beyond. This
one-day event featured a slate of three
IEEE EDS Distinguished Lecturers (DLs)
and six presenters from the Baltimore/
Washington community; together,
they represented diverse perspectives,
with two speakers from industry, three
from government laboratories/institu-
tions, and four from academia. The
The 2019 Baltimore MQ was chaired by Dr.
Pankaj Shah of the U.S. Army Research Lab,
The MQ agenda displayed in the lobby at who also delivered the final presentation of
This one-day event the American Center for Physics. the program.
featured a slate
of three IEEE EDS
Distinguished
Lecturers and six
presenters from
the Baltimore/
Washington
community.

site of the MQ was the American Cen-

ter for Physics, near the University of
Maryland College Park campus.
The morning session was led by
Colloquium Chair and Chapter Trea-
surer Dr. Pankaj Shah from the U.S.
Army Research Lab. The afternoon
sessions were led by Chapter Chair
Dr. Paul Potyraj from Northrop Grum- Attendees were quick to take advantage of promotional items provided by the SSCS.
man Corporation and Chapter Vice-
Chair Dr. Richard Fu. Cosponsored The full-day panel of speakers
by the Washington/Northern Virginia included the following:
Chapter for Electron Devices, the ■■ Dr. A. Bandyopadhyay (GlobalFound-

event drew 36 attendees, including ries): “Silicon Technologies for 5G

29 IEEE Members and seven nonmem- Enhanced Mobile Broadband Radio”
bers. Mirroring the speakers, partici- ■ ■ Dr. Paul Lane (National Science

pants included representatives from Foundation): “Advances in Devic-

industry, government, and academia, es and Circuits for Next-Genera-
including students. tion Communications”
■■ Dr. Patrick Fay (University of Notre
EDS DL Dr. Patrick Fay from the University
Digital Object Identifier 10.1109/MSSC.2019.2951643 Dame, South Bend, Indiana): “Advanc- of Notre Dame discussed advances in
Date of current version: 23 January 2020 es in III-N Devices for 5G and Beyond” III-N devices.

76 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

■■ Dr. Mario Miscuglio (George Wash-
ington University, Washington,
D.C.): “Photonics for Neuromorphic
Computing”
■■ Dr. Mina Rais-Zadeh (University of
Michigan, Ann Arbor, and NASA
Jet Propulsion Laboratory): “Phase
Change Radio-Frequency (RF) to
Optical Microdevices”
■■ D r. R o b e r t Yo u n g ( N o r t h r o p
G r u m m a n ): “ D e v e l o p m e n t o f
Third-Generation Germanium-
Telluride-Based Phase Change RF
Switches”
Region 8 Chapter Chairs Meeting at ESSCIRC 2019
T
The IEEE European Solid-State Circuits
Society (SSCS) Chapter chairs meeting
was held on 25 September 2019 dur-
ing the European Solid-State Device
Digital Object Identifier 10.1109/MSSC.2019.2951644
Date of current version: 23 January 2020
Attendees of the Region 8 Chapter chairs meeting at ESSDERC/ESSCIRC 2019, (from left): Chris Rudell, Joao Olivera, Filip Tavernier, Stefan Rusu,
Pawel Grybos, Donnacha O’Riordan, and Krzysztof Kasinski. In the background are paintings of the rectors of the Jagiellonian University in
Kraków.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 77
EDS DL Dr. Mina Rais-Zadeh from the
University of Maryland during her
presentation.
Research Conference (ESSDERC)/Euro-
pean Solid-State Circuits Conference
(ESSCIRC) in the conference center
of Jagiellonian University in Kraków,
Poland. This annual event brings
together European Chapter chairs
with the SSCS Administrative Commit-
■■ Dr. David Meyer (Naval Research
Laboratory): “Transition Metal Ni-
tride Materials and Devices for Fu-
ture RF Electronics”
■■ Dr. Aristos Christou (University
of Maryland, College Park): “Crys-
tal Defects in Gallium Nitride and
Diamond Electronics”
■■ Dr. Pankaj Shah (Army Research
Laboratory): “Transfer-Doped Dia-
mond Field-Effect Transistors for
Next-Generation RF Applications.”
—Paul Potyraj
tee leadership to review recent Chap-
ter activities and exchange ideas for
future events.
The meeting opened with Stefan
Rusu, SSCS Chapters coordinator,
welcoming participants and high-
lighting the importance of local
Chapters for the growth of the Soci-
ety. Rusu presented an update on
the growth in SSCS Chapters, includ-
ing a summary of the subsidies and
awards available to support Chapter
activities. As of December 2019, the
Society had 113 chapters, with sev-
eral more in the pipeline. The SSCS
Distinguished Lecturer (DL) program
enables experts from industry and
academia to present, at the Chapter
level, information about the latest
technology developments.
The activities of the Portugal,
Poland, Benelux, U.K./Ireland, Swit-
zerland, and Seattle Chapters were
reviewed. Highlights included DL
visits, meetings with figures from
academia and industry, local techni-
cal conferences cosponsored by SSCS
Chapters, and short courses organized
by local Chapters. The IEEE Poland
Chapter organized ESSDERC/ESSCIRC
2019 as well as ­multiple distinguished
lectures. The IEEE U.K./Ireland Chapter
sponsored the Microelectronics Cir-
cuits Center Ireland Technical Confer-
ence in March 2019, with 12 technical
papers presented over four sessions.
The Benelux Chapter spawned a Stu-
dent Chapter at Katholieke Universit-
eit Leuven to promote microelectron-
ics for M.S. and Ph.D. degree students
and bridge the gap between industry
and academia.
The next Chapter chairs meet-
ing was scheduled at the IEEE Asian
Solid-State Circuits Conference in
November 2019 to be followed by
another meeting the International
Solid-State Circuits Conference in
February 2020.
—Stefan Rusu
IEEE Fellow, SSCS Chapter Coordinator

Six San Diego SSCS Seminars in September and October 2019

T
The San Diego IEEE Solid-State Cir-
cuits Society (SSCS) Chapter recently
hosted six seminars at the Qual-
Digital Object Identifier 10.1109/MSSC.2019.2951645
Date of current version: 23 January 2020
comm campus in San Diego, Cali-
fornia, drawing a local attendance
ranging from 35 to almost 100.
On 26 September 2019, past SSCS
Distinguished Lecturer (DL) Daniel
town Heights, New York) presented
the seminar “Hybrid Phase-Locked-
Loop (PLL) Architectures and Imple-
mentations.” Combining the advan-
tages of analog proportional and
Friedman from IBM Research (York- digital integral paths, hybrid PLLs

Attendees at the seminar presented by Daniel Friedman (center).

The attendees gather following the seminar by Shanthi Dr. Pavan (behind podium).

78 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Alvin Loke (right) presents a certificate of appreciation to Pavan (left) enjoying a morning canyon hike with Loke and Hasnain
Dr. Friedman. Lakdawala.

Attendees following the talk by Gabriele Manganaro’s talk (center, holding certificate).

Participants who attended the presentation by Mial Warren (center left in dark jacket).

implemented in advanced CMOS
nodes offer reduced dependence
on special technolog y elements,
reduced PLL area without a large inte-
grating capacitor, improved testabil-
ity, and new functionality. Friedman
described the progressive develop-
ment of a feature-rich frequency syn-
thesizer enabling a wide continuous
tuning range of 2–26 GHz using two
voltage-controlled oscillators (VCOs),
flexible programmability and con-
trol of the loop transfer function,
fractional-N synthesis without sacri-
ficing performance, sub-square-mil-
limeter area, fast-frequency settling,
and reduced spurious content. His
lecture will be broadcast as an SSCS
webinar at a future date.
On 30 September 2019, past SSCS
DL Shanthi Pavan from the Indian
Inst it ute of Technolog y Madras
delivered the seminar “Dissecting
Design Choices for Power-Efficient
Continuous-Time Delta–Sigma Con-
verters.” Pavan made a strong case
for implementing finite-impulse-
r esponse ( F IR) feedback , wh ich
offers the benefits of a simple 1-b
analog-to-digital converter (ADC),
reduced ADC power and area, sim-
plified clock distribution, inherently
linear digital-to-analog converter to
obviate dynamic element matching,
relaxed integrator linearity and jitter
requirements, and free chopping. FIR

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 79

Manganaro (third from left) with Chapter members during lunch of Korean barbecue before
his talk.
feedback leverages the benefits of
1-b and multibit operation to achieve
the highest reported Schreier figure
of merit. Furthermore, it is process-
agnostic, with the aforementioned
benefits realized irrespective of tar-
get specifications.
On 3 October 2019, SSCS DL Gabri-
ele Manganaro visited from Analog
Devices (Wilmington, Massachusetts)
to present “Mixed-Signal Technologies
for Ultrawideband Signal-Processing
Systems.” The talk was motivated
by the ever-increasing consumer
demand for connectivity that is driv-
ing the need for 5G massive multiple-
input/multiple-output/beamforming
and corresponding advances in base-
station infrastructure. Manganaro
argued that, with technology scaling
not keeping up with mixed-signal
performance requirements, precision
high-performance data converters
require frequent architectural inno-
vations to meet market demand. This
set the stage for discussing time-inter-
leaved, continuous-time pipelines and
VCO-based ADCs as well as increasing
dependence on digital circuitry to
achieve up to 14-b resolution and 12-G
sample/s performance.
80 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
On 16 October 2019, Dr. Paul
Rousseau from Taiwan Semiconduc-
tor Manufacturing Company (TSMC)
North America (San Jose, California)
covered “TSMC’s Excellent Adventure
This was an
informative
and enjoyable
overview of the
exciting prospects
of integrating
lidar systems
for autonomous
driving.
Into 7 nm and Beyond.” He provided
an overview of the market segments
driving the insatiable demand for
advanced CMOS technologies and
described samples of TSMC’s 7- and
5-nm offerings.
On 18 October 2019, Prof. Sub-
hanshu Gupta from Washington State
University (Pullman) gave the talk
“Integrated True-Time-Delay-Based
Large-Scale Arrays for Spatially Diverse
Applications.” He provided an over-
view of phase-arrayed beamforming
approaches in wireless receivers and
A certificate of appreciation is presented to
Warren.
proposed two discrete-time-delay com-
pensation architectures to overcome
receiver design challenges. The first
is an interpolating time interleaver to
generate multiphase clocks that drive
a switched-capacitor adder. The second
provides spatial interference cancel-
lation using a media-access control-
compute engine employing a truncated
Hadamard transform matrix.
Finally, on 22 October 2019, Dr. Mial
Warren from TriLumina (Albuquerque,
New Mexico) presented “Navigating
Automotive Lidar Technology.” This
was an informative and enjoyable over-
view of the exciting prospects of inte-
grating lidar systems for autonomous
driving. Warren provided a brief history
of lidar development for autonomous
vehicles before describing the require-
ments of automotive and current lidar
technologies, namely, the flash and
scanned lidar approaches. High cost
remains the primary gating factor to
widespread adoption, but advances in
silicon-based detection technologies
could be the game changer.
—Alvin Loke, Albert Chou,
Alan Islas-Cital, Jeff Shi, and
Mohamed Abouzied
IEEE SSCS DL Paul Wesling Visits SSCS Lehigh Valley Chapter

I
IEEE Life Fellow Paul Wesling, [Hewlett-
Packard (retired) and past commu-
nications director for the IEEE San
Francisco Bay Area Council] presented
the lecture “The Origins of Silicon Val-
ley: Why and How It Happened” for the
Lehigh Valley Section of the IEEE Solid-
State Circuits Society (SSCS) at Lehigh
University on 25 September 2019.
Wesling began by motivating the
audience with an anecdote about how
the famous Silicon Valley innovation
partnership of Steve Wozniak and
Steve Jobs grew their venture from a
garage in Los Altos to the most valu-
able brand in the world. He asked,
“How could this happen?” and “Why in
the San Francisco Bay area?”
Wesling continued with a concise
history from the agricultural days of SSCS Lehigh Valley Chapter Chair Robert Peruzzi (right) thanks Paul Wesling for his lecture
1880 to the formation of Federal Tele- and visit.
graph and the invention of the Audion
vacuum tube in the early 1900s. A in a spirit of competitiveness and pete clauses, and he concluded with
key concept of Federal Telegraph was collaboration that carried forward to a reading list of recommended books.
raising funds from angel investors the Home Brew Computer Club and In keeping with the spirit and phi-
(an early example of venture capital) today’s Silicon Valley. By 1947, Silicon losophy of Silicon Valley, Wesling made
and close involvement with Stanford Valley was the “big dog” of electron- his slides and a video recording of his
University, California. Current events, ics centers, and, by the 1960s, it was talk available. The slides can be found at
economic motivation, and, especially, central to the U.S. defense effort and http://www.pwesling.com/docs/1909b
independent wealth available from the the manufacturing economy. Wesling -wesling.pdf, and the video record-
California gold rush played roles. spoke about the Silicon Valley business ing can be accessed at https://www
The ham radio subculture of cama- climate, contrasting its decentralized .youtube.com/watch?v=lRDB_W6POys.
raderie and egalitarianism resulted structure to the East Coast’s large, ver-
tically integrated firms. He made the —Robert O. Peruzzi
Digital Object Identifier 10.1109/MSSC.2019.2951646 important point that, since the 1870s, Lehigh Valley Section SSCS
Date of current version: 23 January 2020 California has not enforced noncom- Chapter Chair

Wesling (right) presents his talk on the origins of Silicon Valley.

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 81

An Exciting Year of Events for the SSCS Seattle Chapter

T
The newly formed IEEE Solid-State
Circuits Society (SSCS) Seattle Chap-
ter, Washington, had an exciting year
of events in late 2018–2019. Chris
Rudell, Chapter chair, and Visvesh
Sathe, Chapter vice-chair, hosted
speakers in the field of IC to provide
informative and innovative talks on
the latest developments in the field.
The inaugural event held by the SSCS
Seattle Chapter was a presentation
by Alvin Loke (Qualcomm) in December
Brian Ginsburg gives a radar presentation to students, faculty, and IEEE Members. Some IEEE
SSCS Seattle Chapter presentations are sponsored jointly with the University of Washington
Digital Object Identifier 10.1109/MSSC.2019.2951647 Department of Electrical and Computer Engineering’s Colloquium series. The presentations are
Date of current version: 23 January 2020 professionally filmed and will be placed online for viewing by SSCS members.

Dr. Bertan Bakkaloglu presents state-of-the-art work on voltage Chapter Chair Chris Rudell (left) and Bakkaloglu at the University of
regulation. Washington.

The attendees listen to Bakkaloglu’s talk.

82 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

 (From left) Rudell, Visvesh Sathe (Seattle SSCS Chapter vice-chair),
(From left) Rudell (SSCS and CAS Seattle Chapter chair), Joe Decuir (IEEE Brian Ginsburg (Texas Instruments), Prof. Sumit Roy (University
Life Fellow), Alon Newton (IEEE Seattle chair), Alvin Loke (Qualcomm), of Washington), Joe Decuir, Prof. Jenq-Neng Huang (University of
and Titus Lo (Microsoft Research) with several Chapter members. Washington), and Prof. Matt Reynolds (University of Washington).

2018 at Microsoft Research Building
99. Loke presented the lecture “Ana-
log/Mixed-Signal Design Challenges
in 7-nm CMOS and Beyond.”
On 8 October 2019, the Chapter
held a joint forum with the Univer-
sity of Washington Department of
Electrical and Computer Engineer-
ing’s weekly colloquium series. Brian
Ginsburg of Texas Instruments gave
the talk “Millimeter-Wave Imaging
for Automotive and Beyond,” which
sparked significant interest among
attendees. More than 100 students
and IEEE Members attended the pre-
sentation, which will eventually be
made available on video.
As a continuation of the lecture
series organized by the University
of Washington and the SSCS and IEEE
Circuits and Systems Society (CAS)
Seattle Chapters, Bertan Bakkaloglu
of Arizona State University, Tempe,
presented “High-Power-Densit y,
Fully Integrated Voltage Regulators for
High-Performance Digital-Core Supply
Management” on 22 October 2019. The
talk was well attended by students,
faculty, and local IEEE Members.
—Chris Ruddell and Visvesh Sathe


We want
to hear
from you!
IMAGE LICENSED BY GRAPHIC STOCK

Do you like what you’re reading?

Your feedback is important.
Let us know—send the editor-in-chief an e-mail!

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 83

 PEOPLE
In Step With Gabor Temes
Decades of Experience in the Laboratory
P
Prof. Gabor Temes’ journey to become
an engineer was not an ordinary one.
He took the unbeaten path to become
a circuit designer. He did not know
from an early age that he wanted to
be an engineer, and he did not dream
of it since he was a little boy, but he
became one of the greatest engineers
in the field of analog circuits.
Temes was born in 1929 in Buda-
pest, Hungary. This was a tumultu-
ous time because Hungary was an
early ally of Nazi Germany. By his
15th birthday, Budapest was sur-
rounded by the Soviet army. Temes
and his family struggled during this
time, fighting starvation. However,
he managed to graduate from high
school in 1948. After graduation,
Temes grappled with the idea of his
future. He was close to graduating
from the Academy of Music as a con-
cert violinist. However, he also was
very interested in engineering.
Temes credits the
IEEE (which was the
Institute of Radio
Engineers when he
joined) for being an
excellent resource
as he was beginning
his career.
“To become a success as a profes-
sional musician, you need extraor-
dinary manual skills, motivation,
and discipline. I didn’t think I had
Digital Object Identifier 10.1109/MSSC.2019.2952729
Date of current version: 23 January 2020
84 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
Prof. Gabor Temes.
these attributes,” Temes said. So he
chose engineering. The rest, as they
say, is history.
Temes graduated from the Tech-
nical University of Budapest (TUB)
in 1952. He started working in the
Department of Theoretical Electric-
ity at TUB while still a student and
stayed on as a faculty member after
graduation. During his time there,
Temes designed and built counters,
counting rate meters, and high-volt-
age sources for these experiments.
He also researched nuclear phys-
ics instrumentation, circuits, and
plasma physics.
In 1956, following Joseph Stalin’s
death, there was an uprising in Hun-
gary. Temes and his wife, Ibi, along
w ith thousands of Hungarians,
decided to flee the country. Arriv-
ing in Vienna, Austria, after a long
and debilitating journey, Temes and
his wife settled down, and Temes
worked as a technician at the Tech-
nical University of Vienna.
After a short stay in Vienna, Temes
and his wife immigrated to Canada
in 1957, a nd he st a r ted to work
at the Université de Sherbrooke’s
School of Medicine in Québec. Later
that year, he joined Measurement
Engineering Ltd., where he designed
instruments to measure the viabil-
ity of bull sperm, brightness of pulp
and paper, and clarity of beer. He
then moved on to Northern Electric
Co. Ltd, to work as a filter designer
for its R&D laboratory. He developed
novel filter-design techniques along
with his colleagues John MacDonald
and Brian Smith.
In 1964, Temes became head of
the Light Electronics Group at the
Stanford Linear Accelerator Cen-
ter, California. This change of pace
and move to warmer temperatures
and sunshine were just what he and
his wife needed. A few years later,
Temes decided to go back to circuit
design and accepted a position at
Ampex Corp., where he managed the
design of analog signal-processing
circuits. He designed filters, equal-
izers, and tunable delay lines for
time-base control.
The article is part of a series highlight-
ing an SSCS member in each issue of the
magazine. If you would like to nominate
a member to be featured or would like to
be featured yourself, please email News
Editor Abira Altvater (Abira.Altvater@
ieee.org.)
Temes (in the yellow shirt), his past and present students, and Oregon State University faculty members celebrating Temes’ 90th birthday.

Temes then joined the University

of California Los Angeles (UCL A)
in 1970, where he was one of the
key people to help with building a
strong electrical circuits program. At
UCLA, Temes worked on computer-
assisted design topics as well as the
abstract properties of linear circuits
and systems. He also finished up a
coauthored book on linear circuit
design, which was a core text for
graduate courses in many schools.
Between 1975 and 1979, Temes was
chair of the Electrical Engineering
Department at UCLA, leading it to
be ranked as the sixth best electri-
cal engineering department in the
United States.
The exodus from Hungary. Temes and his wife, Ibi, are on the left.
In 1980, Temes became a consul-
tant to Xerox Microelectronics, which
developed ICs for copy machines In 1990, it was time for a change
and other Xerox products. In 1985, again. Temes headed to Oregon State “IEEE allowed me
he went on a sabbatical leave to University (OSU) to head the Elec- to learn through
the Swiss Federal Institute of Laus- trical and Computer Engineering
publications and
meetings, rather
anne (EPFL), where he helped create Department. He is still at OSU today,
than in isolation.”
MEAD Education, which organized teaching courses and carrying out
short courses at EPFL. research funded by three grants
and gifts from semiconductor com-
panies. Temes’ recent research has (IEEE Press, 1997), and Understand-
dealt with CMOS analog ICs, as well ing Delta-Sigma Data Converters
FUN FACTS ABOUT GABOR as data converters and integrated (Wiley/IEEE Press, 2005). In addi-
He
■  loves to hike with his students sensor interfaces. tion, he has published more than
in McDonald Forest on Saturday Temes is coeditor or coauthor of 300 papers in engineering journals
­mornings. several books, including Modern Fil- and conference proceedings.
■  He likes to read and to listen to classi- ter Theory and Design (Wiley, 1973), Temes is a Life Fellow of the IEEE,
cal music. Introduction to Circuit Synthesis and corecipient of the IEEE Circuits and
■  He played competitive bridge when Design (McGraw-Hill, 1977), Analog Systems Society (CAS) Darlington
he was younger. MOS Integrated Circuits for Signal Award in 1968 and 1981, and recipi-
■ He now plays canasta. Processing (Wiley, 1986), Oversam- ent of the 1984 Centennial Medal of
pling Delta-Sigma Data Converters the IEEE. He received the Andrew

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 85


Temes during a hike with his students.
Chi Award from the IEEE Instrumen-
tation and Measurement Society in
1985, the Education Award from CAS
in 1987, the CAS Technical Achieve-
IEEE connects you to
a universe of information!
As the world’s largest professional
association dedicated to advancing
technological innovation and excellence
for the benefit of humanity, the IEEE
and its Members inspire a global
community through its highly cited
publications, conferences, technology
standards, and professional
and educational activities.
Visit www.ieee.org.
Publications / IEEE Xplore ® / Standards / Membership / Conferences / Education
86 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
ment Award in 1998, the IEEE Mil-
lennium Medal in 2000, and the
CAS Golden Jubilee Medal in 2000.
He also received the IEEE ­Gustav R.
Kirchhoff Award in 2006, IEEE CAS
Mac Van Valkenburg Award in 2009,
and OSU College of Engineering
Research Award in 2010. In 2015,
Temes was elected to the National
Academy of Engineering.
Temes credits the IEEE (which was the
Institute of Radio Engineers when he
joined) for being an excellent resource
as he was beginning his career. “IEEE
was a blessing for me starting as a cir-
cuit designer at Northern Electric in
1959,” Temes said. “It allowed me to
learn through publications and meet-
ings, rather than in isolation. This
blessing has now grown to monstrous
dimension, with more papers and con-
ference talks appearing than what can
be followed by an old engineer.”
—Abira Altvater
Reference
[1] G. Temes, “Fifty-five fun-filled years in
circuit design,” in IEEE Solid-State Circuits
Mag., vol. 5, no. 2, pp. 8–21, Spring 2013.

IMAGE LICENSED BY INGRAM PUBLISHING

European Summit on Solid-State Device and Circuit Research
Double Conference in Kraków, Poland
T
The joint 49th European Solid-State
Device Research Conference (­ESSDERC)
and the 45th European Solid-State Cir-
cuits Conference (ESSCIRC) was held in
Kraków, Poland, on 23–26 Septem-
ber 2019. With approximately 550
participants from 42 countries attend-
ing, ESSDERC/ESSCIRC was a great event.
Statistically, 48% of the participants came
from academia, 38% from industry, and
14% from research and development
(R&D) centers. This representation dem-
onstrates how important this conference
is for industry and R&D centers.
The aim of the ESSDERC/ESSCIRC is
to provide an annual European forum
for the presentation and discussion of
recent advances in solid-state devices
and circuits. The two conferences run
Digital Object Identifier 10.1109/MSSC.2019.2951652
Date of current version: 23 January 2020
The Steering and Organizing Committees of ESSDERC/ESSCIRC 2019 in Kraków.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 87
CON FERENCE REPORTS
in parallel, share plenary keynote pre-
sentations, and are governed by a
joint steering committee. The confer-
ences are technically cosponsored by
the IEEE, with the ESSCIRC financially
sponsored by the IEEE Solid-State
Circuits Society (SSCS) and the ESS-
DERC sponsored by the IEEE Electron
Devices Society. The conferences in
Kraków were co-organized by the AGH
University of Science and Technology
(AGH UST) in Kraków, Jagiellonian Uni-
versity Kraków, Warsaw University
of Technology, and the Center for
Advanced Materials and Technologies
(CEZAMAT) in Warsaw. The conference
chairs were Pawel Grybos (AGH UST,
Kraków) and Maciej Ogorzalek (Jagiel-
lonian University Kraków); the Techni-
cal Program Committee (TPC) chair
of ESSDERC was Thomas Skotnicki
(Warsaw University of Technology and
CEZAMAT) and the TPC chair of ESS-
CIRC was Bogdan Staszewski (Univer-
sity College Dublin).
Kraków
The magical city of Kraków is the sec-
ond-largest municipality in Poland.
Located in the southern part of the coun-
try on the Vistula River, it is the capital
of Lesser Poland Voivodeship. Kraków is
a place where history and tradition inter-
twine with culture, modern technology,
and economic development.
Officially rooted in the 13th cen-
tury, its history is much older. Since
serving as the capitol of the Crown of
the Kingdom of Poland from 1038 to
1569, it has never stopped thriving as
an economic and cultural center, and the
uniqueness of this place has not gone
unnoticed. The entirety of Kraków’s his-
toric center (Old Town) is on the United

Kraków’s Old Town is on the UNESCO World Heritage list.
Nations Educational, Scientific, and
Cultural Organization (UNESCO) World
Heritage list. It is recognized for having
the largest medieval market square in
Europe and for its architecture, origi-
nating from the Gothic through the
Renaissance and Baroque eras. The
Royal Wawel Castle, the seat of Polish
kings and their largest necropolis, is a
diamond that rules over the landscape
of the city.
Another important feature of Kraków
is its academic prowess. With over 650
years of scholarly tradition, the city has
one of the oldest universities in Europe
(Jagiellonian University). Currently,
it is home to five major universities
(with AGH UST leading in engineer-
ing research) and numerous schools
of higher education, creating a total
population of approximately 200,000
students. The high-tech landscape in
Kraków continues to expand. It boasts
a special economic zone (Kraków Tech-
nological Park) for major high-tech
investments, with several major R&D
centers focused on industrial electron-
ics and software, four enterprise incu-
bators, three commercial fairgrounds,
and seven higher schools of econom-
ics. Over 100,000 private businesses
88 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
and nearly 2,000 public firms conduct
business in Kraków.
Paper Submission
The ultimate success of a conference
is based on the support of the authors
who submit their papers. This year,
the ESSDERC/ESSCIRC received a total
of 345 submissions, of which 235 con-
tributed to ESSCIRC and 110 to ESS-
DERC. About 56% of the submissions
came from Europe, 24% from Asia, and
20% from North America, demonstrat-
ing the international character of the
conference. The TPC held a meeting on
20 May in Warsaw at CEZAMAT. Mem-
bers of each of the 15 tracks selected a
total of 164 best papers, grouped into
40 regular and three focus sessions.
Joint Plenary
The conference had four plenary key-
note speakers. Edoardo Charbon (École
Polytechnique Fédérale de Lausanne)
presented “Cryo-CMOS: 60 Years of
Technological Advances Toward Emerg-
ing Quantum Technologies”; Franck
Arnaud (STMicroelectronics) presented
“28-nm FDSOI Platform With Embed-
ded PCM for IoT, ULP, Digital, Analog,
Automotive, and Other Applications”;
123RF.COM
Toshio Yanagida (Osaka University)
delivered the talk “Single-Molecule
Nano-Science: Noise and Function of
Life”; and Donhee Ham (Harvard Uni-
versity) presented “Copying Brain With
Semiconductor Technology.”
ESSCIRC Keynote
The ESSCIRC featured three keynote
presentations. Ram K. Krishnamurthy
(Intel) gave the talk “Machine Learning
and Hardware Security Technologies
for the IoT Era: Challenges and Oppor-
tunities”; Jeff Walling (Tyndall National
Institute) presented “Leveraging the
Switched Capacitor Power Amplifier
for Future Communications Systems”;
and Pieter Harpe (TU Eindhoven) deliv-
ered the talk “Low-Power SAR ADCs:
Trends, Examples, and Future.”
ESSDERC Keynote
The ESSDERC also featured three key-
note presentations. Michael Heuken
(AIXTRON SE) gave the talk “GaN-Based
HEMT Technology for Power and RF
Applications”; Subhasish Mitra (Stan-
ford University) presented “The N3XT
1,000X for the Coming Superstorm
of Abundant Data: Carbon Nanotube
FETs, Resistive RAM”; and Jong-Ho Lee
A conference session in the Auditorium Maximum, Jagiellonian University. (Source: Foundation for AGH UST; used with permission.)

(Seoul National University) presented

“Review of Promising Devices for Neu-
romorphic Applications.”

Tutorials
On Monday, 23 September 2019, there
were seven excellent tutorials and a Si
Nano workshop with over 200 partici-
pants. The parallel tutorial presenta-
tion covered topics such as nanoscale
technology and transistor modeling,
Kofi Makinwa delivers a talk during the SSCS Diversity Luncheon.
circuits and systems enabling quantum
technologies, 5G radios, low-power
radio-frequency and analog circuits,
jitter and phase noise, and terahertz
technologies and Internet of Things
devices. These provided additional
opportunities for updating knowledge
in the state-of-the-art technology in the
areas covered. Selected tutorials were
recorded as part of the SSCS Education
Program; the SSCS will release these
recordings free of charge to members
in the coming months.

SSCS Diversity Luncheon

The SSCS Women in Circuits Group
sponsored a luncheon on 24 Septem-
ber 2019 to discuss ways of increas-
ing diversity in the SSC community.
The luncheon featured talks by indus-
try and academic professionals who
shared career experience where a chal-
lenge, project, or mentor helped them
become a better engineer and problem
solver. The meeting was chaired by
Viola Schäffer (Texas Instruments),
and the panelists were Kofi Makinwa,
The Young Professionals Micro-Mentoring and Career Coaching Event.
(Delft University), Téa Williams (Texas Young Professionals and Students
Instruments), and Maud Vinet (French Micro-Mentoring and Career Coaching
Alternative Energies and Atomic Energy Session, which brought together over
Commission Leti). 50 participants. During the event,
leading experts from industry and aca-
SSCS Young Professionals Event demia shared their experiences with
On 23 September 2019, the IEEE Poland young engineers and students. Stu-
Section and the SSCS organized the dent volunteers played an important

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 89

role in ensuring the success of the
ESSDERC/ESSCIRC conferences.
Postconference Publications
and Awards
All presented ESSDERC/ESSCIRC papers
were sent to IEEE Xplore after the
conference. Authors of outstanding
articles from ESSCIRC were invited to
submit their work to a special issue
of IEEE Journal of Solid-State Circuits,
while authors of outstanding ESSDERC
papers were invited to submit work to
a special issue of IEEE Journal of the
Electron Devices Society. For the first
time in ESSCIRC history, there will
be copublication of qualified papers
in IEEE Solid-State Circuits Letters.
Student volunteers from AGH UST with members of the local organizing committee.
The welcome reception at AGH UST. (Source: Foundation for AGH UST; used with permission.)
90 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
As many as 38 outstanding ESSCIRC
papers have been accepted after addi-
tional editorial and quality reviews to
the special issue of IEEE Solid-State Cir-
cuit Letters and will be posted online.
Papers presented at the conference
are considered for the Best Paper
Award and Best Young Scientist Paper
Award. The award ceremony will be
held at ESSDERC/ESSCIRC 2020 in
Grenoble, France.
Social Events
The conference also included an ex­­
tensive social program. During the
welcome reception at AGH UST, par-
ticipants met with representatives
from national and local authorities.
The reception was kicked off by the
reading of a letter to participants writ-
ten by Andrzej Duda, president of the
Republic of Poland. President Duda
welcomed the conference partici-
pants and emphasized how important
Poland is in its active role in the devel-
opment of microelectronics. The hon-
orary patrons of ESSDERC/ESSDERC
included the Ministry of Entrepreneur-
ship and Technology, the Ministry of
Science and Higher Education, the
Ministry of Digital Affairs; the Mayor
of Warsaw, the Mayor of Kraków; the
rector of AGH UST, the rector of Jagiel-
lonian University, and the rector of the
Warsaw University of Technology.
The gala dinner took place at the
Wieliczka Salt Mine, which is among
the oldest salt mines in Europe and
appears on the UNESCO World Heri-
tage list. During the gala dinner, the
Obsession quartet gave a short con-
cert, a musical and humorous journey
through the world of sounds that sur-
round all of us, regardless of our musi-
cal preferences.
The conference social events offered
ample opportunities for networking.
Corporate sponsors of ESSCIRC/ESS-
DERC 2019 were Rigaku Corporation,
Xilinx, SK hynix, Silicon Creations,
ABB, TechInsights, Cadence Academic

(a) The gala dinner at the Wieliczka Salt Mine and (b) representatives of the corporate sponsors of ESSDERC/ESSCIRC 2019. (Source: Foundation
for AGH UST; used with permission.)
Network, Nordic Semiconductor, the
Micron Foundation, Analog Devices,
XFAB, SCALINX, KIOXIA Corporation,
STMicroelectronics, EUROPRACTICE,
Cambridge University Press, Springer,
and River Publishers.
Looking Forward: ESSDERC/
ESSCIRC 2020 in Grenoble,
the French ­“Silicon Valley”
“A blend of mountains, lifestyle, and cos-
mopolitan culture, Grenoble stands out
from other cities in France and Europe
for its proximity to the Alpine chains,”
notes the announcement for ESSDERC/
ESSCIRC 2020 Grenoble, continuing,
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 91
(a)
(b)
With 450,000 inhabitants, it is
the most important European
metropole in the heart of the
Alps. For more than 150 years,
the men and women of this
area have created a unique sys-
tem, built on close relationships
between the companies, the uni-
versities, and public research
labs. In the heart of Auvergne-
Rhône-Alpes (second g ­ reatest
French economic region, eighth
E u r o p e a n) a n d f i v e m aj o r
com­­petitiveness clusters, the
Grenoble-Alpes Metropole is
one of today’s most innovative
European territories in sectors
including micro and nanotech-
nologies, software, life sciences,
and energy. It is the second
French regional research center
with 25,000 researchers, five
major European instruments
(such as Institut Laue–Langevin
and the European Synchrotron
Radiation Facility), and eight
national research organizations
(such as the French Alternative
Energies and Atomic Energy
Commission), and five clusters.”
 —Pawel Grybos
IMESS 2019
AI, 5G, and IoT: Technology Convergence for Betterment of Humanity
T
The IEEE Malaysia Electron Devices
Society (EDS), IEEE Microwave Theory
and Techniques Society (MTT-S), and
IEEE Solid-State Circuits Society (SSCS)
Penang Joint Chapter organized the
fourth IEEE International Microwave,
Electron Devices, and Solid-State
Circuits Symposium (IMESS) on 8–9
October 2019, at the Penang Skills
Development Center (PSDC). Since
the inaugural meeting in 2016, the
IMESS has been recognized as a flag-
ship IEEE event in northern penin-
sular Malaysia. The theme of IMESS
2019 was Atificial Intelligence (AI),
5G, and IoT: Technology Convergence
for Betterment of Humanity. It was a
successful event with approximately
200 participants from industry and
academia exchanging ideas regard-
ing topics related to microwaves,
electron devices, and SSCs. IMESS
2019 featured keynote speeches, Distin-
guished Lecturers, and technical talks
Digital Object Identifier 10.1109/MSSC.2019.2951654
Date of current version: 23 January 2020
The IMESS 2019 opening ceremony.
92 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
by academia and industry experts;
sponsor exhibitions; a design com-
petition co-organized with FILPAL Pte.
Ltd.; and a student technical visit
to the Penang Design Center of the
Plexus Islandview plant.
The IMESS has remained admis-
sion-free since 2016, owing to strong
support from industry. IMESS 2019
received funding support from indus-
try sponsors FILPAL, Motorola Solu-
tions, MFS Technology, QDOS, QRF
Solutions, Smartrac Technology, Syn-
vue, Career Growth, Elliance, and
Robert Bosch. IMESS 2019 was also
supported by IEEE Region 10; the
EDS, MTT-S, and SSCS; the Institution
of Engineers, Malaysia; the Institu-
tion of Engineering and Technology;
investPenang; the IEEE Nanotechnol-
ogy Council; the Penang Convention
and Exhibition Bureau; PSDC; and stu-
dent volunteers from Universiti Sains
Malaysia (USM).
The symposium kicked off with a
keynote speech by Prof. Ewe Hong Tat,
president of Universiti Tunku Abdul
The IMESS
has remained
admission-free
since 2016,
owing to strong
support from
industry.
Rahman. Tat shared his view on tech-
nology revolution, ­economic evolu-
tion, and moving forward to develop
human capital to deal with new chal-
lenges in engineering and education.
Penang’s Deputy Chief Minister I of
Penang, Datuk Ahmad Zakiyuddin
Abdul Rahman, represented the chief
minister and gracefully officiated at
IMESS 2019 during the afternoon.
The opening ceremony started with
a welcoming address by the IMESS
2019 chair, Ir. Dr. Lee Choo Yong. He
noted that technology is a double-
edged sword and that we must use
technology wisely for the betterment
of humanity in areas such as autonomous
driving, faster and easier commu­
nication, interactive learning, and
seamless connectivity, all of which
enable smart cities, smart agriculture,
and more.
The ceremony continued with a
speech by Muhamed Ali Hajah Mydin,
chief executive officer of PSDC. He
emphasized that PSDC was establish­­
ed to develop talent in s
­ ­upporting
industry. Since 2016, PSDC, as the
Center of Excellence for Industry 4.0 in
Penang, has initiated many programs
to support companies moving toward
Industry 4.0. One of these programs is
the Penang Manufacturing Excellence
Conference and Exhibition.
This speech was followed by an
opening address by Deputy Zakiyud-
din, who noted that the IMESS 2019
theme was closely associated with

THE SPEAKERS AND TOPICS AT IMESS 2019.

SPEAKER AFFILIATION TITLE
Keynote Address
Prof. Ewe Hong Tat Universiti Tunku Abdul Rahman, “AI, 5G, and IoT: Technology Convergence and Human Capital
Malaysia Development”
Dr. Pannirselvam Kanagaratnam MIMOS Berhard, Malaysia “AI at the Edge”
(represented by Luke Jing Yuan)
Prof. Cor Claeys KU Leuven, Belgium “Material and Device Challenges for Future CMOS Technologies”
Dr. Khoh Soo Beng PMO Innovations Sdn. Bhd., Malaysia “Fuelling Innovation With Emerging Technology @4IR”
SSC Track
Dr. Wong Yan Chew Universiti Teknikal Malaysia Melaka “–32dBm Sensitivity High Efficiency Rectifier for Energy Harvesting”
Liew Vui Yong Intel Corporation, Malaysia “Advancement of Research in the Area of AI and 5G Opening Up New
Way of Living, New Opportunities and New Product”
Cheng Boon Seng Malaysia Robotics and Automation “Artificial Intelligence: The Chronology: Its Opportunities,
Society Challenges, and Risks”
Kalai Selvan Subramaniam Infinecs Systems Sdn. Bhd., Malaysia “Talent Recruitment for IR4 and Beyond”
Dr. Colin Chee Motorola Solutions, Malaysia “Voltage Versus Current Mode Direct Conversion Receiver”
Dr. Ong Sze Wei Intel Corporation, Malaysia “Developing the Innovation Capabilities for Engineering Advancements”
Mark Wong QRF Solutions Sdn. Bhd., Malaysia “Lowering the Risk of Analog IPs Through Design Automation
and Smart Integration”
MTT-S Track
Prof. Lim Eng Hock Universiti Tunku Abdul Rahman, “Recent Trends and Design Considerations of Passive UHF RFID Tags”
Malaysia
Prof. Widad Ismail Universiti Sains Malaysia “Convergence of Industrial Internet of Things Toward
Technology Humanization”
Dr. Wong Peng Wen FILPAL Pte. Ltd. “A Sustainable and Fast Approach to Filter Design for 5G Implementation”
Prof. Tharek A. Rahman Universiti Teknologi Malaysia “5G Mobile Communication: Evolution or Revolution”
Dr. Soh Ping Jack Universiti Malaysia Perlis “Wearable Antennas: Innovative Designs, Materials, and Features”
Yeoh Chun Yeow TM R&D Sdn. Bhd., Malaysia “5G Building Blocks for IoT Use Case”
Anwar Faizd Osman Rohde & Schwarz, Malaysia “The Study of Electromagnetic Compatibility Between 5G and
Fixed Satellite Services Operating in C-Band in Malaysia”
EDS Track
Prof. (Dr.) V.R. Singh National Physical Laboratory, India “Advanced Electronic Sensing Systems and Devices in Ubiquitous
Health Care”
Dr. P. Susthitha Menon Universiti Kebangsaan Malaysia “Angular Interrogation Sensing in Visible Wavelengths Using K-SPR”
Dr. John Tan Teng Hwang SilTerra, Malaysia “The Next Generation Sensors for IoT Applications”: MEMS on CMOS
Prof. Seiji Samukawa Tohoku University, Japan “Creating Green Nanostructures and Nanomaterials for Advanced
Energy Nanodevices”
Prof. Aimin Song University of Manchester, “Ultrafast Graphene Electronic Devices”
United Kingdom
Ir. Dr. Lim Kok Sing Universiti Malaya, Malaysia “Optical Fiber Devices and Instruments for Biomedical Applications”
Ravisangar Muniandy Semiconductor quality/reliability “New MOSFET Design, Test, Quality, and Reliability Challenges Arising
consultant, Malaysia From Latest Trends in Deep Nanometer Transistor and Voltage Scaling”

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 93

the Penang 2030 transformation plan,
which focuses on increasing quality of
life, upgrading the economy, empow-
ering the people, and investing in the
environment. According to Zakiyud-
din, the electrical and electronic (E&E)
industry is a key enabler of emerging
AI, 5G, and IoT technologies. Today,
the E&E industry remains one of
the most important pillars in Malaysia’s
export-driven economy. He also high-
lighted that, in 2018, Penang contrib-
uted close to 30% of Malaysia’s total
export and 79% of Malaysia’s total trade
surplus. This achievement would not

Dr. Wong Peng Wen (left) presenting a certificate of appreciation to

keynote speaker Prof. Tharek Abdul Rahman. An exhibition tour.

Participants (from left) include IMESS 2019 Chair Ir. Dr. Lee Choo
Yong, IEEE Penang Chapter Vice Chair Dr. Jagadheswaran R ­ ajendran, The finalists and judges of the design competition co-organized with
Chair Ir. Bernard Lim, and keynote speaker Prof. Ewe Hong Tat. FILPAL.

Ir. Bernard Lim (right) awarding a certificate of appreciation to key- IMESS 2019 Secretary Lance Lai (left) presenting a certificate of ap-
note speaker Prof. Cor Claeys. preciation to Prof. Seiji Samukawa.

94 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

have been possible except for the hard
work of all the stakeholders that have
built a thriving ecosystem in the state
by focusing on cutting-edge technolo-
gies and high-value jobs. He expressed
his hope that Penang’s presence in the
global scene of electronic manufacturing
services, research and development,
assembly, and testing of various elec-
tronic products will continue to drive
Malaysia’s economy and create skilled
job opportunities.
Following the opening ceremony,
IEEE Penang Chapter Chair Ir. Bernard
The presentation of a souvenir to Deputy Chief Minister 1 Zakiyuddin.
The USM student technical visit to the Penang Design Center of the Plexus Islandview plant, led by Ir. Dr. Khor Jeen Ghee and
Ms. Azwati Azmin.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 95
Lim, IMESS 2019 Chair Ir. Dr. Lee Choo
Yong, and Muhamed Ali Hajah Mydin
accompanied Zakiyuddin on an exhi-
bition tour and press conference.
Zakiyuddin was impressed with the
products and portfolios showcased
by exhibitors such as RFID tags, flex-
ible circuits, application-specified
IC design, and complete solutions for
Industry 4.0 implementation.
The second day of the symposium
kicked off with a keynote speech by
Prof. Cor Claeys of Katholieke Univer-
siteit Leuven (KU Leuven). The FILPAL
Today, the E&E
industry remains
one of the most
important pillars
in Malaysia’s
export-driven
economy.
design challenge demo and prize pre-
sentation were held during the tea
break and the closing of symposium,
respectively. The FILPAL design win-
ners were as follows:
■■ First Prize: Dr. Siti Zuraidah Ibra-
him and her Ph.D. student
■■ Second Prize: Ng Guan Shen
■■ Third Prize: David Bong.
In parallel, a 20-student delegation
from USM led by Ir. Dr. Khor Jeen Ghee
and Azwati Azmin paid a technical visit
to the Penang Design Center of the
Plexus Islandview plant. The sympo-
sium adjourned at 4:30 p.m. with clos-
ing remarks by Ir. Bernard Lim. Ir. Lim
extended gratitude to PSDC, sponsors,
and participants for their support in
making IMESS 2019 a successful event.
—Lee Choo Yong and
Lai Menn Tatt
2019 International Conference on Microelectronics

T
The 31st International Conference
on Microelectronics (MIEL 2019)
was held 16–18 September 2019 at the
Faculty of Electronic Engineering, Uni-
versity of Niš, Serbia. The meeting
was organized by the joint IEEE Elec-
tron Devices Society (EDS) and IEEE
Solid-State Circuits Society (SSCS) Ser-
bia and Montenegro Section in coop-
eration with the Serbian Academy of
Sciences and Arts Branch in Niš and
the Faculty of Electronic Engineer-
ing, University of Niš. Cosponsorship
was provided by the EDS; the Ser-
bian Ministry of Education, Science,
and Technological Development; the
Academy of Engineering Sciences
at Serbia; and the Serbian Society
for Electronics, Telecommunications,
Conference chair, Academician Ninoslav Stojadinovic´, addressing the audience during the
Computers, Automatic Control, and MIEL 2019 opening session.
Nuclear Engineering.

The attendees,
42 domestic and
40 foreign, came
from 20 different
countries.

The Mini-Colloquium on Nano and

Flexible Electronics (https://eds.ieee
.org/education/distinguished-lecturer
-mini-colloquia-program), held on 16
September, attracted interest from
both domestic and foreign partici-
pants. It was an excellent introduction
to the main technical program of MIEL Arokia Nathan (left) presents the 2018 IEEE EDS Region 8 Chapter of the Year award to
2019, which consisted of a tutorial on Danijel Dankovic, EDS/SSCS University of Niš SB Chapter chair.
power devices and modules, a plenary
session, and four regular sessions 49 posters) were presented. The con- tions, best paper awards were pre-
(two oral and two poster) on device ference proceedings (359 pages) are sented to the following:
physics, technology, and character- available in IEEE Xplore. ■■ D. Osipov (University of Bremen,

ization as well as circuit and system The keynote speakers were G. Germany) for an oral paper, “SAR
design and testing. The attendees, 42 Wachutka (Technical University of ADC Architecture With Fully Pas-
domestic and 40 foreign, came from Munich, Germany), S. Dimitrijev sive Noise Shaping”
20 different countries. A total of four (Griffith University, Nathan, Aus- ■■ Yu. I. Bogdanov (MEPhI, Moscow,

invited keynote papers and 74 regular
contributions (25 in oral sessions and
Digital Object Identifier 10.1109/MSSC.2019.2951675
Date of current version: 23 January 2020
tralia), Z. Prijić (University of Niš),
and Z. Stamenković (IHP, Frank-
furt, Germany).
Based on the evaluation of the
quality of the papers and presenta-
Russia) for a poster paper, “Nonpara-
metric Statistical Analysis of Radia-
tion Hardness Threshold Variation
in CMOS IC Wafer Lots Series With
the Aim of Process Monitoring”

96 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE

Participants of MIEL 2019.
Best paper awards were presented during the closing ceremony (from left): Y.M. Moskovs-
kaya (Russia), Ninoslav Stojadinovic´, L. Jürimägi (Estonia), and R. Długosz (Poland).
■■ L. Jürimägi (Tallinn University of
Technology, Estonia) for a student
paper, “Algorithm for Restructur-
ing of Structurally Synthesized
BDDs.”
In addition, the journal FACTA UNI-
VERSITATIS: Series Electronics and
Energetics awarded the best paper
award to “A Parallel Adaptive LMS
FIR Filter Realized in CMOS Technol-
ogy” by R. Długosz (UTP University
of Science and Technology, Bydgo-
szcz, Poland).
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 97
The IEEE EDS/SSCS University of
Niš Student Branch (SB) Chapter was
selected as the 2018 recipient of the
IEEE EDS Region 8 Chapter of the Year
Award. This award recognized the
quality and quantity of the activi-
ties and programs implemented by
the Region 8 Chapters during the 1
July 2017–30 June 2018 period. The
University of Niš SB Chapter chose
MIEL 2019 as the venue to receive its
plaque. During the opening session,
Arokia Nathan presented the award
In addition to
high-quality
presentations,
MIEL conferences
are generally
characterized
by a friendly
atmosphere
and the great
hospitality of
the local people.
to Danijel Dankovic, IEEE EDS/SSCS
University of Niš SB Chapter chair.
The social program of this year’s
conference included a conference
banquet and gala dinner as high-
lights. In addition to high-quality
presentations, MIEL conferences are
generally characterized by a friendly
atmosphere and the great hospital-
ity of the local people. This special
charm adds to the positive impres-
sions the participants bring back
from the conference and is one of
the reasons that a conference-goer
rarely attends MIEL just once.
—Ninoslav Stojadinović
and Danijel Danković

 IEEE N E WS
CEDA Currents
T
The following is a reprint from CEDA
Currents, September 2019 issue, a publi-
cation of the IEEE Council on Electronic
Design Automation (CEDA). Please
send contributions to Vasilis Pavli-
dis (v.pavlidis@ieee.com). This issue
reports on recent EDA activities and
welcomes upcoming events with
the support of CEDA.
EDAthon 2019 at the Chinese
University of Hong Kong
EDAthon 2019 was held successfully
on 26 July 2019 with 18 teams com-
ing from universities across main-
land China, Hong Kong, and Taiwan.
During the one-day competition, all
participants exercised their sophis-
ticated coding and analytical skills
to solve interesting EDA problems.
Three teams were awarded for their
outstanding performance as follows:
■■ Champion: Peng Zou and Zhipeng
Huang (supervised by Prof. Jianli
Chen), Fuzhou University, China
■■ Second place: Hongzheng Chen and
Jiawei Feng (supervised by Prof.
Minghua Shen), Sun Yat-sen Univer-
sity, China
■■ Third place: Mengke Ge and Jun-
peng Wang (supervised by Prof.
Song Chen), University of Science
and Technology of China.
EDAthon is one of the major events
organized by IEEE CEDA Hong Kong
and sponsored by IEEE CEDA. It is a
full-day programming contest (9:00
a.m. to 3:00 p.m. programming in
addition to a seminar from 3:30 to
4:30 p.m.) that features interesting
Digital Object Identifier 10.1109/MSSC.2019.2951676
Date of current version: 23 January 2020
98 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
and challenging topics in EDA. This
year, we also obtained industry spon-
sorship from Cadence, Inc.
Great Success for the First Workshop
on Machine Learning for CAD
The first ACM/IEEE Workshop on
Machine Learning for CAD was held
2–4 September 2020, in Canmore,
Alberta, Canada. Its location at the
entrance to Banff National Park main-
tained a long tradition of mountain
locations for technical meetings.
The workshop welcomed 52 partici-
pants including eight graduate stu-
dents. The program committee was
cochaired by Hussam Amrouch of
Karlsruhe Institute of Technology
and Bei Yu of the Chinese University
of Hong Kong. The event included 30
contributed presentations based on
submissions to the program commit-
tee as well as five invited talks, fea-
turing lectures from both industry
and academia and participants based
in Asia, Europe, and North America.
The program provided time for in-
depth discussion; topics included
appropriate types of machine-learn-
ing methods for various types of
CAD problems and challenges associ-
ated with training data.
CEDA Brazil Chapter Activities
During Chip in Sampa 2019
The last week of August was intense
for the CEDA Brazil Chapter. Three
activities were organized in con-
junction with the Chip in Sampa
2019 (http://www.psi.poli.usp.br/
chipinsampa/) event that took place
in Sao Paulo, Brazil. Chip in Sampa is
the fantasy name that was given to
this year’s edition of the most impor-
tant ensemble of symposia and work-
shops related to microelectronics and
embedded systems that takes place
each year in Brazil. Among those
scientific events is the Symposium
on Integrated Circuits and Systems
Design (SBCCI), which is technically
sponsored by CEDA. The total audi-
ence of Chip in Sampa reached almost
400 people, including ­r esearchers
from academia and industry, students,
and entrepreneurs.
The Chip in Sampa technical pro-
gram included the participation of
Dr. Sachin Sapatnekar, made possi-
ble thanks to the support of CEDA’s
­Distinguished Lecturer Program. On
27 August, Dr. Sapatnekar gave one of
the four SBCCI 2019 tutorials, “Reli-
ability, Error Resilience, and Approx-
imation in Integrated ­ Systems.” On
28 August, Dr. Sapatnekar gave one
of the three keynote talks of Chip in
Sampa. The talk, “Spintronics: From
Devices to Circuits to Systems” was
IEEE Embedded Systems Letters is open
for submissions. Visit ieee-ceda.org
.publication/esl-publication/author
-guidelines.
IEEE Design & Test is open for submis-
sions. Visit ieee-ceda.org/publication/
ieee-design-test-dt/paper-submission
-instructions.

Find us online at http://ieee-ceda.org.
attended by a large audience who
enthusiastically interacted by posing
several questions.
Besides the technical activities,
Chip in Sampa also hosted the CEDA
Brazil Chapter annual meeting, in
which the executive committee re­­
ported on activities of the previous
12 months and presented the activi-
ties planned for the next months. In
the sequel, some new actions were
proposed and discussed, aiming to
reach a larger number of students in
Brazil. Among those, the most rel-
evant is “CEDA Brazil Talks,” to be
organized in cooperation with the
Brazilian Computer Society.
The SMACD EDA
competition
was a thrilling
event in which
students competed
by presenting
their best ideas,
methodologies,
flows, and tools.
EDA Competition at SMACD 2019
An EDA competition sponsored by
IEEE CEDA, chaired by Engin Afacan
from Kocaeli University and Fabio
Passos from Instituto de Telecomu-
nicações, took place during the Inter-
national Conference on Synthesis,
Modeling, Analysis and Simulation
Methods and Applications to Circuit
Design (SMACD) in Lausanne, Swit-
zerland, 15–18 July 2019. The SMACD
EDA competition was a t h r illing
event in which students competed
by presenting their best ideas, meth-
odologies, flows, and tools aimed at
improving design automation for ICs
and systems.
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 99
The competition required the sub-
mission of a full paper and a presenta-
tion at the conference, together with a
live demonstration by the first author,
who had to be an M.Sc. or Ph.D. stu-
dent. The presenter also had to answer
questions from the judging committee,
which was formed by the following
experts from industry and academia:
David Atienza, EPFL (current president
of IEEE CEDA); Elena Blokhina, Uni-
versity College Dublin; Anton Klotz,
Cadence, Inc.; and Marco Cerchi, AMS.
This committee had to evaluate papers,
presentations, and tools according to
the complexity of the problem, level
of automation, applicability of the pro-
posal, integration with existing tools,
and methodologies and robustness of
the design solutions.
Fourteen proposals were submitted
and competed for the awards, which
included a monetary prize of US$1,000
for first place, provided by IEEE CEDA.
The awarded contributions and pre-
senters were “Mixed-Signal Hardware
Security Using MixLock: Demonstra-
tion in an Audio Application,” by Julian
Leonhard, Sorbonne Université (sec-
ond place), and “TiDeVa: A Toolbox for
the Automated and Robust Analysis of
Time-Dependent Variability at Transis-
tor Level,” by Pablo Saraza-Canflanca,
Instituto de Microelectronica de Sevilla
(first place).
Release of New Robust Design
Flow at ICCAD 2019
The IEEE CEDA Design Automation
Technical Committee (DATC) has devel-
oped an open reference design flow,
called DATC Robust Design Flow (RDF),
to facilitate research on flow-scale
methodology and cross-stage optimi-
zations. The latest RDF-2019 develop-
ment, scheduled to be released at the
IEEE/ACM International Conference
On Computer Aided Design, makes a
significant revision of the previously
reported RDF-2018 flow.
Leveraging recent academic tool
developments made in the OpenROAD
project (https://theopenroadproject
.org/), RDF-2019 adds previously miss-
ing steps, such as floorplanning, I/O
placement, power planning, and clock
tree synthesis.
IEEE COUNCIL ON ELECTRONIC
DESIGN AUTOMATION
President: David Atienza
President-Elect: Yao-Wen Chang
Past President: Shishpal Rawat
Secretary: Agnieszka Dubaj
VP Conferences: Luca Fanucci
VP Finance: Cristiana Bolchini
VP Publications: L. Miguel Silveira
VP Publicity: Vasilis Pavlidis
VP Standards: Dennis Brophy
VP Activities: Gi-Joon Nam
VP Awards: Subhasish Mitra
VP Initiatives: Jose Ayala
Council Operations Manager:
Jennifir McGillis
A number of horizontal extensions
to RDF are also achieved by incorpo-
rating additional tool options at the
static timing analysis, global place-
ment, gate sizing, and detailed rout-
ing stages of the flow.
RDF-2019 provides significantly
enhanced support of and interoper-
ability with industry-standard tools
and design formats such as LEF/
DEF, SPEF, Liberty, SDC, and so on. Be
sure to check out the official Github
repository of IEEE CEDA DATC at
https://github.com/jinwookjungs/
datc_robust_design_flow.
NOCS 2019
The International Symposium on Net-
works-on-Chip (NOCS) (17–18 October
2019) was a premier event dedicated to
interdisciplinary research on on-chip,
package-scale, chip-to-chip, and data-
center rack-scale communication
technology, architecture, design meth-
ods, applications, and systems. NOCS
brings together scientists and engineers
working on network-on-chip innova-
tions and applications from interre-
lated research communities, including
discrete optimization and algorithms,
computer architecture, networking, cir-
cuits and systems, packaging, embed-
ded systems, and design automation.
The conference program included
several keynotes, tutorials, and special
and regular paper sessions with par-
ticipants from industry and academia.

 SOC IET Y N E WS

Diversity Luncheon at ESSDERC/ESSCIRC

T
The IEEE Solid-State Circuits Society
(SSCS) and the Women in Circuits Com-
mittee hosted a diversity luncheon at
the 49th European Solid-State Device
Research Conference (ESSDERC)/45th
European Solid-State Circuits Confer-
ence (ESSCIRC) in Kraków, Poland.
Approximately 50 people attended
the event, which emphasized ways
to cultivate engineering confidence.
This focus was selected because it is
inclusive, appeals to a diverse audi- Kofi Makinwa sharing tips on mentorship.
ence, and can help engineers, no
matter their background or level of
expertise, to collectively become bet-
ter. Viola Schäffer from Texas Instru-
ments, Munich, Germany, moderated
the event.
The first guest speaker was Prof.
Kofi Makinwa from Delft University
of Technology, The Netherlands. He
highlighted the importance of mak-
ing sound decisions in one’s tech-
nical career and shared personal
experiences illustrating how mentor-
ing helped him to navigate oppor-
tunities. Makinwa provided best
practices, tips, and lessons learned The diversity luncheon speakers, conference chair, and moderator (from left): Téa Williams,
regarding becoming an impactful Viola Schäffer, Pawel Grybos, Andreia Cathelin, Kofi Makinwa, Maud Vinet, and Marian
mentor. He noted that a good men- Verhelst.
tor listens, encourages, helps to set
goals, points out the good and the tions but does not need to follow a vocacy. She emphasized that, even
bad, allows room for failure but mentor’s advice and that not every- though we all are at different stages
also helps to mitigate consequences, one can or wants to be mentored. of that journey, when it comes to
practices what he or she preaches, Téa Williams, the second guest increasing diversity in engineering
a nd is av a ila ble when ne eded. speaker, is a business unit man- and boosting confidence, we can
Makinwa emphasized that a mentee ager from Texas Instruments, Dal- all benefit from supporting each
should listen and be open to sugges- las, Texas. Her talk focused on the other by applying more openness
importance and benefits of sup- and empathy. Williams emphasized
Digital Object Identifier 10.1109/MSSC.2019.2951677 porting one another in the journey that this encourages competitive
Date of current version: 23 January 2020 of self-discovery, expertise, and ad­­ and robust solutions in technology

100 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE


Téa Williams discusses how we can all benefit from supporting each other by having more
openness and empathy.
Viola Schäffer (right) introduces Maud Vinet.
SSCS Young Professionals Connect
at ESSDERC/ESSCIRC 2019 in Kraków, Poland
A
Another Young Professional (YP) event
organized by the IEEE Solid-State
Circuits Society (SSCS) Poland Sec-
tion has concluded with success.
An international group of YPs and stu-
Digital Object Identifier 10.1109/MSSC.2019.2951678
Date of current version: 23 January 2020
IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 2 0 101
dents, as well as scientists and indus-
try representatives, met to make new
contacts and exchange knowledge.
This year’s gathering was organized
at the 49th European Solid-State Device
Research Conference (ESSDERC)/45th
European Solid-State Circuits Confer-
ence (ESSCIRC). The YP meeting took
and leads to a better pipeline of
future engineers.
The third guest speaker was Prof.
Maud Vinet from the French Alter-
native Energies and Atomic Energy
Commission Leti, Grenoble, France.
Her talk underlined the role of part-
nerships toward increasing skills
and rewards for successful proj-
ects. Vinet reflected on how people
she has encountered contributed to
her growth as a better engineer by
providing complementary perspec-
tives, challenging her views, and
supporting her.
The diversity luncheon was well
attended, and attendees were fully
engaged. Despite their diverse back-
grounds, all speakers expressed some
initial discomfort about presenting at
an event focused on diversity. How-
ever, they agreed that inclusion and
a wide variety of perspectives are
key for getting the best solutions and
results. Participants wanted to con-
tribute to the solution and motivate
others to do so as well. All agreed
that maintaining an open dialogue
and organizing similar events in the
future will help improve the engi-
neering environment for everyone.
—Viola Schäffer
place in Kraków, Poland, on 23 Septem-
ber 2019, the first day of the conference.
Close to 60 guests from Germany, Swe-
den, Poland, Austria, The Netherlands,
Italy, and other countries gathered for
the event. Attendees included not only
IEEE Members but also those who have
not discovered this opportunity yet.
It was a full house at the YP event at ESSDERC/ESSCIRC 2019.
YPs, students, and mentors discuss a wide range of topics including industry versus
academia and entrepreneurship.
The evening kicked off with Dr.
Konrad Markowski, YP Affinity Group
(AG) Chair of the IEEE Poland Section,
who provided some brief information
about the YP Poland Section and the
activities of this AG. Afterward, the
invited guests, Prof. Paweł Gryboś
(general chair of the conference) and
Prof. Barm Nauta (president of SSCS)
welcomed attendees.
In a brief lecture, Prof. Vojin Oklob-
dzija shared his knowledge about
102 W I N T E R 2 0 2 0 IEEE SOLID-STATE CIRCUITS MAGAZINE
machine-learning arithmetic for an
integrated circuit designer. Partici-
pants spent the next couple of hours
integrating and exchanging ideas.
However, not only science and tech-
nology were discussed that evening.
Some attendees met with old friends
while others made new acquain-
tances. All guests were free to enjoy
food and drinks, and, during regis-
tration, attendees could treat them-
selves to a gift, including a notepad,
earphones, or YP pin. Information on
how to join the IEEE was also distrib-
uted. At the end of the gathering, the
attendees were asked for their feed-
back via electronic survey.
This event organized by the SSCS
Poland Section YP AG was the third of
its kind. The previous two took place
in 2017 and 2018 during, respectively,
the 19th European Conference on
Power Electronics and Applications
and the 22nd International Micro-
wave and Radar Conference. For all
three events, more than 360 guests
from all over the world were given
the opportunity to extend their con-
tact networks, both professional and
personal, and learn more about the
IEEE. Such YP meetups are friendly
gatherings that enable and encour-
age communication among students,
scientists, and professionals; the cir-
cumstances of large scientific confer-
ences are certainly conducive to such
interaction. Organizing these events
allows the IEEE Poland Section YP AG
to seek opportunities and cooper-
ate with various IEEE Societies. The
meetings have been successful and
received positive ratings and reviews.
—Adrian Lipowski

 ILLUMINATE EDUCATE ENGAGE ENERGIZE
the possibilities of the next generation a wider audience innovation by
technology by using of innovators and in appreciating the celebrating
it to address global engineers value and importance technological
challenges of engineering and excellence
technology

The world’s most daunting challenges The IEEE Foundation is leading a special
require innovations in engineering, and campaign to raise awareness, create
IEEE is committed to finding the solutions. partnerships, and generate financial resources
needed to combat these global challenges.

Our goal is to raise $30 million by 2020.

DONATE NOW
ieeefoundation.org
 CON FERENCE CALEN DAR

SSCS-SPONSORED 2020 IEEE Asian Solid-State Circuits 2020 International Symposium on VLSI
CONFERENCES Conference (A-SSCC) Design, Automation, and Test (VLSI-DAT)
http://www.a-sscc2020.org/ http://expo.itri.org.tw/2020vlsidat
9–11 November 20–23 April
2020 Hiroshima, Japan Hsinchu, Taiwan

2020 IEEE International Solid-State 2020 IEEE Symposium on VLSI

Circuits Conference (ISSCC) SSCS TECHNICALLY Technology and Circuits
http://isscc.org/ COSPONSORED CONFERENCES http://www.vlsisymposium.org/
16–20 February 14–19 June
San Francisco, California, Honolulu, Hawaii, United States
United States 2020
2020 IEEE BiCMOS and Compound
2020 IEEE Custom Integrated Semiconductor Integrated Circuits and
2020 Design, Automation, and Test in
Circuits Conference (CICC) Technology Symposium (BCICTS)
Europe Conference and Exhibition (DATE)
http://www.ieee-cicc.org/ http://bcicts.org/
http://www.date-conference.com/
22–25 March 8–11 November
9–13 March
Boston, Massachusetts, United States Monterey, California,
Grenoble, France
United States
2020 IEEE Symposia on VLSI Circuits
http://www.vlsisymposium.org/ 2020 International Symposium on VLSI For more information on upcoming
16–18 June Technology, Systems, and Applications conferences, please visit: http://
Honolulu, Hawaii, United States (VLSI-TSA) sscs.ieee.org/conferences.
http://expo.itri.org.tw/2020VLSITSA
Digital Object Identifier 10.1109/MSSC.2019.2951679 20–23 April
Date of current version: 23 January 2020 Hsinchu, Taiwan 

Are You Moving?

Update your contact information so you don’t miss
an issue of this magazine!
Change your address
E-MAIL: address-change@ieee.org
PHONE: +1 800 678 4333 in the United States
or +1 732 981 0060 outside
the United States

If you require additional assistance

regarding your IEEE mailings,
visit the IEEE Support Center
at supportcenter.ieee.org.
IMAGE LICENSED BY INGRAM PUBLISHING

IEEE publication labels are printed six to eight weeks in advance

of the shipment date, so please allow sufficient time for your publications
to arrive at your new address.
 w
Best Ne
ourn al in
J 5
2 0 1
STM

Become a published
author in 4 to 6 weeks.
Get on the fast track to publication with the multidisciplinary open
access journal worthy of the IEEE.

IEEE journals are trusted, respected, and rank among the most
highly cited publications in the industry. IEEE Access is no exception;
the journal is included in Scopus, Web of Science, and has
an Impact Factor.
Published online only, IEEE Access is ideal for authors
who want to quickly announce recent developments,
methods, or new products to a global audience.

Publishing in IEEE Access allows you to:

• Submit multidisciplinary articles that do not fit
neatly in traditional journals
• Reach millions of global users through the
IEEE Xplore® digital library with free access to all
• Establish yourself as an industry pioneer by
contributing to trending, interdisciplinary topics
in one of the Special Sections
• Integrate multimedia and track usage and
citation data on each published article
• Connect with your readers through commenting
• Publish without a page limit for only $1,750
per article
17-PUB-013 3/17

Learn more at:

ieeeaccess.ieee.org
 What + If = IEEE

420,000+ members in 160 countries.

Embrace the largest, global, technical community.
People Driving Technological Innovation.

ieee.org/membership #IEEEmember

knowledge community professional development career advancement