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Y
A
OU
TPU
T
INP
UT
10
10
TR
UT
H
TA
BLE
A
Y=A
 If
INP
UT
is
high
then
the
OU
TPU
T is
high
.If
INP
UT
is
low
then
the
OU
TPU
T is
low.
BUFFER Gate
BUFFER Gate
TR
UT
H
TA
BLE
NAND Gate
NAND Gate
If at
least
one
ofth
 e
INP
UT
is
low
then
the
OU
TPU
T
 is
high
.
Y
B
A0
0
1
0
1
1
1
0
1
1
1
0
OU
TP
UT
INP
UTAB
Y=A.B
TR
UT
H
TA
BLE
NOR Gate
NOR Gate
 If
both
 of
the
INP
UTs
 are
low
then
the
OU
TPU
T is
high
.
Y
B
A0
0
1
0
1
0
1
0
0
1
1
0
OU
TP
UT
INP
UTAB
Y=A+B
 If
allth
 e
INP
UTs
aren
 ’t
equa
 l
then
the
OU
TPU
T is
high
.
Y
B
A0
0
0
0
1
1
1
0
1
1
1
0
OU
TP
TR
UT
H
TA
BLE
XOR Gate
XOR Gate
 AB
Y=A+B

UT
INP
UT
 If
allth
 e
INP
UTs
are
equa
l
then
the
OU
TPU
T is
high
.
Y
B
A0
0
1
0
1
0
1
0
0
1
1
1
OU
TP
TR
UT
H
TA
BLE
XNOR Gate
XNOR Gate
 AB
Y=A+B

UT
INP
UT
SUMMARY
 SUMMARY

Whe
re A
&B
are
INP
UTs
and
Y is
OU
TPU
T.
NO
T
Gate
Y=
A
BUF
FER
Gate
Y=
A
XN
OR
Gate
Y=
A+B
NO
R
Gate
Y=
A+B
OR
Gate
Y=
A+B
XO
R
Gate
Y=
A+B
NA
ND
Gate
Y=
A.B
AN
D
Gate
 Y=
A.B
Logic Gates Ppt
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language
Computer
Or
Basic
About
Assembly
Circuit
buffer
nand
XOR
nor
summery
logic gates
(more tags)

rasikalb

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Add a Comment

 
This document has made it onto the Rising list!
05 / 22 / 2010
 
dharampaljaat left a comment
nice for every one
02 / 26 / 2010
 
mrapurva left a comment
 thanks alot for this gr8 tutorial on GATES
02 / 11 / 2010
 
0000b1d47 left a comment
plz tell me abt circuits of gates and tell me how we can make circuits using truth table.
09 / 09 / 2009

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