INE Indie's Best Institute for IES, GATE & PSUs ‘Test Centres: Delhi, Hyderabad, Noida, Jaipur, Lucknow, Bhopal, Indore, Pune, Bhubaneswar, Kolkata, Patna ESE-2019: MAINS TEST SERIES UPSC ENGINEERING SERVICES EXAMINATION ELECTRICAL Test No. 1 ENGINEERING : Section A : Digital Electronics [All topics] Section B : Control Systems [All topics] Time Allowed : 3 hrs Maximum Marks: 300 Question Paper Specific Instructions Please read each of the following instructions carefully before attempting questions: + Answers must be written only in ENGLISH. + There are EIGHT questions divided in TWO sections. + Candidate has to attempt FIVE questions in all + Question no. 1 and 5 are compulsory and out of the remaining THREE are to be attempted choosing at least ONE question from each section. + The number of marks carried by a question/ partis indicated against it + Wherever ny assumptions are made for answering a question, they must be clearly indicated Diagrams/igures, wherever required, shall be drawn in the space provided for answering the question itself. + Unless otherwise mentioned, symbols and notations carry their usual standard meanings. Attempt of questions shall be counted in sequential order. Unless struck off, attempt of @ question shall be counted even if attempted partly. Any page or portion of the page left blank in the Question-cum-Answer Booklet must be clearly struck off DO NOT OPEN THIS BOOKLET UNTIL YOU ARE ASKED TO DO SO For any query write to us, at: info@madeeasy.in2 | ESE 2019: MAINS TEST SERIES MADE EASY Q1) (b) © @ Wise (i) If AB+CD =0, then prove that AB+C(A+D) = AB+BD+BD+ ACD. [6 marks] (ii) If AB+ AB =C, show that AC + AC =B. [6 marks] A company has 4 directors A, B, C and D and their corresponding percentage of shares in company are 30%, 40%, 15% and 15% respectively. The directors are eligible to vote according to their percentage of shares in the board of directors meeting 60% majority is required to pass any resolution. Design a combination circuit to indicate whether resolution is passed or not. [12 marks] Draw the block digrams of 4-bit serial-in parallel-out (SIPO) shift register and a 3-bit parallel-in parallel out (PIP) shift register. Give applications of shift registers. [12 marks] Consider the R-2R, 4-bit converter shown below, Assume the feedback resistance R,of the op-amp is variable, the resistance R = 5 kQ and V, = 10 V. Determine the value of R, that should be connected to achieve the following output conditions. () The value of 1 LSB at the output is 1 V, Gi) An analog output of 8 V for a binary input of 1000 (ii) The actual maximum output voltage of 10 V. [12 marks] wwwmadeeasy.inMADE EASY Test No: 1 ELECTRICAL ENGINEERING | 3 (©) Perform the following mathematical operations and give the answers in decimal format (@ (10.011), « (110.1), i) (11001), + (101), Gi) (-88),9 + 8), Gv) (111000),,., + (100011) - (111001), gray gray [12 marks] Q2 (a) Consider the sequential circuit given below: Ish B@HI4h BHiq~k BHiqh & CLK: IK) 14K G) 14% OB] 14K LSB. MSB. (Find the count sequence of the circuit given above. Assume initial condition of flip-flop to be zero. i) If clock frequency is 160 kHz. Find the frequencies of Q, and Q,. ketch the waveforms of clock, Qy Q,, Q, and Q;. [8 +4 +8 marks] (b) With a neat block diagram, explain the operation of counter type ADC. Give advantages and disadvantages of counter type ADC. [20 marks] (©) Each of the following arithmetic operation is correct in atleast one number system. Determine the possible bases in each operation 142 () 3441 + 4235 = 7676 fi) “> =16 (ii) 23 + 44 + 14 + 32 = 223 (iv) 21 * 16 = 366 302 @) 3p 7221 (vi) V51=6 [20 marks] Q3 (a) Using 4-bit parallel adder design a 4-bit BCD adder. [20 marks] (b) Design a synchronous counter with the following sequence using D-flip flops [001 O11 > 100 > 111 > 110» 101 > 010 ~» 0005 [20 marks] wwwmadeeasy.in4 | ESE 2019: MAINS TEST SERIES MADE EASY (© @ Consider the Karnaugh map given below: ofa) [=p OL Ty) x}. Determine simplified expression and implement the simplified expression with minimum number of two input NOR-gates. [12 marks] (ii) Consider the Boolean expression F(A, B, C, D) = ABD + ACD + ABD + ABC. If input combinations ABCD = 0101, 1001, 1011 are don’t cares, then determine the simplified expression of F? [8 marks] Q4@) (i) Explain with necessary diagram the operation of a full subtractor? [12 marks] (ii) In view of important parameters, give the comparison between serial binary adder and parallel binary adder. [8 marks] (6) (@ The truth table for XY flip flop is shown below. Design this flip flop using T-flip flops and additional logic gates. ‘Truth table XY | Quid 0/0] Q oj1] Q, ajo} o afaj4 [12 marks] (i) Realize J-K flip flop using D-flip flop. [8 marks] wwwmadeeasy.inMADE EASY Test No: 1 ELECTRICAL ENGINEERING | 5 Q4 (©) (i) Design a asynchronous counter using positive edge triggered T-flip flop that has a repeated sequence of six states as given in the table below. Count sequence: @ Q OQ] o 0 0 111 11 £40 1 o 1 1 0 0 oO 1ii1 [12 marks] (ii) What is the need for A/D converter? What is meant by the resolution of a D/A converter? [8 marks] ion B : Control fu Q5 (a) Simplify the given below block diagram by block reduction technique and obtain closed loop transfer function C(s)/R(s) for given system? Hy -O QE re GLa a Hy Hy [12 marks] (&) A control system with open loop transfer function is represented by K GH) = Tapers: Determine the range of value of K for which value of gain margin (GM) > 4 and position error constant is K, > 2 when unit step input is applied. [12 marks] (© Acontrol system has open loop transfer function, 1 GOH = Graerh 42? o. What is the value of |G(s)H(s)| at @ = 0°? Draw the Nyquist plot and comment on the stability of the system. [12 marks] ot MADE EASY wwwmadeeasy.in6 | ESE 2019: MAINS TEST SERIES MADE EASY (@) A unity feedback system whose forward path transfer function is given by 64 s(+1) G@) = What will be the value of steady state error due to unit step input and also the percentage overshoot resulting when unit step input is applied? [12 marks] 1 1 (©) Acontrol system has transfer function G(s) = (: +7 } | (: +7 } Ifa sinusoidal input 1 D x(f) = X sin ot is given to the system and value of constant T, is greater than value of Ty then prove that the system corresponds to a lead network. [12 marks] Q6 (a) A control system is represented by block diagram given below. Find the value of constants ‘A’ and ‘B’ of closed loop system such that maximum overshoot in unit step response is 30% and the peak time is 4 sec. (Take J = 1 kg-m?) A ce) [20 marks] (b) A state space representation of control system is given by, 3 41 1 me A hy 2 alle} m1 =[1 0 1-0 of Calculate the transfer function of the system. [15 marks] (9 A unity feedback control system has open loop transfer function, K Calculate the value of K for which the gain margin is 40 dB. G(s) = [15 marks] wwwmadeeasy.inMADE EASY Test No: 1 ELECTRICAL ENGINEERING | 7 (@) A unity feedback closed loop system is formed with plant transfer function, 124 s(s7 + 2s° + 165° + 24s* + 4855 + 72s? + 96s +112) Comment on the stability of the system using Routh Hurwitz criteria. How many roots lie on right half of s-plane? G@)= [10 marks] Q7 (a) Ade motor (separately excited) is controlled by armature voltage control method as shown by the setup below. J,, and f,, are moment of inertia of motor and coefficient of friction of motor. Assuming input variable V, and output variable ‘®,,’ find the transfer function of system shown below assuming motor torque constant, K; and back emf constant K,, What is the type of the derived system? i, (constant) [20 marks] (b) A negative unity feedback control system is provided with compensator in cascade with system, for system to be stable. The transfer function of plant and compensator s+ are respectively = and S40 G+2)6+4) sel” Calculate the range of value of ‘a’ for system to be stable and also represent complete system in form of block diagram? At critical stability condition, what will be the nature of compensator? [15 marks] (©) Consider the bode magnitude plot shown below. Using data given in plot, derive the transfer function of system. M, -20 dB /dec -10 4B 40 aB/dee 4/9 30 a8 -20 dB/dec [10 marks] ecovot MADE EASY wwwmadeeasy.in8 | ESE 2019: MAINS TEST SERIES MADE EASY (@) Derive a time response of a first order control system subjected to unit ramp input function when first order control system is given by, T)= sT+1 Also determine relation of error for all ¢ and steady state error. [15 marks] Q8 (a) Draw polar plots of given below open loop transfer function: 1 Kes i) G(s)H(s) = fi) G(s)H(s) = @ G)H(s) Pai Gi) G(s)H(s) ‘ [10 + 10 marks] () @) Define state transition matrix. What is the significance of state transition matrix? i) For the state transition matrix, 6(t) = et, show that $"1(H) = o(-2). (ii) Obtain state transition matrix of the given below state space model. EE OE} (6). Sketch the root locus plot of closed loop system having open loop transfer function, K +4)(s+8) (Find the location of centroid, angle of asymptotes, breakaway point and indicate on root locus. [6+ 6 +8 marks] GOH) ii) For marginal stability of given system find the value of K. fii) Find the coordinates of points at which root locus intersects, the ima; axis. Ps ginary [6+ 6 +8 marks] 2000 wwwmadeeasy.in