4.

0 VLSI Clocking, Protection and Interconnect 06

4.1 CMOS clocking styles, pipelined systems, Clock generation,
stabilization and distribution
4.2 ESD protection, Input circuits, Output circuits, power distribution
scheme
4.3 Interconnect delay model, interconnect scaling and crosstalk
Most VLSI chips receive clock signals from a common clock source and then in turn must
generate internal clock signals.
On-Chip Clock Generation and Distribution
Clock signals are the heartbeats of digital systems. Hence, the stability of clock signals is
highly important. Ideally, clock signals should have minimum rise and fall times, .specified
duty cycles, and zero skew. In reality, clock signals have nonzero skews and noticeable rise
and fall times; duty cycles can also vary. In fact, as much as 10% of a machine cycle time is
expended to allow realistic clock skews in large computer systems. The problem is no less
serious in VLSI chip design. A simple technique for on-chip generation of a primary clock
signal would be to use a ring oscillator as shown in Fig. below. Such a clock circuit has been
used in low-end microprocessor chips.
However, the generated clock signal can be
quite process-dependent and unstable.
As a result, separate clock chips which use
crystal oscillators have been used for high
performance VLSI chip families. Figure
13.20 shows the circuit schematic of a Pierce
crystal oscillator with good frequency
stability. This circuit is a near series-resonant
circuit in which the crystal sees a low load
impedance across its terminals.

Series resonance exists in the crystal but its internal series resistance largely the determines
the oscillation frequency. In its equivalent circuit model, the crystal can be represented as a
series RLC circuit; thus, the higher the series resistance, the lower the oscillation frequency.
The external load at the terminals of the crystal also has a considerable effect on the
frequency and the frequency stability. The inverter across the crystal provides the necessary
voltage differential, and the external inverter provides the amplification to drive clock loads.
Usually a VLSI chip receives one or more primary clock signals from an external clock chip
and, in turn, generates necessary derivatives for its internal use. It is often necessary to use
two non-overlapping clock signals. The logical product of such two clock signals should be
zero at all times. Figure 13.21 shows a simple circuit that generates CK- 1 and CK-2 from the
original clock signal CK. Figure 13.22 shows a clock decoder circuit that takes in the primary
clock signals and generates four phase signals.
Since clock signals are required almost uniformly over the chip area, it is desirable that all
clock signals are distributed with a uniform delay. An ideal distribution network would be the
H-tree structure shown in Fig. 13.23. In such a structure, the distances from the center to all
branch points are the same and hence, the signal delays would be the same. However, this
structure is difficult to implement in practice due to routing constraints and different fanout
requirements. A more practical approach for clock-signal distribution is to route main clock
signals to macro blocks and use local clock decoders to carefully balance the delays under
different loading conditions.
The reduction of clock skews, which are
caused by the differences in clock arrival
times and changes in clock waveforms due
to variations in load conditions, is a major
concern in high-speed VLSI design. In
addition to uniform clock distribution (H-
tree) networks and local skew balancing, a
number of new computer-aided design
techniques have been developed to
automatically generate the layout of an
optimum clock distribution network with
zero skew.
If the package is considered a protection layer of the silicon chip, then the IO frame
containing input and output circuits and clock circuits can be considered a second protection
layer. Any external hazards such as electrostatic discharge (ESD) and noises should be
filtered out before propagating to the internal circuits for their protection. Also, some chips
have to communicate with Transistor- Transistor Logic (TTL) or Emitter-Coupled Logic
(ECL) bipolar chips, and in such cases, the input or output circuit must provide proper level
shifting so that the transmitted signal contents can be correctly received or sent by the CMOS
chip.
ESD Protection
Electrostatic discharge is one of the most prevalent causes for chip failures in both chip
manufacturing and field operation. ESD can occur when the charges stored in machines or
the human body are discharged to the chip on contact or by static induction. Figure below
shows different models for ESD testing, namely the human body model (HBM), the machine
model (MM), and the charged device model (CDM).
A human walking across synthetic carpet in 80% relative humidity can potentially induce 1.5
kV of static voltage stress. In the HBM.MIL-STD-883C, Method 3015,1988) shown in Fig.
(a), a touch of a charged person's finger is simulated by discharging a 100-pF capacitor
through a 1.5-kQ resistor. It is important that some protection network be designed into the
I/O circuits of the chip so that the ESD effect can be filtered out before its propagation to the
internal logic circuit. Effective protection networks can withstand as high as 8-kV HBM ESD
stress. In addition to human handling, contact with other machines can also cause ESD stress.
Since body resistance is absent, the stress can be more severe with higher current levels. The
schematic diagram of the machine model is shown in Fig. (b). The third model is the charged
device model shown in Fig.(c). It is intended to model the discharge of the packaged
integrated circuits. The charge can be accumulated either during the chip assembly process or
in the shipping tubes. The CDM ESD testers electrically charge the device under test (DUT)
and then discharge it to ground, thus probing the high short-duration current pulse to DUT.
Simplified lumped-circuit element models of both HBM and MM ESD testers are shown in
Fig. below along with corresponding parameter values.
The protection network (PN) usually
consists of a diffused resistor-diode
structure as shown in Fig. 13.3 along with
its equivalent circuit model. The input
resistance is normally between 1 and 3 kQ.
This resistance in conjunction with the
capacitances in diffusion, diodes, and gate
capacitance in input transistors integrates
and clamps the voltage to a safe level. The
RC time constant, however, should be
small enough not to increase the circuit
delay significantly.
In essence, the diodes clamp the signal level within a certain voltage range, in order to
minimize the impact of ESD. In order not to permanently, damage the diode structure, the
current through the diode should be limited to less than several tens of milliamperes. Past
attempts to use polysilicon series resistors failed due to dielectric breakdown under high
electric fields. The use of additional thick-oxide nMOS transistors as shown in Fig. 13.4 has
proven to be very effective and yielded protection in excess of 3 kV in the HBM-ESD test. In
this circuit, MI is a thick-oxide punch-through device, M2 is a thick-oxide nMOS transistor,
and M3 is a thin-oxide nMOS transistor operating in saturation mode. For positive input
transients, Ml and M2 have threshold values of 20 to 30 V.
Input Circuits
A simple input circuit consisting of a transmission gate activated by an enable (E) signal
and its complement is shown in Fig. below

The incoming signal A is fed into the transmission gate through the protection network (PN)
from the bonding pad of the chip. The enable signal is generated on-chip and controls the
gating of the input signal as
* X=A, whenE=0
* X = high-impedance state, otherwise
Any unused chip input terminals should be tied to VDD or Vss using pull-up or pull-down
resistors externally. Some input pad circuit modules have a built-in internal pull-up or pull-
down resistor or active load (normally-on transistor) with a resistance of 200 k to 1M.
Figure shows an inverting input circuit
consisting of the protection network and a
CMOS inverter Typical values for VIL and
VIH are 0.3VDD and 0.7 VDD,
respectively for about 30% noise margins.
This basic input circuit can be designed to
receive TTL signals for CMOS logic
circuits by adjusting the ratio of the
channel widths in pMOS and nMOS
transistors in the inverter. In TTL, the
worst-case output signal levels are
 VOL= 0.8 V
 .VOH=2.0V
Therefore, input voltages less than or equal to 0.8 V should be interpreted low and input
voltages greater than or equal to 2.0 V should be interpreted high. After the input protection
circuit, the incoming signals have to be level-shifted to a desirable level, depending on their
voltage levels. For instance, if the incoming signal is from a TTL driver, then its low voltage
can be as high as 0.8 V and its high output voltage can be as low as 2.0 V. Therefore a careful
level shifting has to be done to translate such logic levels to corresponding MOS gate voltage
levels. The level shifting between a TTL driver and a CMOS gate can be achieved by
properly designing the ratio between pMOS and nMOS transistors of the receiving CMOS
inverter gate. A practical method is to adjust the transistor ratio in the inverter gate such that
the saturation voltage at which both transistors operate in saturation region is set at the
midpoint between 0.8 V and 2.0 V.
Figure below shows an input pad circuit with a Schmitt trigger circuit and a 70-ka pull-down
resistor. This circuit provides a negative-going logic threshold voltage of 1 V and a positive-
going logic threshold voltage of 4 V, for a 5-V power supply.
Output Circuits and L(dI/dt) Noise
The output circuits of VLSI chips are designed to be tristable as shown in Fig. 13.12. The
circuit implementation 13.12(b) requires more transistors (12 transistors) than the circuit
implementation 13.12(c), in which only four transistors are required if polarity is ignored.
In terms of silicon area, however, the implementation in 13.12(b) may require less than
the circuit in 13.12(c) since the last-stage transistors have to be sized large to provide sufficient current sinking
and sourcing capability and also to reduce delay times.
Unfortunately, such a requirement demands a high rate of change in the current di/dt and
can cause significant on-chip noise problems due to the L(di/dt) drop across the bonding
wire connecting the output pad to the package.