module full_adder(s,c,cin,i1,i2) ;

input i1,i2,cin;
output s,c;
assign s = i1^i2^cin;
assign c = (cin &(i1^i2))|(i1&i2);
endmodule
module tb_fa();
reg i1,i2,cin;
wire s,c;
full_adder f1(s,c,cin,i1,i2) ;
initial
begin
i1=0;
i2 =0;
cin=0;
i1 =1;
i2=0;
cin=0;
i1 =0;
i2=1;
cin =0;
i1 =1;
i2=1;
cin =0;
i1=0;
i2 =0;
cin=1;
#100
i1 =1;
i2=0;
cin=1;
i1 =0;
i2=1;
cin =1;
i1 =1;
i2=1;
cin =1;
end
endmodule