Interview PDF

CLIENT INTERVIEW Pozibility
Technologies
QUESTIONS
The document contains interview questions based on experience shared by
candidates.
Pozibility Technologies
Table of Contents
Mediatek interview questions - 1 2
MediaTek Interview Questions -2 4
Mediatek face to face interview questions -1 7
Synapse Interview Questions - 1 15
Aricent Interview Questions - 1 19
Aricent interview Questions - 2 20
L&T Interview Questions 22
Qualcomm interview questions - 1 23
Qualcomm interview Questions -2 26
Qualcomm Interview Questions -3 28
Extra Questions 30
Mediatek interview questions - 1

1) Issues faced in each stages
A. FloorPlan - While placing macros.
Macro count was in hundreds. Non uniform sized macros were there and I had to reserve
enough routing space around macros. I had to check the macro alignment, its orientation and
avoid the crisscross placement. Did multiple iterations to avoid any notches.
For power plan different team was there.
B. Placement
a. Placed end cap cells, tap cells, IO buffers and then placed, standard cells.
Then used command place_opt to optimize the placement.
b. I got congestion due to Pin density and Cell density.
c. Pin Density – When pins for standard cells were more in a certain part due to use of AOI
and OAI. Used partial blockage and keep-out margin to avoid congestion of pin density.
d. Cell density – When certain standard cells were placed very closely. Used keep out
margin to reduce congestion due to cell density.
C. CTS
a. Timing Issues – setup and hold violation
b. Meeting skew and latency targets
c. Exception pin declaration was not proper
D. Routing
a. After routing I faced congestion which I fixed by detouring the nets.
b. Cross related issues
c. DRC issues
d. Timing issues
e. Antenna violation after DFM (Base fill)
2) Types of congestions.
Congestion occurs when numbers of routing tracks available for routing are less than required
routing tracks.
Types of Congestions:
a) Congestion between macros
a. First check fly lines, check net connections, place macros connecting each other
closer
b. If there is more connection from macro to macro, place those macros nearer to
each other preferably nearer to core boundaries
c. If input pin is connected to macro, better to place nearer to that pin or pad
d. If macros have more connections to std cells, spread the macros and add soft
blockage if not added already
b) Congestions in core
a. Local congestion - Check for pin and cell density. Spread cells and insert partial
blockage if necessary
Pin density is due to more pins in particular area. For example, OAI, AOI has more
pins and it causes pin density
b. Global congestion - Check for cells causing congestion. Do the cell padding/keep out
margin
c. Module splitting - Tool splits the modules sometimes, causing the congestion by
using routing resources
3) What will you do if there is a timing violation in placement stage?

Analyze the timing with ideal clock and try to fix the setup. We will try fixing the hold after CTS.
4) Types of skew
Global skew - between any 2 flops driven by same clock source
Local skew - between any 2 adjacent flops
5) In which corner you fixed setup?

The setup was checked for high temperature, low voltage and slow process (worst case).
6) Have you worked on low power? If yes...explain

In low power, we used upf flow. There were two power domains. Contents of upf were,
a. Create Power domain: vddOn, vddSw, vddHv
b. Create Power Supply Rails
c. Create PST: Power state table - relation between power domains (which power domain
is ON in which state)
d. Isolation strategy
e. Level Shifter strategy
Issues faced in low power stage. There was one MVRC tool. It take two inputs, netlist and upf. It
compares and verifies that upf is implemented in netlist properly. One isolation cell was
connected to vddsw while it should have been connected to vddOn. Tool was recommending to
connect one more isolation cell while there was already one existing isolation cell. The issue was
with upf file which was not written correctly.
7) What will you do if 200 PS violation in placement stage?
8) Have u fixed setup or hold? If yes, then how?

Setup fixing techniques:
a. Insert buffers with faster slew in data path.
b. Remove buffers from data path
c. Replace one buffer with 2 inverters in data path
d. Upsize the standard cell
e. Use LVT/RVT/SVT instead of HVT
f. Adjust cell position in layout
Hold fixing techniques:
a. Decreasing the standard cell size

b. Inserting the delay cells
9) If skew is less then will it affect setup or hold... and how?

Skew if positive in quantity, then capture path becomes longer, hence good for setup. Negative
skew is good for hold.
MediaTek Interview Questions -2

1. What are sanity checks?
a) Netlist Checks
i. Outputs are connected to vdd or gnd
ii. Inputs are floating
iii. Is there any feedback loop in combinational block
iv. Are there any multiple driver nets
v. Is there any empty module (LEF/LIB not available for module)
vi. Is there any tri-state buffers
vii. Are there any black-boxes present
b) SDC Checks
i. IO Delay constraints are defined or not
ii. There is no clock defined for clock port
iii. Multiple clocks are reaching the flop
iv. There is no input transition or input driver defined for a port
v. There is no load defined for output port
c) Linking related checks
i. LEF Views
1. Cells not defined in library
2. Cells with missing dimension, geometry, direction
ii. LIB Views
1. Timing related information is missing
iii. PG Checks
1. Reports if PG nets are not defined, or not connected to PG terminals
iv. Tie high, Tie low checks
1. Reports if tie high, tie low terminals connected to other nets.
d) Netlist vs SDC Checks
i. For this we do the analysis using ZWLM (zero wire load model)
ii. Use command set zero_interconnect_delay_mode = true to do this
2. How will you get to know that input of any gates is connected to power or gnd pin is valid or
not?
While doing the sanity check, we will come to know this.
Or, in power planning, we run the command – check_design, this also reports if input is
connected to power or ground pin.
3. How will you solve if flop is connected to multiple clocks?

Check_design command will report if two clocks are driving same flop. We can use mux or
and gate or may ask the higher team.
4. How will you start FP?

The team will give us aspect ratio, and utilization. Using that we create core and die. We will
place the pins. Then we start placing macros based on data flow diagram. After placing macros
we do the power planning. We will check legality of floor-plan then.
5. Have you worked on upf? What are special cells?

Yes, special cells in upf are power management cells, like power switch, retention cells, isolation
cells, level shifter, always on cells.
6. Will standard cell power rails will be overlapped on ip?

No, IP will have separate meshes.
7. How you will check that power pin of macros is connected to power pin or not.
Check_mv_design, verify_pg_nets (ICC Commands)
8. What is command to check whether the libs are properly loaded or not?
Check_library
9. What was the utilization of your block from FP to routing?

Fp – 65, routing – 82
10. In placement what issues you have faced?

In placement, I faced issues related to congestion, timing and module splitting. In congestion, I
faced issues because of cell density, pin density and in timing the issues were related to setup
timing.
11. How you solved the congestion? Give the commands?

Select the cell = get_selection
Give keepout margin = set_keepout_margin [get_selection] –outer {1 1 1 1}
Legalize placement = legalize_placement
12. For create bounds how much utilization you have provided. Types of bounds?
40-50% utilization. Soft bound, Hard bound
13. How you have fixed DRC?

In IC Validator, we fixed DRC for metal layers
14. Extract and compare errors in LVS?
15. GPA and PBA difference?

path based - time consuming and accurate
graph based - more pessimistic and less time consuming (Considers worst slew)
16. What is NDR?

Non default rules are defined in CTS/routing stage to avoid congestion.
Command to define NDR in ICC is
define_routing_rule rule_name -default_reference_rule
-widths {m1 0.8 m4 0.9} -spacings {m1 1.0 m4 1.0}
17. What is skew? In CTS report you will see local or global skew reports?
Skew is difference between latencies. There are two types of skews, local and global skews.
Local skew is skew between two adjacent flip flops, while global skew is between any two flip
flops across the block.
report_clock_tree -local_skew
report_clock_timing -type skew
18. What is latency?

Latency is the delay of clock signal to reach from clock start point to clock end point. To set clock
latency, we use the command:
set_clock_latency
19. What analysis you will do, if you are getting shorts?
In intel, we used rip_n_route.tcl to fix metal shorts violation.
20. Tool will try to upsize and add buffer during optimization. Why we are using command size-
cell?
Size cell is used to resizing, vt ein eco stage to manually change the drive strength.
21. In CTS which topology you have used?

We used H-Tree in our block.
22. Combination of what is better? Inverter buffer or only inverter or only buffers?
It depends on situation but mostly it is inverter and buffer combination.
23. Why clock buffer is used instead of normal buffer in CTS?

Clock buffers have symmetrical rise and fall time.
24. Why they will have equal rise and fall time. What will happen if I use normal buffers?
They have equal rise/fall time because of their W/L ratio in PMOS vs NMOS. If we use, normal
buffers, we will encounter different rise/fall time which could lead to min pulse width violation
too.
Mediatek face to face interview questions -1

1) Complexity of recent project
2) How do you say a floorplan is good?

We say a floorplan is good after verifying following checkpoints:
i) All macros are placed to the edge of core and there should not be any overlapping macros.
ii) There should not be any notches in design.
iii) All pins must be aligned to the center of track.
iv) All macros are place.
3) Is utilization depends on floor plan after place opt ?
4) How do you fix congestion and timing ?

Congestion occurs when numbers of routing tracks available for routing are less than required
routing tracks.
Types of Congestions:
a. Congestion between macros
i. First check fly lines, check net connections, place macros connecting each other
closer
ii. If there is more connection from macro to macro, place those macros nearer to
each other preferably nearer to core boundaries
iii. If input pin is connected to macro, better to place nearer to that pin or pad
iv. If macros have more connections to std cells, spread the macros and add soft
blockage if not added already
b. Congestions in core
i. Local congestion - Check for pin and cell density. Spread cells and insert partial
blockage if necessary
Pin density is due to more pins in particular area. For example, OAI, AOI has
more pins and it causes pin density
ii. Global congestion - Check for cells causing congestion. Do the cell padding/keep
out margin
iii. Module splitting - Tool splits the modules sometimes, causing the congestion by
using routing resources
5) How do you find channel between macros ?

Channel length between macros = (pin pitch*no of pins) + space between pins
Number of horizontal/vertical metal layers
6) Did u have any feed through pins ?

No there weren't any feed through pins.
7) What does spec file contains ?

Spec file contains, target skew, target latency, NDRs, and information related to which buffers to
use for CTS.
8) For leaf cell and non-leaf cells to which cells you apply NDR ?
We apply NDR to leaf cells.
9) What is use of ndr in spec file ?

NDR is used to specify what metal width and spacing to use in CTS or routing stage. With use of
define_routing_rule command, ndr can be specified.
10) Different flavors of lvt devices and hvt cells and which lvt is used for setup and which lvt cell
for low power?
11) How did you fix DRC w.r.t. double patterning, which metal layers had double and triple
pattern ?
12) How did you fix LVS from Calibre ? #Calibre
13) Inputs for Star rc and inputs for pt shell ?

Star RC - .v, DEF, Tech file, Output - SPEF file
how Spice netlist is generated ?
14) Explain routing which net will u route first ?

Firstly, routing will be done for power domains, then for clock domains and last for data signals.

1) How you will analyze the congestion?
Report_congestion, it will report grc overflow. For other congestion, we give keep-out margin or
partial blockage. To analyze congestion, you can use, report_congestion -routing_stage
2) Causes of congestion?
Congestion could be caused due to mainly due to cell density, pin density or module splitting.
3) Contents of spec-file?
Spec file is input to CTS Stage. It mainly contains, target skew and target latency (insertion delay).
It also contains NDRs and other details like which buffers to use for building the CTS.
4) CTS methodology and commands

Following are commands for CTS:
Cts_opt (synopsis)
Cco_opt (cadence)
In CTS, the aim is to reduce the skew and insertion delay and balance the clock tree. For this, the
tool follows one algorithm, (it could be H-Tree/Pie/Fishbone etc.) and constructs the clock tree and
balances it. The tool will also place clock buffers to ensure signal quality.
For common problems related to clock tree, we can check it using the command, check_clock_tree.
5) Explain routing in detail?

Routing is the process of creating physical connections based on logical connectivity. Signal pins are
connected by routing metal interconnects. Routed metal paths must meet timing, clock skew, max
trans/cap requirements and also physical DRC requirements.
There are four steps of routing operations: Global routing, track assignment, detailed routing.
Global route: It identifies nets with shortest path and assigns them to specific metal layers and
global routing cells. It avoids congestion, detours and blockages. Uses steiner tree or maze
algorithm.
Track assignment: It takes the global routed layout, assigns track to all nets. It performs DRC
unaware assignment.
Detailed routing: Performs DRC aware routing. It is the final stage of routing.
6) What are the inputs for star rc ?

.nxtgrd (it contains where to pick the delays from, nothing but mapping file), tluplus
Routed db (DEF/GDS)
7) How will you add end cap n tap cells

Following are the commands:
add_end_cap
add_tap_cell_array
8) What is the use of filler cells and purposes of metal filling?

filler cells are added to the core area to avoid base drc errors. Similarly metal filling is also done to
avoid metal drc error. Base and metal drc guideline are provided by foundry to add minimum certain
percentage of material for increasing yield.
9) Explain clock gating?

Clock gating is the method of gating clock signal so that we can save clock power by turning off te
gate in case a certain gated portion of design is not in function.
10) What happens if u put dummy metal in combo path and will it affect other metal?
Dummy metal is added to increase the yield but it may cause shorts, drc violation, if it is cross talk
with data metal then causes timing effect in data path.
11) When you will do clock push?

Clock push is done in the event of utilising the useful skew. We insert delay cells in clock path to
push the clock and use the skew to meet the slack.
12) How will you analyze the report?
13) ECO timing fixing commands?

fix_eco_timing -type setup
fix_eco_drc
write_eco_changes filename
14) How will you fix LVS and DRC?

LVS is layout vs. schematic check. It’s Verilog netlist vs layout netlist check. Typical example of LVS is
open nets, short nets.
15) What are fixes of setup apart from buffering, upsize, VT cell swapping?
Useful skew, detour net, cloning.
16) Explain all commands in each stage in ICC.

Stage wise commands in ICC:
a) Sanity Checks:
i. Netlist Checks – Check_design/ Check_mv_design (Checks the current design for
consistency).
ii. Sanity Checks – Check_timing (Checks for possible timing problems in the current
design).
iii. Library Checks – Check_library (Performs consistency checks between logic and
physical libraries, across logic libraries, and within physical libraries).
iv. Netlist vs SDC – Report_timing (Displays timing information about design).
b) Floorplan Stage:
i. Source your ioports.tcl file in icc shell
ii. get_attribute [get_ports *] is_fixed
If port fixing not done, then set_attribute [get_ports *] is_fixed true
iii. Hand place your macros
iv. Check_legality -verbose : Checks the floor-plan for any overlaps
c) Placement Stage:
Pre-placement
i. read_def: reads the design data file in def format
ii. add_end_cap: adds end cap cells to current design

Example -
add_end_cap -lib_cell cellName
iii. add_tap_cell_array: adds tap cells to the current design
Example:
add_tap_cell_array -master_cell_name cellName -distance
distanceValue
iv. check_legality: Checks if all cells placed so far are fixed and not overlapping.
v. place_opt:
vi. insert_buffer/add_buffer_on_route:
vii. magnet_placement:
d) CTS Stage:
i. Get_clocks : displays all the clocks in your design
ii. Report_clocks –clock_name : displays clock information of particular clock
iii. Define_routing_rule : Defines NDR for clock.
Example:
define_routing_rule new_rule -default_reference_rule -widths {m1
0.8 m4 0.9} -spacings {m1 1.0 m4 1.0}
You can specify the reference rule with respect to which NDR is defined. It could be
default_reference_rule too. You need to specify only one reference rule at once.
iv. set_clock_tree_options –routing_rule rule_name –clock_trees
clock_name : It will link the ndr defined above to specified clock clock_name.
v. set_clock_tree_references : specifies the buffers, inverters, clock gates to be
used in CTS.
vi. Clock_opt: creates the clock tree, routing of nets, performs extraction and
optimization and hold time violation on the design.
vii. Check_clock_tree : Checks the clock trees of the current design for common
problems that can adversely impact clock tree synthesis.
e) Static Timing Analysis:
i. group_path:
ii. check_timing:
iii. psynopt -area_recovery -congestion:
iv. report_port:
v. report_qor:
vi. report_timing -from -to -trans -cap -net:
vii. report_constraints:
f) Routing Stage:
i. Global routing: route_zrt_global
ii. Track Assignment: route_zrt_track
iii. Detailed routing: route_zrt_detail -max_number_iterations 20
iv. route_opt will do all above three actions in single command.
17) Explain latch up problem briefly.

Latch up is development of low resistance path inside CMOS which is not fabricated by design, but
develops because of many CMOS connected in parallel. To avoid latch up, Tap cells are placed
periodically to break that low resistance path.
18) TCL scripting ( for each ,while , array based )


1) Write the prime time report?
2) Causes of timing violation in placement stage?

Timing violation in placement stage is due to congestion in standard cells, also HFN.
3) What are the causes of congestion?
Floorplan stage: Congestion can occur in floor-plan stage while placing macros and leaf cells. To
avoid this, we may use following command:
create_fp_placement -congestion_driven
Placement Stage: Congestion in placement stage is mainly due to high pin density or cell density. To
avoid congestion, we can use methods like spreading of cells, use of partial blockage etc.
Command for congestion driven placement is create_placement -congestion.
create_placement -congestion
create_placement -congestion_effort low|medium|high
We may also use refine_placement for refining the placement.
refine_placement -congestion_effort low|medium|high
Congestion effort option specifies the effort level for congestion mode. The default effort level is
medium.
CTS Stage: Congestion can also occur in clock tree synthesis.

clock_opt -congestion
The clock_opt is for creating and optimizing the clock tree. Argument -congestion tells the tool to
optimize the clock tree with congestion driven mode.
clock_opt_feasibility -congestion
This command performs analysis on design after CTS for optimization. -congestion argument tells
the tool to remove congestion in CTS.
psynopt -congestion
Psynopt is incremental optimization on the design. Enables congestion removal algorithms for
improved routability. By default, the command does not perform congestion removal.
Routing stage: report_congestion -routing_stage global|track|detail

Above command reports congestion map for routing stage, we need to specify weather it is global
route congestion map, track assignment congestion or detailed congestion map. By default, it is
global. The effort to create the map will be medium. To change effort, we can specify it with -effort
argument.
4) Skew, slew, Trans Everything is fixed. Latency is more why you have to reduce the latency?
If latency is more, chip might consume more power.
5) How will you get to know which buffers to use for CTS stage?
It will be mentioned in .spec file, which buffers to use. In ICC, One can use command
set_clock_tree_references for telling the tool which clock buffers to use for which clock.
Example:
icc_shell>set_clock_tree_references -clock_trees CLK1 -references
buffer4x
6) How tool will take buffers for CTS, if it's not mentioned in spec file?
The tool will take default value.
7) Inputs for prime time?

Gate level net-list, Libraries, SDC, SPEF, SDF are input to prime time.
8) Commands for keepout margin?

Select the cell = get_selection
Give keepout margin = set_keepout_margin –type soft –outer {1 1 1 1} [get_selection]
Synapse Interview Questions - 1

1) Explain about recent project and complexity?
1) Problems faced in macro placement?
Macros were of different size and shape. While doing macros some of them were overlapping.
We reiterated and made sure they should not overlap. We also reiterated the macro placement
to make sure that there is no notch.
2) How you decided channel distance between macros?

Channel length between macros = (pin pitch*no of pins) + space between pins
Number of horizontal/vertical metal layers
3) What are tap-cells, end-cap cells?

Tap cells are used to avoid latch up problems. These cells are placed at particular distance in
design to avoid latch up.
End cap cells are placed at the edge or end of the row to satisfy well tie off requirements. This
will serve as end point of that row.
4) How do you fix congestion?

There are mainly two types of congestion.
a) Congestion between macro – We can spread the macro or we can add soft blockage to
reduce congestion between macros.
b) Congestion in core – can be due to increased cell density or pin density. For increased
cell density we can add partial blockage or give keep out margin. For increased pin
density we give keep out margin.
5) What was your frequency, skew targets?

Frequency was 975 MHz and Skew was 51ps.
6) What are the guidelines for routing?

Routing order: Power routing, Clock routing, Signal routing.
7) Explain Double patterning ?

Double patterning is a technique used below 28nm technologies by the foundry, since the
distance between the metal is less and etching might not be proper. Hence we do it alternately.
For example, we do M1, M3, M5, M7 together, then we do M2, M4, M6, M8. In the case of
triple patterning, we do M1, M4, M7, M10, like that we follow.
8) Which type of drc you faced and how you fixed drc errors?
I got DRC errors related to open/shorts, minimum metal spacing, width and pitch. DRCs were
fixed manually.
9) How do you fix EM issues?

Generally we increase metal layer width wherever we get EM Issues.

1. Explain about recent project?
2. What are the problems faced in macro placement ?

Macro count was in hundreds. Non uniform sized macros were there and I had to reserve
enough routing space around macros. I had to check the macro alignment, its orientation and
avoid the crisscross placement. Did multiple iterations to avoid any notches.
3. Why we need end-cap and well tap cells ?

End cap cells are needed at the end of rows, for proper etching during fabrication. It prevents
any errors to occur in case of improper etching. Tap cells are to added periodically to avoid
CMOS latch up.
4. Have you worked on low power if yes explain.

In low power, we used upf flow. There were two power domains. Contents of upf were,
a. Create Power domain: vddOn, vddSw, vddHv
b. Create Power Supply Rails
c. Create PST: Power state table - relation between power domains (which power domain
is ON in which state)
d. Isolation strategy
e. Level Shifter strategy
Issues faced in low power stage. There was one MVRC tool. It take two inputs, netlist and upf. It
compares and verifies that upf is implemented in netlist properly. One isolation cell was
connected to vddsw while it should have been connected to vddon. Tool was recommending to
connect one more isolation cell while there was already one existing isolation cell. The issue was
with upf file which was not written correctly.
5. How to reduce insertion delay/latency ?

Set target latency as minimum. Then tool will consider less from starting. Put cells of same
hierarchy together to reduce insertion delay.
6. What happened if macro is placed in center of the core?

Placement of macro in centre should be avoided as much as possible. It leads to routing
congestion. However if it is recommended by top level to place it in center, then we can do it. If
it leads to IR drop, then we can increase power strap width, place decap or create power mesh.
7. What are causes for timing violations in placement stage?

In placement stage, the violation of timing was mainly due to module splitting.

1. What is Flip-Chip and Wirebound Technology. Which one you used in your design ?
Flip chip is more advanced, compact, smaller form factor, faster than wire-bonded packaging.
However wire-bonded is cost effective and flexible compared to flip-chip. The choice of packaging is
usually vendor specific. In my design it was wire-bonded.
2. What were the challenges in your design ?
3. Difference btw Fence n Region ?

Fence and region are terms used for bounds. Fence and region is term in Cadence encounter, in ICC,
the term is Bounds (Soft, Hard and Exclusive).
Soft bound - The tool will try to place cells inside the bound but there is no guarantee that cells will
be placed inside the bound created.
Hard bound - The tool will force the specified cells to place inside the bound, but other cells can also
come and place.
Exclusive bound - The tool will force the specified cells to place inside the bound, but other cells
cannot come and place inside the bound.
4. Different Methods to fix trans & Cap ?

Max trans violation occur when signal is too slow to rise. Hence transition is degraded. It usually
occurs when Net length is large. We can fix it by buffering the nets. To do so, we can use
add_buffer_on_route command.
Max cap violation occurs when the pin is loaded with more than maximum fan-out it can handle. We
can fix max-cap violation by Load splitting, cloning, net length, or by adding buffer.
5. Difference between PBA and GBA ?

path based - time consuming and accurate
graph based - more pessimistic and less time consuming (Considers worst slew)
6. What are Hold and setup fixes you used in your design ? Explain with commands.
a. Insert buffers with faster slew in data path.
Add_buffer_on_route : Adds buffers along the route of the specified nets.
add_buffer_on_route -repeater_distance 100 -first_distance 80 net1 lib/BUF
# adds 2 buffers, first after 80 microns from driver pin, second after 100 microns from first
buffer.
b. Remove buffers from data path

remove_buffer: Removes the buffer cells at a specified driver pin or net on a mapped
design.
remove_buffer -net [get_nets net1]
c. Replace one buffer with 2 inverters in data path
d. Upsize the standard cell

Size_cell : Relinks leaf cells to a new library cell that has the required drive strength
e. Use LVT/RVT/SVT instead of HVT

Size_cell: Same command to swap LVt to HVt
f. Adjust cell position in layout:

To adjust cell position, make cell’s attribute is_fixed as false, then move it using cursor, after
pressing M.
a. Decreasing the standard cell size or swapping the lvt/svt with hvt
Size_cell: Command for resizing the standard cell.
b. Inserting the delay cells
insert_buffer e1/Z class/B1I
7. What Special DRC fixing you did in 16nm ?

For fixing DRCs, there was separate team. I didn’t do it.
Aricent Interview Questions - 1

1) Physical cells explain in detail ?
End Cap - Added at the end of rows
Tap cell - To avoid latch up
Filler Cell - To avoid base DRC errors.
Spare Cell - Added in design keeping in mind future about perspective.
2) What all will you check once you’re done floor-plan ?

After floorplan, we will check for
a) Are there any overlaps between macros
b) Pins are placed properly on centre of tracks
c) There are no notches, and hard blockage is used if there is a notch
d) There is no congestion in between macros.
e) No I/O ports are shorted
f) DRC and LVS Checks are clean
3) How many metal did you have in your block and explain which are allocated to what ?
28nm - M9
10nm - M11
4) Why can't you use lower metals for power and clock ?
Lower metal layers have lower width and hence, they have high resistance. They can’t be used for
critical nets like power, clock.
5) How much time will your placement run will take ?

23 Hours
6) If placement run takes long time, while running how can you find congestion or timing issues
before run is completed ?
We will go to pre-placement stage reports, to see what went wrong. Based on possible problems we
will proceed.
7) Post placements checks ?

Post placement we check for timing (setup) and congestion.
8) Which tool you used for pv?

Calibre
9) Have you worked on pv?

No, there was separate team for PV.
10) What are the inputs used for primetime?

Gate level netlist, Libraries, SDC, SPEF, SDF are input to prime time.
11) How you do Channel length calculation?

Channel length = (Pitch* number of pins + Spacing)
Number of effective metal layers
Aricent interview Questions - 2

1) Explain about your recent project.
2) What are PD Inputs and Contents.
PD Inputs include the following files:
a) LEF (Physical View of Cell. i.e. its size, area, orientation etc.)
b) Lib (It contains timing and power related information of cells).
c) Upf (It is used in low power design. It contains information related to which power domain being
used, what isolation cells are being used etc.)
d) TF (Technology file, it contains information related to which metal layers are used and what are
their width, resistivity and other parameters.)
e) Netlist File (it's a verilog file containing information related to logical connection between
standard cells)
f) SDC (It’s a synopsys design constraints file which contains information related to clocks. Which
clocks are being used. What is max trans, max cap. What is clock definition, latency, uncertainty.
What is path exceptions in design, i.e. false path, multi-cycle path etc.)
g) tluplus file: It contains information related to R & C values.
h) IO Assignment File
3) Draw your Macro placement.

4) Checks after floorplan and commands
After floorplan, we check following things:
a) There should not be any overlap between macros. All macros should have required spacing and
their placement must be legalized.
b) There should not be any notches in the design and if at all, the notch is present even after
performing multiple iterations, a hard blockage must be placed.
c) The pins must be placed in the center of track and legalized.
5) Explain In detail about what you did in placement stage?

In pre-placement stage, the placement of endcap and tap cells was done. Then, all fillers cells were
added to check base DRCs. After that, filler cells were removed and placement of standard cells was
done. Placement of standard cells was timing driven.
Congestion due to pin density was observed at one end of block. We used keep out margin to
spread the cells and also used partial blockage near the pin. Some cells were AOI and OAI, with high
pin count. Synthesis team was asked to split the cell to reduce pin density. Congestion due to cell
density was also present. Cells were spreaded out using keep-out margin. Also, timing issues were
there due to module splitting. For that, we used bounds.
6) Explain Crosstalk and what commands you used for fixing it ?

Crosstalk occurs when highly switching aggressor net causes victim to change behaviour. Because of
cross-talk, the signal maybe delayed or may reach earlier than expected. To avoid crosstalk we do
shielding of switching nets like crosstalk shielding.
7) What was the process of Calibre run ? #Calibre
8) What are prime time inputs?

Inputs to prime time are tf file, sdc, lib, netlist,spef
9) How can you fix a Macro to reg setup violation?

Macro to reg is same as reg to reg path.
10) What was the run time for each stage?

Floorplan -
Placement -
CTS -
Routing -
11) How can you fix, if you have 2000 violation paths?
In prime time, we will use fix_eco_timing to analyse.
Then in primetime we will use report_bottleneck command.
12) What is your WNS value, How can you fix it?
WNS - 800 pS others were in range of 300-500 pS.
WNS after fixation of timing was 300 pS.
Total violating paths were 400.
13) What is your latency value, How can u fix it?
14) What are setup and Hold fixes commands?

g. Insert buffers with faster slew in data path.
Add_buffer_on_route : Adds buffers along the route of the specified nets.
add_buffer_on_route -repeater_distance 100 -first_distance 80 net1 lib/BUF
# adds 2 buffers, first after 80 microns from driver pin, second after 100 microns from first
buffer.
h. Remove buffers from data path

remove_buffer: Removes the buffer cells at a specified driver pin or net on a mapped
design.
remove_buffer -net [get_nets net1]
i. Replace one buffer with 2 inverters in data path
j. Upsize the standard cell

Size_cell : Relinks leaf cells to a new library cell that has the required drive strength
k. Use LVT/RVT/SVT instead of HVT

Size_cell: Same command to swap LVt to HVt
l. Adjust cell position in layout:

To adjust cell position, make cell’s attribute is_fixed as false, then move it using cursor, after
pressing M.
a) Decreasing the standard cell size or swapping the lvt/svt with hvt
Size_cell: Command for resizing the standard cell.
b) Inserting the delay cells
insert_buffer e1/Z class/B1I
15) How can you get your block size?

The command for block size is get_attribute [get_die_area] bbox
16) How do you start primetime what inputs you will give ?
17) How skew is affects Hold ?

If negative skew, it is good for hold.
18) What are the inputs for calibre? #Calibre

19) How do you start after giving the inputs to calibre? #Calibre
20) What tool does in placement stage. Algorithm in ICC for placement?
21) What physical-only cells in each stage do you use ?
Floorplan : Filler cells (for base DRC), (after checking, cells were removed)
Pre-placement : end_cap_cells, tap_cells, decap if necessary
22) How can you fix violations using spare cells ?

We can use spare cells to fix violation, usually it is done in functional eco. If there are few changes in
RTL, we will get updated netlist, which has to be implemented and this is done using spare cells in
design. In functional eco, after implementing updated netlist, there will be new violations, which
needs to be fixed.
L&T Interview Questions

1) What was complexity of your recent project?
2) What you did in every stage, and what were the challenges faced?
3) Your recent project is on 14nm and previous projects are on 28nm.
What was the difference in implementing the design.
4) If timing is not met during placement stage, can you still continue for CTS?
We should keep on checking the log continuously, and we will observe the value of WNS. If it keeps
on increasing to large value then we need to see our floorplan again.
5) What was the setup and hold values. What was WNS in placement and CTS stage?
WNS - 800 pS others were in range of 300-500 pS
WNS after fixation of timing was 300 pS
6) How many paths were violating and how you fixed?

After routing, there were around 200 path violations for setup and 150-160 path violations for hold.
We took design to primetime and did timing fixations in PT.
7) To fix timing, did you use PT ? If yes, what were the commands.
fix_eco_timing -type setup #setup
fix_eco_timing -type hold #hold
8) How did you fix IR Drop issues in pnr.

Static IR - Increase strap width (Change power.tcl)
Dynamic IR - Use decap
9) What were the guidelines given to you by PV team for your design.
10) What is difference between Graph based and Path based analysis.
GBA Mode is more pessimistic and less time consuming.
PBA is more accurate and more time consuming.
11) Out of GBA/PBA which one you use during AOCV and why ?
PBA is more pessimistic. AOCV is more accurate analysis. It considers PBA only.
report_timing -pba_mode
Qualcomm interview questions - 1

1) Introduce yourself
I have worked for 2.2 years in PD. Initially I was working with DigiComm, from there, I went to
Sandisk. Worked on 2 Projects. Then I went to Infosys. I worked for Intel Project. I did 2 projects
there.
2) Which company you worked previously ?

I was working at Infosys for Intel Project.
3) How many projects you handled till now?

Based on resume/CV.
4) What was the duration of your recent project?

Based on resume/CV
5) How you started your project?

I started with floor plan. The DEF file was given to me. It had aspect ratio set, and die size defined. IO
Ports were already placed. I started with macro placement. Then went till routing stage.
6) Explain the issues and fixes you done in your recent project ?
Floor plan issues-

There was notch issue in macro placement. Did multiple trials for avoiding notch issue. Placed
macros based on hierarchy. Followed the guidelines for macro placement. Checked for pin and
macro alignment.
Placement Issues -
I got timing violations, since module was splitted during placement. I used placement bounds to fix
setup timing. Then because of cells sitting closer, congestion due to cell density got increased. We
used keepout margin to fix congestion.
CTS Issues -
CTS goal was to fix skew and latency in clock path. In CTS, I got many shorts since since tool had
routed many signals in layers which were reserved for CTS.
Routing Stage -
We faced timing violations in routing stage which we took to prime time and fixed it.
7) What are the inputs for pd and what it contains ?

Mainly, the inputs for PD will be netlist, libs, lefs, tlu+, tech file, io assignment file, upf,
8) What is setup and hold time ?

Setup Time- Minimum time before which data signal should be held steady before the active clock
edge so that the data can be captured reliably by the flop.
Hold Time- Minimum time for which data signal should be held steady after the active clock edge so
that the data can be sampled reliably by the flop.
9) What is timing report? What does it contain?

Startpoint: in1 (input port clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk1
Path Type: max
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0 0

clock network delay (propagated) 0 0
input external delay 7500 7500.00 f
in1 (in) 142.37 7642.37 f
i1/INPUT1 (iinvc) 0.33 7642.70 f
i1/OUTPUT1 (iinvc) 1469.09 9111.79 r
out1 (out) 14.66 9126.45 r
data arrival time 9126.45
clock clk (fall edge) 10000 10000

clock network delay (propagated) 0 10000
output external delay -6000 4000
data required time 4000
-----------------------------------------------------------
data required time 4000

data arrival time -9126.45
-----------------------------------------------------------
slack (VIOLATED) -5126.45
10) What about STA? What are the things you come across in it?
During STA, we try to fix max cap, max trans, max fan-out, setup, hold related issues. We take the
updated netlist along with spef, .sdc, .lib in prime time and fix timing in all corners.
11) What is fixes you done for both setup and hold? Explain in detail?
12) Utilization after floor-plan and placement? Also, total design utilization?
13) Which are the scripting languages you know?

I know perl basics.
14) How much time you took for each fixes in each stages?
15) What is the runtime for placement?

20 hours
16) What is the duration of your recent project?

6 Months
17) Have worked on both innovus and icc2 tool?

Icc only
18) Have you done pv checks? What are those? Explain in brief.
For PV, different team was there. I fixed only shorts.
Qualcomm interview Questions -2

1st round (PD Profile)
1. How you start your floor-plan?

Floorplan DEF was given to me. I did read_def. It contained block shape and sizing done. I/O Ports
were placed. After that, I placed macros based on hierarchy.
2. Qualifying for each stage?
3. Numbers - Timing, Congestion?

It might vary from project to project
4. Diff between set_false_path and set_disable_timing ?

When a false path is set, timing arc will exist and tool will calculate it but will not report. While, if
disable timing arc is true then, tool will not calculate the timing and there will not be any timing arc.
5. If an uncertainty already added to the paths why don’t you check hold before CTS.
The uncertainty before CTS is just an estimate and not real one. The clock is ideal before CTS and
hence we prefer to check once clock is synthesized.
6. Steps to minimize the WNS before Routing and ECO.
7. TAP Cell distance, who will give you the number ?

Tap cell distance was 20um and was given from foundary.
8. What is the Name of the check for missing tap for cell?
Preplacement checks
9. How will you highlight the net in the GUI?

Change_selection in ICC
10. Diff between %hash and @array?

Hash is not ordered set of objects while an array is.
11. Write a script to find all the instances with Name inst_* from report?
2nd round (STA Profile)
1. How will you place macro?

I will place macros based on hierarchy and data flow diagram.
2. What are physical cells ?

End caps, Tap cells, Decap Cells, Fudicial Cells, Tie Cells, Fillers.
3. Timing Numbers each stage?

Project Based
4. What were target skew and Target Latency ?

Answer based on clock frequency, block size.
5. How did you achieve your skew with this latency number - your block contains 11.89 million
gates?
6. How will you try to minimize the timing in placement and CTS stage ?
Usually placement bounds and path grouping is used to minimize timing in placement stage.
In CTS we can use high driving strength buffers, replace buffers with pair of inverters etc. to
minimize timing.
7. Consider your latency is more, how will you minimize it after CTS is done?
We can reduce latency by using upsized buffers in CTS.
8. How target latency can be achieved?

I had set lesser target than actual one in my CTS Spec file. Hence I was able to meet my target.
9. If a block is placed between two flops, and also combinational path also split due to that, routing
detoured. In this path, timing violation is there, how you will meet timing in this case?
10. Rectilinear block is given to you, how will you proceed?

Qualcomm Interview Questions -3

1st Round
1. What are inputs to PD?

Go here.
2. Explain issues faced while placing macros.
3. What was your tap-cell spacing?

20um
4. What issues did you face in placement stage?

Congestion and timing related issues.
5. How tool calculates cap and trans? How does it come to know that cap and trans are violated ?
6. How will you fix cap and transition violation?
7. How will you qualify your placement stage apart from timing checks?
Apart from timing, we need to see that there is no congestion. Also, there should not be excessive
buffering done by tool. The floorplan utilization should not shoot up too much.
8. How did you decide uncertainty in placement stage?

Uncertainty is skew + jitters. Overall, it should be around 25%-30% of clock period.
9. How will you qualify CTS apart from timing checks?

Apart from timing, we need to see crosstalk violations, floorplan utilization, target skew and latency
should meet.
10. If setup is violated by 200ps, your clock period is 1ns, and what will you do next. Will you proceed
for routing or go back to rerun CTS after applying fixes for timing violation?
11. If setup or hold is violated at last. Can you still proceed for tape-out? If yes, how will you proceed?
Yes in setup violation, we can proceed for tape-out with reduced frequency.
12. Scenario based question for ECO Stage:

a. If data path is optimized, and setup is violating by 100ps. What will you do to fix
timing?
b. Continuing above, if setup is also violating by 150ps in next path, and data path is
again optimized now what can be done.
13. What was your latency after CTS? How did you achieve it?
14. If tool has optimized the clock tree and still the skew is not met in 2000 paths. The clock buffers
used in tree are of highest available strength. What will you do to fix skew?
In that case, mostly it could be related to fan-out of clock.
15. If you have fixed setup in one path but it led to hold violation. List all possible causes for this and
how will you fix it.
2nd Round
1. Explain full PD Flow.
2. Inputs for each stage. How will you proceed from beginning?
Go here
3. Issues faced in each stage.

Go here
4. Commands for each stage.

Go to Mediatek face to face interview questions-2, Question no 16
5. How tool calculates cell delay?

Tool calculates cell delay based on input trans and output load
6. What are timing models available for calculation of cell delays?

There is non-linear delay model and concurrent current source model. Tool prefers CCS since it is
more accurate.
7. How tool calculates library setup time?
For one corner, characterization of setup time is done and table is made for input Trans and output
load. Tool will pick-up setup and hold values from this table.
8. For a same standard cell used at many places in design, why library setup time is not reported
same across design?
Library setup time for same flavor of standard cell will vary across different corners. For one single
corner setup time is same.
9. What sort of scripts did you work on. Then, Scripting related questions ?
10. How will you get all cells and instances of same hierarchy?
11. Commands for timing fixing.
Extra Questions
1) What are inputs to PD ?
a) Netlist (logical connection connections)

b) SDC (Design constraints)
a. Clock Definition, Uncertainty, Latency
b. IO Delays
c. DRV Constraints (Max transition, Max capacitance, Max fanout)
d. Path Exceptions (False path, Multicycle Path)
c) Libraries (lib, tlu+, lef, tech file)
a. Logic
b. Physical
c. Timing
i. Modes
1. Func
2. Test
a. Scan capture
b. Scan shift
c. Scan AC
d. Scan DC
ii. Corners
d. Technology file
d) IO Assignment File
2) Explain Antenna Effect ?
Antenna effect is plasma induced gate oxide damage that can cause reliability problems in
manufacturing of MOS ICs. It occurs due to accumulation of charge carriers near the gate of transistor.
The tool will calculate if metal area connected to gate is more than gate area then, charge accumulation
will occur and may damage the gate. Hence, we need to reduce it. It can be done by use of metal jogging
technique (use of higher metal layers), use of standard cells or use of reverse bias diode.
3) What is Electromigration ?
It is the slow displacement of metal atoms in a semiconductor. It occurs when the current density is high
enough to move metal ions in direction of electron flow. This phenomenon causes the eventual loss of
connections or failure of a circuit. Hence, the circuit faces reliability issues. To test for reliability, the DUT
is put under high temperature operating life conditions, and the data obtained is extrapolated to
estimate the durability.
4) What is difference between keep-out margin and blockage?
Ans - Keep out margin is attached to cell/instance, which means if you move cell/instance the keep-out
margin also moves along with the cell. Blockage depends on its coordinate; hence it stays in the same
place.
5) How exactly is Well TAP cells used to overcome latch-up?
Tap cells ensures n-well substrate continuity in the design. Tap cells should be placed such that they
have uniform horizontal periodicity and vertical continuity in the design. Horizontal periodicity reduces
when we migrate the design from upper node to lower node. Vertical continuity can be disturbed only if
macros are placed in the path of the tap cells.
6) What are all the ways to fix setup violation?
⎯ Remove/reduce buffers from data path

⎯ Replace existing buffers, with buffers of faster slew
⎯ LVT Swap
⎯ Upsizing the buffers
⎯ Reduce the net delay by using higher metal resources
⎯ Clock pushing (de-touring the clock to slow it down)
⎯ Cloning (dividing the load by adding a clone of buffer to make it fast)
⎯ Replace buffers with two inverters placed farther apart
⎯ Readjust the position of buffers
7) What are commands for sanity check?
Ans – Netlist Checks - Check_design

SDC Checks – Check_timing
Library Checks – Check_library
Netlist vs SDC – report_timing
8) How will you create the logical power and ground connections in design?
Ans – derive_pg_connection will connect power and ground pin to specified power and ground
nets. To verify weather all power and ground pins of standard cells, macro cells are connected to
corresponding power and ground nets, we can use verify_pg_nets.
9) What is the use of Tie cell ?

Ans - Tie cell is normally used to tie the standard cell or spare cell or any floating input to a known state.
We don’t connect standard cell to a power rail directly, because, it can cause loading issues on rails. Tie
cell helps in reducing the load.
10) What are the sign off checks you performed and how did you do it. Explain with commands.
Sign off checks - DRC and LVS.
11) While analysing setup at worst case slow corner, we don’t derate the late path, however we
derate the early path. Why ?
In slow corner (worst case slow), the data path is already the slowest possible. Hence, we don’t derate it
further.
12) Explain the analysis of in2reg, reg2out, in2out timing analysis ?
13) How tool will know that clock is ideal in placement stage ?
14) What is pipelining technique for fixing the timing of design ? How is it used, explain with commands
?
15) How synchronous cells help in meeting the timing ?
Physical Design Questionnaire

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CLIENT INTERVIEW Pozibility

Mediatek interview questions - 1 2

MediaTek Interview Questions -2 4

Mediatek face to face interview questions -1 7

Mediatek face to face interview questions -2 8

Mediatek face to face interview questions -3 13

Synapse Interview Questions - 1 15

Synapse Interview Questions - 2 16

Synapse Interview Questions - 3 17

Aricent Interview Questions - 1 19

Aricent interview Questions - 2 20

L&T Interview Questions 22

Qualcomm interview questions - 1 23

Qualcomm interview Questions -2 26

Qualcomm Interview Questions -3 28

Mediatek interview questions - 1

3) What will you do if there is a timing violation in placement stage?

5) In which corner you fixed setup?

6) Have you worked on low power? If yes...explain

7) What will you do if 200 PS violation in placement stage?

8) Have u fixed setup or hold? If yes, then how?

a. Decreasing the standard cell size

9) If skew is less then will it affect setup or hold... and how?

MediaTek Interview Questions -2

3. How will you solve if flop is connected to multiple clocks?

4. How will you start FP?

5. Have you worked on upf? What are special cells?

6. Will standard cell power rails will be overlapped on ip?

9. What was the utilization of your block from FP to routing?

10. In placement what issues you have faced?

11. How you solved the congestion? Give the commands?

13. How you have fixed DRC?

14. Extract and compare errors in LVS?

15. GPA and PBA difference?

16. What is NDR?

18. What is latency?

21. In CTS which topology you have used?

23. Why clock buffer is used instead of normal buffer in CTS?

Mediatek face to face interview questions -1

2) How do you say a floorplan is good?

3) Is utilization depends on floor plan after place opt ?

4) How do you fix congestion and timing ?

5) How do you find channel between macros ?

6) Did u have any feed through pins ?

7) What does spec file contains ?

9) What is use of ndr in spec file ?

12) How did you fix LVS from Calibre ? #Calibre

13) Inputs for Star rc and inputs for pt shell ?

14) Explain routing which net will u route first ?

Mediatek face to face interview questions -2

4) CTS methodology and commands

5) Explain routing in detail?

6) What are the inputs for star rc ?

7) How will you add end cap n tap cells

8) What is the use of filler cells and purposes of metal filling?

9) Explain clock gating?

11) When you will do clock push?

12) How will you analyze the report?

13) ECO timing fixing commands?

14) How will you fix LVS and DRC?

16) Explain all commands in each stage in ICC.

ii. add_end_cap: adds end cap cells to current design