DSP56858 Evaluation Module User's Manual: Order This Document by DSP56858EVMUM/D Rev. 2.0, 10/07/2002

Freescale Semiconductor, Inc.
Order this document by

DSP56858EVMUM/D
Rev. 2.0, 10/07/2002
Freescale Semiconductor, Inc...
DSP56858 Evaluation Module

User’s Manual
© Motorola, Inc., 2002. All rights reserved.
For More Information On This Product,

Go to: www.freescale.com
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.

Table of Contents
Preface
Chapter 1
Introduction
1.1 DSP56858EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 DSP56858EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 DSP56858EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1 DSP56858 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI Serial EEPROM/Data FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 RS-232 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.7 Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8.1 JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.9 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12.1 Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13 Daughter Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.13.1 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-18
2.13.2 Peripheral Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-19
2.14 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.15 Host Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.16 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
MOTOROLA Table of Contents i

Appendix A
DSP56858EVM Schematics
Appendix B
DSP56858EVM Bill of Material
ii DSP56858EVM User’s Manual MOTOROLA

List of Figures
1-1 Block Diagram of the DSP56858EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 DSP56858EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the DSP56858EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . 2-3
2-2 Schematic Diagram of the External CS1/CS2 Memory Interface . . . . . . 2-4
2-3 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-4 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . 2-9
2-7 Block Diagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . 2-11
2-8 Schematic Diagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-12
2-9 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-13
2-10 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 CODEC Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-12 CS4218 Stereo Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-13 Diagram of the USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MOTOROLA List of Figures iii

iv DSP56858EVM User’s Manual MOTOROLA

List of Tables
1-1 DSP56858EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-1 SPI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-2 RS-232 Serial Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4 LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 JTAG Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-6 Parallel JTAG Interface Disable Jumper Selection. . . . . . . . . . . . . . . . . 2-10
2-7 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . 2-11
2-8 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-9 ESSI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-10 GPIO Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-11 Memory Daughter Card Connector Description. . . . . . . . . . . . . . . . . . . 2-18
2-12 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . 2-19
2-13 Host Interface Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
MOTOROLA List of Tables v

vi DSP56858EVM User’s Manual MOTOROLA

Preface
This reference manual describes in detail the hardware on the DSP56858 Evaluation
Module.
Audience
This document is intended for application developers who are creating software for
devices using the Motorola DSP56858 part.
Organization
This manual is organized into two chapters and two appendixes.
• Chapter 1, Introduction - provides an overview of the EVM and its features.
• Chapter 2, Technical Summary - describes in detail the DSP56858 hardware.
• Appendix A, DSP56858EVM Schematics - contains the schematics of the
DSP56858EVM.
• Appendix B, DSP56858EVM Bill of Material - provides a list of the materials used on
the DSP56858EVM board.
Suggested Reading
More documentation on the DSP56858 and the DSP56858EVM kit may be found at URL:
http://www.mot.com/SPS/DSP/documentation/index.html
MOTOROLA Preface vii

Notation Conventions
This manual uses the following notational conventions:
Term or Value Symbol Examples Exceptions
Active High Signals No special symbol A0

(Logic One) attached to the signal CLKO
name
Active Low Signals Noted with an WE In schematic drawings,

(Logic Zero) overbar in text and in OE Active Low Signals may be
most figures noted by a backslash: /WE
Hexadecimal Values Begin with a “$” sym- $0FF0

bol $80
Decimal Values No special symbol 10

attached to the 34
number
Binary Values Begin with the letter b1010

“b” attached to the b0011
number
Numbers Considered positive 5 Voltage is often shown as

unless specifically -10 positive: +3.3V
noted as a negative
value
Blue Text Linkable on-line ...refer to Chapter 7,

License
Bold Reference sources, ...see:

paths, emphasis http://www.mot.com/S
PS/DSP...
Definitions, Acronyms, and Abbreviations

Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference..
Codec COder/DECoder; a part used to convert analog signals to digital (coder)

and digital signals to analog (decoder)
DIP Dual Inline Package
DSP Digital Signal Processor or Digital Signal Processing
EEPROM Electrically Erasable Programmable Read-Only Memory
viii DSP56858EVM User’s Manual MOTOROLA

EOnCE Enhanced On-Chip Emulation; a debug bus and port created by Motorola
to enable a designer to create a low-cost hardware interface for a
professional quality debug environment
ESSI Enhanced Synchronous Serial Interface; a communications port on
Motorola’s family of DSPs
EVM Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application.
GPIO General Purpose Input and Output port on Motorola’s family of DSPs;
does not share pin functionallity with any other peripheral on the chip
and can only be set as an input, output or level-sensitive interrupt input

HI Host Interface; a communications port on Motorola’s family of DSPs
IC Integrated Circuit
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LED Light Emitting Diode
LQFP Low Profile Quad Flat Pack package
MPIO Multi Purpose Input and Output port on Motorola’s family of DSPs;
shares package pins with other peripherals on the chip and can function
as a GPIO
PCB Printed Circuit Board
PLL Phase Locked Loop
RAM Random Access Memory
ROM Read Only Memory
SCI Serial Communications Interface; a communications port on Motorola’s
family of DSPs
SPI Serial Peripheral Interface; a communications port on Motorola’s family
of DSPs
SRAM Static Random Access Memory
SSI Synchronous Serial Interface; a communications port on Motorola’s
family of DSPs
MOTOROLA Preface ix
THD Total Harmonic Distortion

USB Universal Serial Bus
WS Wait State
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM/D
[2] DSP5685x 16-Bit Digital Signal Processor User’s Manual,

DSP5685xUM/AD
[3] DSP56858 16-Bit Digital Signal Processor Technical Data, DSP56858/D
x DSP56858EVM User’s Manual MOTOROLA

Chapter 1
Introduction
The DSP56858EVM is used to demonstrate the abilities of the DSP56858 and to provide a
hardware tool allowing the development of applications that use the DSP56858.
The DSP56858EVM is an evaluation module board that includes a DSP56858 part, 16-bit
stereo codec, USB 1.1/2.0 interface, external memory and a daughter card expansion
interface. The daughter card expansion connectors are for signal monitoring and user
feature expandability.
The DSP56858EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800E
architecture. The tools and examples provided with the DSP56858EVM facilitate
evaluation of the feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/Enhanced
OnCE (EOnCE) port. The breakpoint features of the EOnCE port enable the user
to easily specify complex break conditions and to execute user-developed software
at full speed until the break conditions are satisfied. The ability to examine and
modify all user-accessible registers, memory and peripherals through the EOnCE
port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, providing the user with the ability to reassign any and all of the DSP's
peripherals. The EOnCE port's unobtrusive design means that all memory on the
board and on the DSP chip is available to the user.
1.1 DSP56858EVM Architecture

The DSP56858EVM facilitates the evaluation of various features present in the DSP56858
part. The DSP56858EVM can be used to develop real-time software and hardware
products based on the DSP56858. The DSP56858EVM provides the features necessary
MOTOROLA Introduction 1-1

for a user to write and debug software, demonstrate the functionality of that software and
interface with the customer’s application-specific device(s). The DSP56858EVM is
flexible enough to allow a user to fully exploit the DSP56858’s features to optimize the
performance of his product, as shown in Figure 1-1.
DSP56858
RESET SPI Data FLASH

LOGIC RESET SPI 1M-bit
IRQ IRQ Interface
MODE RS-232 DSub

MODE SCI0 Interface
LOGIC 9-Pin
CS0 Address,
(Program Memory) Data &
128Kx16-bit SRAM Control
Peripheral
CS1/CS2
ESSI1 Daughter Card
(Data Memory)
Connector
128Kx16-bit SRAM SCI1
Memory
Daughter Card
Connector
Stereo Line In
USB USB Interface Stereo 16-bit
Con (CS3) ESSI0 Codec
Stereo Line Out
Amp Headphone Jack

JTAG JTAG/EOnCE
Connector GPIO Debug LEDs
DSub Parallel
JTAG Host Interface
25-Pin HI
Interface Connector
4.00MHz +1.8V, +3.3V Power Supply

XTAL/EXTAL
Crystal & GND +1.8V, +3.3V & +5.0V
Figure 1-1. Block Diagram of the DSP56858EVM
1.2 DSP56858EVM Configuration Jumpers

Ten jumper groups, (JG1-JG11), shown in Figure 1-2, are used to configure various
features on the DSP56858EVM board. Table 1-1 describes the default jumper group
settings.
1-2 DSP56858EVM User’s Manual MOTOROLA

DSP56858EVM Configuration Jumpers
2 8 2 4
JG10 JG8
1 7 1 3 JG1 JG9 JG11 JG5
6 5
2 1 P3 J5 S1
P1
JG5
TB1
P2
JG2
S/N
JG7 JG8
JG1
JG9
RESET JTAG 1 2
DSP56858EVM
RE10519B REV
JG11
J3 3 4
3 1 JG10 J2 U2
S2
U1 U3
IRQA
S3 HEADPHONE
JG6
JG4 J4
JG7 JG4 JG3
JG2
J1
IRQB
P6 1 2
S4
Y1 JG6
JG3 LEDS
U6
S4
P4 P5
U7 LINE LINE
IN OUT
3 1 9 10
Figure 1-2. DSP56858EVM Jumper Reference
Table 1-1. DSP56858EVM Default Jumper Options

Jumper Jumpers
Comment
Group Connections
JG1 Enable on-board Word selectable SRAM via CS0 (U2) 1–2
JG2 Enable on-board Byte selectable SRAM via CS1/CS2 (U3) 1-2, 3-4
JG3 Use on-board EXTAL crystal input for DSP oscillator 2–3
JG4 Use on-board XTAL crystal input for DSP oscillator 1–2
JG5 Enable on-board Parallel JTAG Host/Target Interface NC
JG6 Enable ESSI0 Port for CODEC data 1-2, 3-4, 5-6, 7-8,
9-10
JG7 Enable GPIO for CODEC control 1-2, 3-4, 5-6
JG8 Enable SCI0 Port to RS-232 transceiver 1–2, 3-4
JG9 Enable RS-232 output NC
JG10 Enable SPI Port to Serial EEPROM/Data FLASH 1–2, 3–4, 5–6 & 7–8
JG11 Enable USB interface via CS3 1-2
MOTOROLA Introduction 1-3

1.3 DSP56858EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply or external +5.0V DC lab power supply to the
DSP56858EVM board.
Parallel Extension
Cable
DSP56858EVM
PC-compatible
Computer
P1
Connect cable P2 TB1

to Parallel/Printer port
External +5.0V
with 2.1mm, +12.0V Lab
receptacle Power Supply
connector
Figure 1-3. Connecting the DSP56858EVM Cables
Perform the following steps to connect the DSP56858EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3,
on the DSP56858EVM board. This provides the connection which allows the host
computer to control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the
external +5.0V DC 1A lab power supply is not plugged into a +120V AC power
source.
4. Connect the 2.1mm output power plug from the external switching power supply
into P2, shown in Figure 1-3, on the DSP56858EVM board. Optionally, attach an
external +5.0V DC lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.

Chapter 2
Technical Summary
The DSP56858EVM is designed as a versatile Digital Signal Processor, (DSP),
development card for developing real-time software and hardware products to support a
new generation of applications in digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit
DSP56858 DSP, combined with the on-board 128K × 16-bit external program/data static
RAM (SRAM), 128K × 16-bit external data/program SRAM, RS-232 interface, Stereo
16-bit codec interface, USB 2.0 interface, Daughter Card Expansion interface and parallel
JTAG interface, makes the DSP56858EVM ideal for developing and implementing many
audio and voice algorithms, as well as for learning the architecture and instruction set of
the DSP56858 processor.
The main features of the DSP56858EVM, with board and schematic reference designators
include:
• DSP56858 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]

• External fast static RAM (FSRAM) memory, configured as:
— 128K×16-bit of memory [U2] with one wait state at 120MHz via CS0
— 128K×16-bit of memory [U3] with one wait state at 120MHz via CS1/CS2
• 1M-bit Serial EEPROM/Data FLASH [U4]
• 4.00MHz crystal oscillator for DSP frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG3 and JG4]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P1]
• RS-232 interface for easy connection to a host processor [U5 and P3]
• 16-bit stereo codec interface [U6, JG6, JG7, P4 and P5]
• Stereo headphone interface [U8 and P6]
• Codec sample rate selector [S5]
MOTOROLA Technical Summary 2-1

• USB interface [U15and J5]

• Peripheral Daughter Card Expansion Connector, to allow the user to connect his
own SCI, ISSI, SPI or GPIO-compatible peripheral to the DSP [J2]
• Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the DSP [J1]
• Host Interface Connector, for high-speed bus data transfer [J4]
• On-board power regulation from an external +12V DC-supplied power input [P2]
• On-board power regulation from an optional +5V DC-supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]

• Boot MODE selector [S4]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
2.1 DSP56858
The DSP56858EVM uses a Motorola DSP56858FV120 part, designated as U1 on the
board and in the schematics. This part will operate at a maximum speed of 120MHz. A full
description of the DSP56858, including functionality and user information, is provided in
these documents:
• DSP56858 Technical Data, (DSP56858/D): Provides features list and

specifications, including signal descriptions, DC power requirements, AC timing
requirements and available packaging
• DSP5685x User’s Manual, (DSP5685xUM/AD): Provides an overview description
of the DSP and detailed information about the on-chip components, including the
memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem
• DSP56800E Reference Manual, (DSP56800ERM/D): Provides a detailed
description of the core processor, including internal status and control registers and
a detailed description of the family instruction set
Refer to these documents for detailed information about chip functionality and operation.
They can be found on this URL:
http://www.motorola.com/semiconductors

Program and Data Memory
2.2 Program and Data Memory

The DSP56858EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS2.
2.2.1 SRAM Bank 0

SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI
GS72116, labelled U2) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-1. CS0 can be configured to use this memory bank as 16-bit program
memory, data memory, or both. Additionally, CS0 can be configured to assign this
memory’s size and starting address to any modulo address space.
This memory bank will operate with one wait state access while the DSP56858 is running
at 120MHz and can be disabled by removing the jumper at JG1.
DSP56858 GS72116
A0-A16 A0-A16
D0-D15 DQ0-DQ15
RD OE
WR WE
CS0
+3.3V
Jumper Pin 1-2: JG1

Enable SRAM
1
2
Jumper Removed: CE
Disable SRAM
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1

SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K×16-bit Fast Static RAM
(GSI GS72116, labelled U3) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte
(8-bit) or word (16-bit) accessable program memory, data memory, or both. Additionally,

CS1 and CS2 can be configured to assign this memory’s size and starting address to any
modulo address space.
This memory bank will operate with one wait state access while the DSP56858 is running
at 120MHz and can be disabled by removing the jumpers at JG2.
DSP56858 GS72116
A0-A16 A0-A16
D0-D15 DQ0-DQ15
RD OE
WR WE
JG2
CS1 1 2 LB
CS2 3 4 HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:

Enable SRAM High Byte
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface

SPI Serial EEPROM/Data FLASH Memory
2.3 SPI Serial EEPROM/Data FLASH Memory

A 1M-bit +3.3V SPI serial EEPROM/Data FLASH Memory, Atmel AT45DB011B-SC, is
provided on the DSP56858EVM, reference Figure 2-3. This memory connects directly to
the SPI Port through a header on the DSP56858. It can be used to load program code and
data into the DSP56858’s internal or external memory spaces. Jumper block JG10 is
provided to allow the user to disconnect the on-board SPI EEPROM/Data FLASH from
the SPI port and allow him to connect his own SPI port peripheral. The header details are
shown in Table 2-1.
Data FLASH Enable Serial EEPROM /

DSP56858 (SPI Port Connector) Data FLASH
MOSI/SRFS SDI
MISO/SRCK SDO
SCLK/STCK SCK
SS/STFS/PC3 CS
JG10
Figure 2-3. SPI EEPROM Memory Block Diagram
Table 2-1. SPI Port Connector Description
JG10
Pin # Signal Pin # Signal
1 SS/PF3 2 CS
3 MISO/PF0 4 SDO
5 MOSI/PF1 6 SDI
7 SCK/PF2 8 SCK

2.4 RS-232 Serial Communications

The DSP56858EVM provides an RS-232 interface by the use of an RS-232 level
converter, (Maxim MAX3245EEAI, designated as U5). Refer to the RS-232 schematic
diagram in Figure 2-4. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232-compatible signal levels and connects to the host’s serial port via
connector P3. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pinout of connector P3 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG9.
RS-232
DSP56858 Level Converter
Interface
P3
1
6
TXD0 T1in T1out 2

7
RXD0 R1out R1in
3
8
4
+3.3V 9
x
5
FORCEOFF
Jumper Removed: JG9

Enable RS-232
1
2
Jumper Pin 1-2:
Disable RS-232
Figure 2-4. Schematic Diagram of the RS-232 Interface
Table 2-2. RS-232 Serial Connector Description
P3
1 Jumper to 6 & 4 6 Jumper to 1 & 4
2 TXD0 7 Jumper to 8
3 RXD0 8 Jumper to 7
4 Jumper to 1 & 6 9 N/C
5 GND

Operating Mode
2.5 Clock Source

The DSP56858EVM uses a 4.00MHz crystal, Y1, connected to its external crystal inputs,
EXTAL and XTAL. To achieve its 120MHz maximum operating frequency, the
DSP56858 uses its internal PLL to multiply the input frequency by 30. An external
oscillator source can be connected to the DSP by using the oscillator bypass connectors,
JG3 and JG4; see Figure 2-5. If the input frequency is above 4MHz, then the EXTAL
input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2. The
input frequency would then be injected on JG3’s pin 2. If the DSP needs to be
synchronized to the codec’s sample frequency, then the DSP’s input frequency should be
jumpered using the 12.2280MHz codec frequency. If the input frequency is below 4MHz,
then the input frequency can be injected on JG4’s pin 2.
EXTERNAL
OSCILLATOR
HEADERS DSP56858
JG4
3
2 EXTAL
+1.65V 1
4.00MHz
JG3
1
2 XTAL
12.2880MHz 3
Figure 2-5. Schematic Diagram of the Clock Interface
2.6 Operating Mode

The DSP56858EVM provides a boot-up MODE selection switch, S4. This switch is used
to select the operating mode of the DSP as it exits RESET. Refer to the DSP56858 User’s
Manual for a complete description of the chip’s operating modes. Table 2-3 shows the
two operation modes available on the DSP56858.
Table 2-3. Operating Mode Selection
Operating Mode S4 (ON) Comment
0 1–2, 3-4 & 5-6 Bootstrap from External byte-wide memory
1 3-4 & 5-6 Bootstrap from SPI
2 1-2 & 5-6 Normal Expanded mode
3 5-6 Development Expanded mode

Table 2-3. Operating Mode Selection
Operating Mode S4 (ON) Comment
4 1-2 & 3-4 Host Interface Port Single Strobe mode
5 3-4 Host Interface Port Dual Strobe mode
2.7 Debug LEDs

Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging
for user programs. These LEDs will allow the programmer to monitor program execution
without having to stop the program during debugging; refer to Figure 2-6.
Table 2-4describes the control of each LED.

Table 2-4. LED Control
Controlled by
User LED Port Signal
LED1 Port D PD0
LED2 Port D PD1
LED3 Port D PD2
LED4 Port D PD3
LED5 Port D PD4
LED6 Port D PD5
Setting PD0, PD1, PD2, PD3, PD4 or PD5 to a Logic One value will turn on the
associated LED.

Debug Support
DSP56858 INVERTING BUFFER

+3.3V
RED LED
PD0
YELLOW LED
PD1
GREEN LED
PD2
RED LED
PD3
YELLOW LED
PD4
GREEN LED
PD5
Figure 2-6. Schematic Diagram of the Debug LED Interface
2.8 Debug Support

The DSP56858EVM provides an on-board Parallel JTAG Host Target Interface and a
JTAG interface connector for external Target Interface support. Two interface connectors
are provided to support each of these debugging approaches. These two connectors are
designated the JTAG connector and the Host Parallel Interface Connector.

2.8.1 JTAG Connector

The JTAG connector on the DSP56858EVM allows the connection of an external Host
Target Interface for downloading programs and working with the DSP56858’s registers.
This connector is used to communicate with an external Host Target Interface which
passes information and data back and forth with a host processor running a debugger
program. Table 2-5 shows the pin-out for this connector.
Table 2-5. JTAG Connector Description
J3

1 TDI 2 GND
3 TDO 4 GND
5 TCK 6 GND
7 NC 8 KEY
9 RESET 10 TMS
11 +3.3V 12 NC
13 DE 14 TRST
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG5. Reference
Table 2-6 for this jumper’s selection options.
Table 2-6. Parallel JTAG Interface Disable Jumper Selection
JG5 Comment
No jumpers On-board Parallel JTAG Interface Enabled
1–2 Disable on-board Parallel JTAG Interface

Debug Support
2.8.2 Parallel JTAG Interface Connector

The Parallel JTAG Interface Connector, P1, allows the DSP56858 to communicate with a
Parallel Printer Port on a Windows PC; reference Figure 2-7. Using this connector, the
user can download programs and work with the DSP56858’s registers. Table 2-7 shows
the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG5
should be removed, as shown in Table 2-6.
DB-25 Connector Parallel JTAG Interface DSP56858
TDI IN OUT TDI

TDO OUT IN TDO

P_TRST IN OUT TRST
TMS IN OUT TMS
TCK IN OUT TCK
P_RESET IN OUT RESET
P_DE IN OUT DE
+3.3V
EN
JG5
Jumper Removed:
Enable JTAG I/F 1
2
Jumper Pin 1-2:
Disable JTAG I/F
Figure 2-7. Block Diagram of the Parallel JTAG Interface
Table 2-7. Parallel JTAG Interface Connector Description

P1
1 NC 14 NC
2 PORT_RESET 15 PORT_IDENT
3 PORT_TMS 16 NC
4 PORT_TCK 17 NC
5 PORT_TDI 18 GND
6 PORT_TRST 19 GND
7 PORT_DE 20 GND

Table 2-7. Parallel JTAG Interface Connector Description
P1
8 PORT_IDENT 21 GND
9 PORT_VCC 22 GND
10 NC 23 GND
11 PORT_TDO 24 GND
12 NC 25 GND
13 PORT_CONNECT
2.9 External Interrupts

Two on-board push-button switches are provided for external interrupt generation, as
shown in Figure 2-8. S1 allows the user to generate a hardware interrupt for signal line
IRQA. S2 allows the user to generate a hardware interrupt for signal line IRQB. These two
switches allow the user to generate interrupts for his user-specific programs.
+3.3V
DSP56858
10K
S2
IRQA
0.1µF
+3.3V
10K
S3
IRQB
0.1µF
Figure 2-8. Schematic Diagram of the User Interrupt Interface

Reset
2.10 Reset
Logic is provided on the DSP56858 to generate an internal Power-On RESET. The
DSP56858EVM provides reset logic to support the RESET signals from the JTAG
connector, the Parallel JTAG Interface and the user RESET push-button; refer to
Figure 2-9.
JTAG_RESET
RESET
RESET
PUSHBUTTON
MANUAL RESET
TRST
JTAG_TAP_RESET
Figure 2-9. Schematic Diagram of the RESET Interface

2.11 Power Supply

The main power input, +12.0V DC/AC, to the DSP56858EVM is through a 2.1mm coax
power jack. An optional +5.0V DC power supply input is available through a 2-pin
terminal block, TB1. A +12.0V DC 1.2A power supply is provided with the
DSP56858EVM; however, less than 500mA is required by the EVM. The remaining
current is available for user daughter card applications when connected to the daughter
card interface. The power regulation on the DSP56858EVM provides +5.0V DC voltage
regulation for the codec’s analog circuits and to the additonal voltage regulation logic on
the EVM. The additonal voltage regulation logic provides +1.8V DC voltage regulation
for the DSP’s core and +3.3V DC voltage regulation for the DSP’s I/O, memory, parallel
JTAG interface and supporting logic; refer to Figure 2-10. Power applied to the
DSP56858EVM is indicated with a Power-On LED, referenced as LED7.
P2
+5.0V Power +5.0V DC
+12.0V DC CODEC
Regulator Condition Analog
TB1
+3.3V +3.3V DC
+5.0V DC DSP56858
Regulator
GND
DSP56858EVM
PARTS
+1.8V +1.8V DC DSP56858

Regulator CORE
Figure 2-10. Schematic Diagram of the Power Supply

Stereo Codec
2.12 Stereo Codec

A 16-bit audio-quality stereo codec, Crystal Semiconductor CS4218, is connected to the
DSP56858’s ESSI port to support audio, voice and signal analysis applications. The codec
is clocked with a 12.288MHz oscillator. This allows the codec to operate between a
sample frequency of 8KHz and 48KHz. The sample rate can be manually set by setting the
appropriate switch positions on DIP switch S5. The sample rate selections possible using
this three-position dip switch are detailed in Table 2-8. The codec supports +3.3V digital
levels, eliminating the need for voltage level translation circuitry. Additionally, a set of
zero ohm resistors are provided on the EVM to allow a user to disconnect the on-board
codec from the ESSI port and allow him to connect his own codec to the ESSI port; see
Figure 2-12. The on-board codec has analog signal conditioning logic, allowing direct
connection to its line-level input and line-level output signals through two 1/8” stereo
jacks; reference Figure 2-11.
Table 2-8. Codec Sample Rate Selector
SW 5 SW 5 SW 5
Position 3 Position 2 Position 3 Sample Rate
(MF6) (MF7) (MF8)
ON ON ON 48.00KHz
ON ON OFF 32.00KHz
ON OFF ON 24.00KHz
ON OFF OFF 19.20KHz
OFF ON ON 16.00KHz
OFF ON OFF 12.00KHz
OFF OFF ON 9.60KHz
OFF OFF OFF 8.00KHz
2.12.1 Analog Input/Output

The DSP56858EVM uses jacks for line-level stereo input, line-level stereo output and
stereo headphone output. A National Semiconductor LM4880 provides the drive required
for the use of headphones. This device offers a THD, which is superior by a factor of two
to the CS4218’s on-chip headphone drive circuitry. The basic Analog codec connections
are shown in Figure 2-11.

CS4218
P4 P5
RIN1 LOUTL
Line-Level Line-Level
Input LIN1 LOUTR Output
A A
LM4880 P6
Headphone
Output
Figure 2-11. CODEC Analog Connections

2.12.2 Digital Interface

The serial interface of the codec transfers digital audio data and control data into and out
of the device. The ESSI port consists of independent transmitter and receiver sections and
is used for serial communication with the codec.
On the DSP side, the Serial Transmit Data pin, STD0, is an output when data is being
transmitted to the codec. The Serial Receive Data pin, SRD0, is an input when data is
being received from the codec. These two pins are connected to the codec’s Serial Data
Input, SDIN, and Serial Data Output, SDOUT, pins.
The DSP’s Transmit Serial Clock pin, SCK0, provides the serial bit rate clock for the ESSI
interface. It is connected to the CODEC’s Serial Port Clock pin, SCLK. Data is
transmitted on the rising edge of SCLK and is received on the falling edge of SCLK.
The DSP’s GPIO PORT C Bit 4 pin, PC4, is programmed to control the codec’s Active
Low Reset signal, RESET.
The Serial Transmit Frame Sync pin, SC02, is programmed to control the codec’s Frame
Sync signal, FSYNC. This signal is sampled by SCLK, with a rising edge indicating a new
frame is about to start. The FSYNC frequency is always the system’s sample rate. It may
be an input to the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in Figure 2-12, Table 2-9 and Table 2-10.
The codec’s MODE is set by the three MODE selection resistors, R42-R44. In the factory
default setting of MODE 4, the codec is set to be the master of the ESSI bus with its data
word set at 32 bits per frame; i.e., 16 bits Left channel and 16 bits Right channel. The
sample rate is selected on the Sample Rate Selector switch S5; see Table 2-8 for selection
options. Codec control information is sent over a separate serial port using: PC3 as the
Control Chip Select signal, CCS; PE2 as the Control Data Input signal, CDIN; and PE3 as
the Control Clock signal, CCLK.

Stereo Codec
DSP56858 CODEC Enable Logic CS4218

JG6
STD0 1 2 SDIN
SRD0 3 4 SDOUT
SCK0 5 6 SCLK
SC02 7 8 FSYNC
PC4 9 10 RESET
JG7
PC3 1 2 CCS
PE2 3 4 CDIN
PE3 5 6 CCLK
Figure 2-12. CS4218 Stereo Audio Codec
Table 2-9. ESSI Port Connector Description
JG6
Pin # DSP Signal Pin # Codec Signal
1 STD0 2 SDIN
3 SRD0 4 SDOUT
5 SCK0 6 SCLK
7 SC02 8 FSYNC
9 PC4 10 RESET
Table 2-10. GPIO Port Connector Description
JG7
Pin # DSP Signal Pin # Codec Signal
1 PC3 2 CCS
3 PE2 4 CDIN
5 PE3 6 CCLK

2.13 Daughter Card Connectors

The EVM board contains two daughter card expansion connectors. One connector, J1,
contains the DSP’s external memory bus signals. The other connector, J2, contains the
DSP’s peripheral port signals.
2.13.1 Memory Daughter Card Expansion Connector

The DSP’s external memory bus signals are connected to the Memory Daughter Card
Expansion connector, J1. Table 2-11 shows the port signal-to-pin assignments.
Table 2-11. Memory Daughter Card Connector Description
J1
1 A10 2 A11
3 A9 4 CS1
5 A8 6 A15
7 A7 8 A14
9 A20 10 A19
11 WR 12 A13
13 D0 14 A12
15 D1 16 D8
17 D2 18 D9
19 GND 20 GND
21 D3 22 D10
23 D4 24 D11
25 D5 26 D12
27 D6 28 D13
29 A18 30 A17
31 D7 32 D14
33 CS0 34 D15
35 A0 36 RD
37 A1 38 A6
39 A16 40 GND

Daughter Card Connectors
J1
41 A2 42 A5
43 A3 44 A4
45 CS3 46 CS2
47 +3.3V 48 +3.3V
49 GND 50 GND
51 +5.0V
2.13.2 Peripheral Daughter Card Expansion Connector

The DSP’s peripheral port signals are connected to the Peripheral Daughter Card
Expansion connector, J2. Table 2-12 shows the port signal-to-pin assignments.
Table 2-12. Peripheral Daughter Card Connector Description
J2
1 CS0/PA0 2 CS1/PA1
3 CLKO 4 CS2/PA2
5 TIO0/PG0 6 TIO1/PG1
7 CS3/PA3 8 RSTOUT
9 TIO2/PG2 10 TIO3/PG3
11 NC 12 NC
13 GND 14 GND
15 SRD0/PC1 16 SRD1/PD1
17 SC01/PC4 18 SC11/PD4
19 SCK/PF2 20 SCK1/PD2
21 GND 22 GND
23 MOSI/PF1 24 SC10/PD3
25 MISO/PF0 26 SC12/PD5
27 GND 28 GND
29 SS/PF3 30 STD1/PD0

Table 2-12. Peripheral Daughter Card Connector Description (Continued)
J2
31 SC00/PC3 32 MODA/PH0
33 SC02/PC5 34 MODB/PH1
35 RESET 36 MODC/PH2
37 GND 38 GND
39 STD0/PC0 40 RXD1/PE2
41 SCK0/PC2 42 TXD1/PE3
43 IRQB 44 RXD0/PE0
45 IRQA 46 TXD0/PE1
47 +3.3V 48 +3.3V
49 GND 50 GND
51 +5.0V
2.14 USB
A USB version 2.0 interface controller, NetChip NET2270, is connected to the
DSP56858’s external address/data bus via CS3. The NET2270 is clocked with a
30.00MHz crystal. This allows the NET2270 interface controller to support the USB Full
Speed (12 Mb/sec USB version 1.1) along with the USB High Speed (480 Mb/sec USB
version 2.0) bus transfer rates. The NET2270 provides a USB Tranceiver, Serial Interface
Engine, USB Protocol Controller, Endpoint FIFOs, Local Bus Interface and Configuration
Registers. Refer to the USB diagram in Figure 2-13. The USB Interface’s use of CS3 can
be disabled by removing the jumper at JG11.

USB
DSP56858 USB Interface
D0-D15 LD0-LD15 J5
A0-A4 LA0-LA4 DM 2
RD IOR DP 3
WR IOW
IRQA IRQ USB
JG11 B-TYPE
CS3 1 2 CS
Jumper Pin 1-2:
Enable USB
Jumper Removed:
Disable USB
Figure 2-13. Diagram of the USB Interface

2.15 Host Interface Connector

The DSP56858EVM board contains a Host Interface connector. The HI connector, J4,
provides the signals present on the DSP56858’s HI port. Table 2-13 shows the HI
connectors signal-to-pin assignments.
Table 2-13. Host Interface Connector Description
J4
1 HD0 2 HD1
3 HD2 4 HD3
5 HD4 6 HD5
7 HD6 8 HD7
9 HA0 10 HA1
11 HA2 12 HRW
13 HDS 14 HCS
15 HREQ 16 HACK
17 +3.3V 18 GND
19 +3.3V 20 GND
2.16 Test Points

The DSP56858EVM board has a total of seven test points. Three digital GND test points
are located in corners of the board. The +5.0VA and AGND test points are located in the
analog corner of the board. The +1.8V and +3.3V test points are located in the power
supply section of the board.

Appendix A
MOTOROLA DSP56858EVM Schematics A-1

A B C D E
A-2
U1
A0 10 A0 XTAL 27 XTAL
11 28 +3.3V
A1 A1 EXTAL EXTAL
A2 12 A2 CLKOUT 37 C L KO
A3 13 U 1 1A
4 A3 L E D1 4
A4 29 A4 IRQA 22 /IRQA R75
30 23 PD0 1 2
A5 A5 IRQB /IRQB STD1
A6 31 A6
32 1 RED LED 270
A7 A7 MISO/PF0 MISO
A8 48 2 MOSI M C 74AC04AD
A8
A9 49 A9
SPI MSOCSKI // PP FF 21 3 SCK
A10 50 A10 SS/PF3 4 /SS
A11 51 U 1 1B
A11 L E D2
A12 63 A12 74 TXD0 R76
64 73 PD1 3 4
A13 A13
SCI0 RT XX DD 00 // PP EE 01 RXD0 SRD1
A14 65 A14
66 108 YELLOW LED 270
A15 A15 TXD1
A16 75 107 RXD1 M C 74AC04AD
A16
SCI1 RT XX DD 11 // PP EE 23
A17 76 A17
A18 77 A18 STD0/PC0 131 STD0
A19 78 132 SRD0 U11C
A19 SRD0/PC1 L E D3
A20 79 A20 133 S C K0 R77
134 PD2 5 6
ESSI0 SSCCK0 00 // PP CC 23 S C 00 SCK1
D0 81 D0 SC01/PC4 135 S C 01
94 136 GREEN LED 270
D1 D1 SC02/PC5 S C 02
D2 95 M C 74AC04AD
D2
D3 96 D3 STD1/PD0 99 STD1
D4 97 D4 SRD1/PD1 100 SRD1
3 D5 98 101 S C K1 U11D 3
D5 SCK1/PD2 L E D4
D6 120 D6
ESSI1 SC10/PD3 102 S C 10 R78
121 103 PD3 9 8
D7 D7 SC11/PD4 S C 11 SC10
D8 122 D8 SC12/PD5 104 S C 12
123 RED LED 270
D9 D9
D10 124 114 TIO0 M C 74AC04AD
D10 TIO0/PG0
D11 137 D11 112 TIO1
D12 138 D12
TIMER TIO1/PG1
TIO2/PG2 111 TIO2
D13 142 110 TIO3 U 1 1E
D13 TIO3/PG3 L E D5
D14 143 D14 R79
144 90 PD4 11 10
D15 D15 HA0/PB8 HA0 SC11
HA1/PB9 91 HA1
8 92 YELLOW LED 270
/RD RD HA2/PB10 HA2
/WR 9 M C 74AC04AD
WR
HD0/PB0 33 HD0
/CS0 83 CS0/PA0 HD1/PB1 34 HD1
/CS1 84 35 HD2 U11F
CS1/PA1 HD2/PB2 L E D6
/CS2 85 CS2/PA2 HD3/PB3 40 HD3 R80
86 HOST 41 PD5 13 12
/CS3 CS3/PA3 HD4/PB4 HD4 SC12
HD5/PB5 42 HD5
17 43 GREEN LED 270
MODA MODA/PH0 HD6/PB6 HD6
MODB 18 44 HD7 M C 74AC04AD
MODB/PH1 HD7/PB7
M O DC 19 MODC/PH2
HRW/HRD/PB11 93 HRW
2 116 /HDS 2
HDS/HWR/PB12
TDI 58 TDI HCS/PB13 117 /HCS
TDO 57 TDO HREQ/HTRQ/PB14 118 /HREQ
TCK 60 TCK HACK/HRRQ/PB15 119 /HACK
/TRST 56 TRST
TMS 59 TMS RESET 39 /RESET
DSP56858EVM User’s Manual

/DE 55 DE RSTOUT 38 /RSTOUT
+1.8V 14 VDDC1 VSSC1 16

52 VDDC2 VSSC2 54
87 VDDC3 VSSC3 89
125 VDDC4 VSSC4 127
+3.3V 5 VDD1 VSS1 7

20 VDD2 VSS2 21
45 47

VDD3 VSS3
61 VDD4 VSS4 62
68 VDD5 VSS5 70
80 82
VDD6 VSS6
105 VDD7 VSS7 106 DSP Standard Products Division
113 VDD8 VSS8 115
129 VDD9 VSS9 130 2100 East Elliot Road
139 VDD10 VSS10 141
Tempe, Arizona 85284
1 24 26 1
+3.3V VDDA VSSA
(480) 413-5090 FAX: (480) 413-2510
D S P 56858FV80
Title DSP56858 Processor and DEBUG LEDS
Document Rev.
Size Number DSP56858EVM.DSN
B 1.2
Date: Thursday, January 10, 2002 Designer: DSPD Design Sheet 1 of 11
A B C D E
Figure A-1. DSP56858 Processor and DEBUG LEDS
MOTOROLA
A B C D E
+3.3V
JG3
3
MOTOROLA
R66
Vcc/2 2 EXTAL 10K
4 1
IRQA PUSHBUTTON 4
S2
Y1 R8
4.00MHz 10M /IRQA
OSC BYPASS
C23
JG4 0.1uF
+3.3V
1
2 XTAL
12.288MHZ 3 +3.3V
R91
10K
R67
+3.3V IRQB PUSHBUTTON 10K
Vcc/2
S3
3 3
/IRQB
R92 R68
10K 10K
DNP C24
S1 0.1uF
/POR
RESET PUSHBUTTON
C25
0.1uF +3.3V
S4 R69
MODA
1 2 MODA 470K
3 4 MODB
5 6 MODC
R70
MODB
+3.3V R71 R72 R73 Boot MODE
2 470K 2
10K 10K 10K
U20 Select
2
Vcc R74
1 /POR MODC
RST
3 GND 470K
DS1818
DSP Standard Products Division

2100 East Elliot Road

3 (480) 413-5090 FAX: (480) 413-2510
1 DS1818 1
Title RESET, CLOCK, BOOT MODE & IRQS
1 2
Document Rev.
A 1.2
Date: Thursday, January 10, 2002 Designer: D S P D D e s i g n Sheet 2 of 11
A B C D E
Figure A-2. RESET, CLOCK, BOOT MODE & IRQs
A-3
A B C D E
A-4
128Kx16-bit Program Memory (CS0) 128Kx16-bit Data Memory (CS1/CS2)
U2 U3
5 7 A0 5 7 D0
A0 A0 DQ1 D0 A0 DQ1
4 8 A1 4 8 D1
A1 A1 DQ2 D1 A1 DQ2
3 9 A2 3 9 D2
4 A2 A2 DQ3 D2 A2 DQ3 4
2 10 A3 2 10 D3
A3 A3 DQ4 D3 A3 DQ4
1 13 A4 1 13 D4
A4 A4 DQ5 D4 A4 DQ5
44 14 A5 44 14 D5
A5 A5 DQ6 D5 A5 DQ6
43 15 A6 43 15 D6
A6 A6 DQ7 D6 A6 DQ7
42 16 A7 42 16 D7
A7 A7 DQ8 D7 A7 DQ8
27 29 A8 27 29 D8
A8 A8 DQ9 D8 A8 DQ9
26 30 A9 26 30 D9
+3.3V A9 A9 DQ10 D9 A9 DQ10
25 31 A10 25 31 D10
A10 A10 DQ11 D10 A10 DQ11
24 32 A11 24 32 D11
A11 A11 DQ12 D11 A11 DQ12
21 35 A12 21 35 D12
A12 A12 DQ13 D12 A12 DQ13
20 36 A13 20 36 D13
A13 A13 DQ14 D13 A13 DQ14
R60 19 37 A14 19 37 D14
A14 A14 DQ15 D14 A14 DQ15
10K 18 38 A15 18 38 D15
A15 A15 DQ16 D15 A15 DQ16
22 A16 22
A16 A16 A16
VDD 11 +3.3V VDD 11 +3.3V
JG1 41 33 /RD 41 33
/RD OE VDD OE VDD
17 /WR 17
/CS0 1 /WR WE WE
3 /ECS0 6 JG2 6 3
2 CE CE
39 LB VSS 12 /CS1 1 2
/ E C S 1 39
LB VSS 12
40 UB VSS 34 /CS2 3 4
/ E C S 2 40
UB VSS 34
GS72116ATP-7 R61 GS72116ATP-7

R62 R63 1K
1K 1K
+3.3V
CS1/CS2 ENABLE JUMPER
CS0 ENABLE JUMPER R64 OPTION JG2
/ECS1
2 OPTION JG1 10K SRAM WORD ENABLE 1-2 3-4 2
SRAM ENABLE 1-2 SRAM UPPER BYTE ENABLE NC 3-4

R65
/ECS2

SRAM LOWER BYTE ENABLE 1-2 NC
10K
SRAM DISABLE NC SRAM DISABLE NC NC


(480) 413-5090 FAX: (480) 413-2510
1 1
Title P R O G RAM [WORD] (CS0) and DATA [BYTE] (CS1/CS2) SRAM MEMORY
Document Rev.
A 1.2
Date: Sunday, October 06, 2002 Designer: DSPD Design Sheet 3 of 11
A B C D E
Figure A-3. Program [Word] (CS0) & Data [Byte] (CS1/CS2) SRAM Memory
MOTOROLA
A B C D E
MOTOROLA
4 4
+3.3V
U4
J4 JG10
/EE_CS 4 6
HD0 1 2 HD1 /SS 1 2 CS VCC
HD2 3 4 HD3
EE_SO 8 3 /RST
HD4 5 6 HD5 MISO 3 4 SO RESET
HD6 7 8 HD7
EE_SI 1 5 /WP
HA0 9 10 HA1 MOSI 5 6 SI WP
HA2 11 12 HRW
EE_SCK 2 7
/HDS 13 14 /HCS SCK 7 8 SCK GND
/HREQ 15 16 /HACK
17 18 AT45DB011B-SC
+3.3V 19 20
EEPROM Enable
HOST PORT
3 3
+3.3V +3.3V
R53 10K R54 10K

HRW /RST
R55 10K R56 10K

/HDS /WP
R57 10K
/HCS
2 2
R58 10K
/HREQ
R59 10K
/HACK


(480) 413-5090 FAX: (480) 413-2510
1 1
Title HOST Port and SPI Serial 1M EEPROM MEMORY
Document Rev.
A 1.2
A B C D E
Figure A-4. HOST Port and SPI Serial 1M-bit Serial EEPROM Memory
A-5
A B C D E
A-6
+3.3V
U5
4 4
28 C1+ VCC 26
C19 3 C20
1.0 uF V- 1.0 uF
24 C1-
1 C2+
27 C21
C22 V+ 1.0 uF
1.0 uF 2 25
C2- GND P3
1 DCD
JG8 6 DSR
TX 14 9 2 TXD
TXD0 1 2 T1IN T1OUT
RX T2IN 13 10 7 CTS
RXD0 3 4 T2IN T2OUT 1 T1
T3IN 12 11 3 RXD
T3IN T3OUT 1 T2
8 RTS
T3 1 20 R2OUTB 4 DTR
19 R1OUT R1IN 4 9 RI
3 T4 18 5 R2IN 5 GND +3.3V 3
1 R2OUT R2IN R3IN
T5 1 17 R3OUT R3IN 6 R45
T6 16 7 R4IN /EN 1K
+3.3V 1 R4OUT R4IN R5IN
T7 1 15 R5OUT R5IN 8 SCI
/EN T2IN R46 1K
23 FORCEON RS-232
INVALID 21 1 T8
R47 22
RS-232 ENABLE 1K FORCEOFF CONNECTOR T3IN R48 1K
MAX3245EEAI
RS-232 ENABLE N/C JG9
R49
R2IN 1K
1
2
RS-232 DISABLE 1 - 2 R50
R3IN 1K
R4IN R51 1K
2 2
R5IN R52 1K


(480) 413-5090 FAX: (480) 413-2510
1 1
Title SCI PORT, RS-232 AND CONNECTOR
Document Rev.
A 1.2
A B C D E
Figure A-5. SCI PORT, RS-232 and Connector
MOTOROLA
A B C D E
R19 C1 +3.3V
0.33uF
5.62K
1% R21
R20 /PDN
5.62K C2
P4 470pF 10K
1%
3 RING_IN
R22
MOTOROLA
11 U6 MODE1
10 C3 P5 10K
4 TIP_IN ROUT 1uF RING_OUT 4
2 19 RIN1 ROUT 9 3
1 R23 25V 11
5.62K C4 MODE2 R24
470pF 10
1/8" 1% 10 L O UT C5 TIP_OUT 2
LOUT 1uF 10K
Line-Input 1
R25 C6 25V
21 LIN1 Line Out R26
Stereo Jack 0.33uF MODE3
5.62K Stereo Jack
32 MF5 C7 R27 R28
1% MF5 C8 10K
C9 30 /CCS 0.0022uF 3 9 .2K 39.2K 1/8"
MF4 0.0022uF
0.47uF 20 29 CCLK 1% 1%
RIN2 MF3 CDIN MF6 R29
MF2 33
34 MF1
C10 MF1 10K
0.47uF 22 LIN2 MF6 MF7 R30
WF6 28
25 MF7
C11 WF7 MF8 10K
WF8 24
0.47uF 14
+ 3 .3V REFBUF MF8 R31
U7 35 MODE3
12.288MHZ SWODE3 10K
4 26 MODE2
VCC SWODE2 MODE1
R32 R33 SWODE1 23 R34
1 3 1 2 .288MHZ 41 /CCS
+3.3V EN OUT CLKIN
3
/ C O D E C _ R E SET 40 15 3
1K 1K RESET REFBY 10K
2 /PDN 7
GND CODEC_FSYNC PDN C13 + C12
39 SSYNC R35
1 2 . 2 8 8 M HZ OSC C O D E C _ S C LK 38 0.1uF 4 7 uF MF5
C O D E C _ S D O UT SCLK 10VDC
37 SDOUT 10K
CODEC_SDIN 36 16
SDIN REFGND
+5.0VA 18 VDDA VDD 42 +3.3V

17 43 R37 SHUTDN R36
GNDA GND
10K
C S 4218-KQ 2 0 .0K 1%
MF1 R38
10K
R39
JG6
CODEC_SDIN 2 0 .0K 1%
S T D0 1 2 C O D E C _ S D O UT
SRD0 3 4 C O D E C _ S C LK U8
SCK0 5 6 C14
CODEC_FSYNC P6
SC02 7 8 R40
+
PC4 / C O D E C _ R E SET ROUT 6 7 RING_PHN 3

SC01 9 10 IN_B OUT_B
11
1uF 20.0K C15
2 10 2
25V 1% 4 7 uF TIP_PHN 2
10VDC 1
JG7 S5 C16 R41 Headphone Out
+
PC3 /CCS MF6 6 5 LOUT 2 1

SC00 1 2 IN_A OUT_A Stereo Jack
PE2 CDIN MF7 4 3
R X D1 3 4
PE3 CCLK MF8 2 1 1uF 20.0K C17 1/8"
TXD1 5 6 25V 1% BYPASS 3 8 4 7 uF
BYPASS VDD +5.0VA
Sample Select 10VDC
C18 SHUTDN 5 4
1uF SHUTDN GND
MF6 MF7 MF8 FS (KHZ) 25V
LM4880M
SERIAL MODE 4 SELECTED 0 0 0 48.00
MASTER, 32BITS PER FRAME

R42 0 0 1 32.00
M O D E1
0 Ohm 0 1 0 24.00
0 1 1 19.20
R43 M O D E2
0 Ohm 1 0 0 16.00
1 1 0 1 12.00 1
R44 M O D E3
DNP
(480) 413-5090 FAX: (480) 413-2510
0 Ohm 1 1 0 9.60
1 1 1 8.00 Title SSI 16-BIT STEREO CODEC
CODEC Mode Select
Document Rev.
NOTE: DNP - Do Not Populate B 1.2
A B C D E
Figure A-6. SSI 16-Bit Stereo Codec
A-7
A B C D E
A-8
Parallel JTAG Interface
4 4
R1
P O R T _ I DENT
270
P1
R2
1
14 U9
270
2 P O RT_RESET 2 18 P_RESET
1A1 1Y1
15 R3
3 PORT_TMS 4 16 TMS
1A2 1Y2
16 270
4 P O RT_TCK 6 14 TCK
1A3 1Y3
17 R4
5 P O R T _ TDI 8 12 TDI
1A4 1Y4
18 270
6 / P O RT_TRST 11 9 /J_TRST
2A1 2Y1
19 R5
7 T11 7 13 P_DE
P O R T _DE 1 2Y2 2A2
20 270
8 5 15 TDO
2Y3 2A3
21
9 P O R T _ VCC 3 2Y4 2A4 17 +3.3V
3 22 3
10 + 3 .3V +3.3V
23 R7
11 P O RT_TDO 20 VCC
24 51 Oh m 1 1G R11
12 19 10 TDO
2G GND
25 R9 47K
P O R T _ C O N NECT
2
1
13
JG5 R10 MC74LCX244D W R16
51 Oh m
5.1K /DE
DB25M
5.1K
On-Board
Host Target Interface
R6
Disable P _ DE
5.1K
R12
/J_TRST
+3.3V 47K
R13
2 5.1K 2
U10A U 1 0B
/ J _ R E SET / J _ R E SET 1 4 J3
3 6 /J_TRST
/RESET /DE 13 14
/POR 2 5 + 3 .3V 11 12
R14 / J _ R E SET
9 10 TMS
P_RESET Q1

7 4 AC00 7 4 AC00 KEY
2N2222A 7 8
5.1K TCK 5 6
U10C U10D
R15 TDO 3 4
9 12 TDI 1 2
47K
8 11 /TRST
/J_TRST 10 13 JTAG Connector
7 4 AC00 7 4 AC00


C 2100 East Elliot Road
1 1
2N2222A (480) 413-5090 FAX: (480) 413-2510
Title PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR

B E
Document Rev.
B 1.2
A B C D E
Figure A-7. Parallel JTAG Host Target Interface and JTAG Connector
MOTOROLA
A B C D E
MOTOROLA
4 4
J1 J2
PA0 PA1
A10 1 2 /DS A11 /CS0 1 2 PA2 /CS1
A9 3 4 /CS1 CLKO PG0 3 4 PG1 /CS2
A8 5 6 A15 TIO0 PA3 5 6 TIO1
A7 GND 7 8 GND A14 /CS3 PG2 7 8 PG3 /RSTOUT
A20 9 10 A19 TIO2 9 10 TIO3
/WR 11 12 A13 11 12
GND GND
D0 13 14 A12 PC1 13 14 PD1
D1 15 16 D8 SRD0 PC4 15 16 PD4 SRD1
D2 17 18 D9 SC01 PF2 17 18 PD2 SC11
GND GND
19 20 SCK 19 20 SCK1
GND GND
D3 21 22 D10 PF1 21 22 PD3
D4 23 24 D11 MOSI PF0 23 24 PD5 SC10
D5 25 26 D12 MISO 25 26 SC12
GND GND
D6 GND 27 28 GND D13 PF3 27 28 PD0
3 3
A18 29 30 A17 /SS PC3 29 30 PH0 STD1
D7 /PS 31 32 D14 SC00 PC5 31 32 PH1 MODA
/CS0 33 34 D15 SC02 33 34 PH2 MODB
A0 35 36 /RD /RESET 35 36 MODC
GND GND
A1 GND 37 38 A6 PC0 37 38 PE2
GND
A16 39 40 STD0 PC2 39 40 PE3 RXD1
A2 41 42 A5 SCK0 41 42 PE0 TXD1
A3 GND 43 44 GND A4 /IRQB 43 44 PE1 RXD0
/CS3 45 46 /CS2 /IRQA 45 46 TXD0
+3.3V 47 48 +3.3V +3.3V 47 48 +3.3V
GND GND GND GND
49 50 49 50
+5.0V 51 +5.0V 51
Daughter Address/Data Connector Daughter Peripheral Port Connector
2 2
GND


(480) 413-5090 FAX: (480) 413-2510
1 1
Title D A U G H T E R CARD EXPANSION CONNECTORS
Document Rev.
A 1.2
A B C D E
Figure A-8. Daughter Card Expansion Connectors
A-9
A B C D E
A-10
U15
R84
14 59 RSDM J5
D0 LD0 RSDM USBCGND
D1 15 LD1 35.7 1% S-L
16 USBVCC
4 D2 LD2 1 4
18 58 DM
D3 LD3 DM 2
20 56 DP
D4 LD4 DP 3
21 USBLGND
D5 LD5 4
22 R85 USBCGND
D6 LD6 S-R
23 55 RSDP
D7 LD7 RSDP
D8 25 LD8 35.7 1%
USB B-TYPE
D9 26 LD9 R86
27 53 RPU L5 L6 R87 C60
D10 LD10 RPU
28 FERRITE BEAD FERRITE BEAD 1M 0.01uF
D11 LD11 1.5K
D12 30 LD12
42 OHM 42 OHM
D13 31 LD13
33 48 VBUS
D14 LD14 VBUS
D15 34 LD15 T9
1
8 R88
A0 LA0 C61
7 11 CLKIN 47K
A1 LA1 XIN
A2 6 LA2 1 2 pF
5 Y2
A3 LA3
4 30.00MHz
A4 LA4 C62
12 C L K O UT
J G 11 XOUT
/RD 44 IOR 1 2 pF
45 35 C L O C K _OUT
/CS3 1 /WR IOW LCLKO 1 T10
/ECS3 46
2 CS
3 IRQ 47 /IRQA 3
USB SELECT / R E S ET 43 RESET
DACK 38
37 DREQ EOT 39
ALE 40
RREF 49 1
RREF TEST1
TEST2 2
TEST3 64
+3.3VD 36 DMARD
13 DMAWR
VSS1 54
+3.3VD 3 60
SMC VSS2
VSS3 63
VSSIO1 19
R90 +3.3VD 57 VDD VSSIO2 24
/ECS3 17 29
VDDIO1 VSSIO3
10K 32 VDDIO2 VSSC1 9
10 VDDC1 VSSC2 41
42 VDDC2 PVSS 61
62 PVDD AVSS1 50
R89 +3.3VA 51 AVDD AVSS2 52
RREF
9.09K 1%
NET2270
2 2
L7
+3.3V +3.3VD
+3.3VD
FERRITE BEAD
C64 + C63
0.01uF 4 7 uF C65 C66 C67 C68

10VDC 0.01uF 0.01uF 0.1uF 0.1uF
DIGITAL GND
L8
+3.3V +3.3VA Tempe, Arizona 85284
1 1
+3.3VA
FERRITE BEAD (480) 413-5090 FAX: (480) 413-2510
C70 + C69
0.01uF 4 7 uF C71 C72
10VDC 0.01uF 0.1uF Title USB 2.0 Controller Interface
GND L9
AGND Document
FERRITE BEAD Rev.
ANALOG GND
B 1.2
A B C D E
Figure A-9. USB 2.0 Controller Interface
MOTOROLA
A B C D E
EXTERNAL POWER INPUT

7-12VDC/AC D1 D2
P2
MOTOROLA
2 1 FM4001 FM4001
3
4 4
D4
3
U12 +5.0V U13
2 - + 1 3 2 3 2 VCC
VIN VOUT VIN VOUT L1
+ C53 1 4 C54 1 4
GND VOUT GND VOUT +3.3V
470uF 0.1uF
FERRITE BEAD +
16VDC C55
4
MC33269DT-5 MC33269DT-3.3 47uF
10VDC
D3
3 TB1 FM4001 3
+5VDC + 1 +5.0V
INPUT - 2 U14
3 VIN VOUT 2
L2
C56 1 4
GND VOUT +1.8V
0.1uF
FERRITE BEAD + C57
L3 MC33269DT-ADJ R81 47uF
243 10VDC
+5.0V +5.0VA
1%
FERRITE BEAD
Rhigh
C58
0.1uF
L4 C59 + R82 Vout = 1.25( 1 + (Rlow/Rhigh))

2 2
47uF 107
FERRITE BEAD 10VDC 1% Rlow = 107 1% for 1.8V
Rlow Rlow = 243 1% for 2.5V
Rlow = 127 1% for 1.9V
+3.3V
5.0V, 3.3V
& Adj DSP Standard Products Division

R83 REGULATOR
270 2100 East Elliot Road

4
(480) 413-5090 FAX: (480) 413-2510
LED7
1 1
1 2 3 Title P O W ER SUPPLIES
Document Rev.
Size Number DSP56F858EVM.DSN
POWER GOOD LED
MC33269 1.2
A Date: Thursday, January 10, 2002 Designer: D S P D D e s i g n Sheet 1 0 of 11
A B C D E
Figure A-10. POWER SUPPLIES
A-11
A B C D E
A-12
DSP56858
+3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V
C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37
4 4
0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF
Near VDDA
GS72116 GS72116 AT45DB011 74AC04 74AC00 DS1818 MAX3245 74LCX244 Host Port
+3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V
C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48
3 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF 0.1uF 0.1uF 3
CS4218 OSC LM4880

+5.0VA ANALOG GROUND GROUND +3.3V +1.8V
TEST POINT TEST POINT
+3.3V +3.3V +3.3V +5.0VA
TP1 DNP
1
1
1
1
TP3
1
C49 C50 C51 C52
0.01uF 0.1uF 0.01uF 0.1uF TP6
TP2 1 TP4 TP5
2 2
+3.3V +1.8V
+5.0VA TP7 TEST POINT TEST POINT
1
TEST POINT

(480) 413-5090 FAX: (480) 413-2510

1 1
Title BYPASS CAPS
Document Rev.
Size Number D S P 5 6 8 58EVM.DSN
A 1.2
Date: Thursday, January 10, 2002 Designer: D S P D D e s i g n Sheet 1 1 of 11
A B C D E
Figure A-11. POWER SUPPLIES
MOTOROLA
Appendix B
DSP56858EVM Bill of Material
Qty Description Ref. Designators Vendor Part #
Integrated Circuits
1 DSP56858 U1 Motorola, DSP56858FV120
2 GS72116 U2, U3 GSI, GS72116ATP-7
1 AT45DB011 U4 Atmel, AT45DB011B-SC
1 MAX3245 U5 Maxim, MAX3245EEAI
1 CS4218 U6 Crystal Semiconductor, CS4218-KQ
1 12.288MHz OSC U7 Epson, SG-531P-12.288MC
1 LM4880 U8 National Semiconductor, LM4880M
1 74LCX244 U9 ON Semiconductor, MC74LCX244ADW
1 74AC00 U10 Fairchild, 74AC00SC
1 74AC04 U11 ON Semiconductor, MC74AC04AD
1 +5.0V Voltage Regulator U12 ON Semiconductor, MC33269DT-5
1 +3.3V Voltage Regulator U13 ON Semiconductor, MC33269DT-3.3
1 +1.8V Voltage Regulator U14 ON Semiconductor, MC33269DT-ADJ
1 NET2270 U15 NetChip, NET2270
1 DS1818 U20 Dallas Semiconductor, DS1818
Resistors
12 270 Ω R1 - R5, R75 - R80, R83 SMEC, RC73L2A270OHMJT
5 5.1K Ω R6, R10, R13, R14, R16 SMEC, RC73L2A5.1KOHMJT
2 51 Ω R7, R9 SMEC, RC73L2A51OHMJT
1 10M Ω R8 SMEC, RC73L2A10MOHMJT
4 47K Ω R11, R12, R15, R88 SMEC, RC73L2A47KOHMJT
MOTOROLA DSP56858EVM Bill of Material B-1

4 5.62K Ω, 1% R19, R20, R23, R25 SMEC, RC73L2A5.62KOHMFT
29 10K Ω R21, R22, R24, R26, R29-R31, SMEC, RC73L2A10KOHMJT

R34-R36, R38, R53-R60,
R64-R67, R71-R73, R90-R92
2 39.2K Ω, 1% R27, R28 SMEC, RC73L2A39.2KOHMFT
13 1K Ω R32, R33, R45-R52, R61-R63 SMEC, RC73L2A1KOHMJT
4 20.0K Ω, 1% R37, R39-R41 SMEC, RC73L2A20.0KOHMFT
2 0Ω R42, R43 SMEC, RC73JP2A

0 0Ω R44 SMEC, RC73JP2A
0 10K Ω R68 SMEC, RC73L2A10KOHMJT
3 470K Ω R69, R70, R74 SMEC, RC73L2A470KOHMJT
1 243 Ω, 1% R81 SMEC, RC73L2A243OHMFT
1 107 Ω, 1% R82 SMEC, RC73L2A107OHMFT
2 35.7 Ω, 1% R84, R85 SMEC, RC73L2A35.7OHMFT
1 1.5K Ω R86 SMEC, RC73L2A1.5KOHMJT
1 1M Ω R87 SMEC, RC73L2A1MOHMJT
1 9.09K Ω, 1% R89 SMEC, RC73L2A9.09KOHMFT
Inductors
4 1.0mH FERRITE BEAD L1 - L4 Panasonic, EXC-ELSA35V
5 FERRITE BEAD L5 - L9 TOKO, FLSM2520-1R0J
LEDs
2 Red LED LED1, LED4 Hewlett-Packard, HSMS-C650
2 Yellow LED LED2, LED5 Hewlett-Packard, HSMY-C650
3 Green LED LED3, LED6, LED7 Hewlett-Packard, HSMG-C650
Diode
1 S2B-FM401 D1 Vishay, DL4001DICT
1 +50V 1A BRIDGE RECT D2 DIODES, DF02S
B-2 DSP56858EVM User’s Manual MOTOROLA

Capacitors
2 0.33µF C1, C6 SMEC, MCCE334K3NR-T1
2 470pF C2, C4 SMEC, MCCE471J2NO-T1
9 1.0µF, +25V DC C3, C5, C14, C16, C18-C22 SMEC, MCCE105K3NR-T1
2 0.0022µF C7, C8 SMEC, MCCE222K2NR-T1
3 0.47µF C9-C11 SMEC, MCCE474K3NR-T1

8 47µF, +16V DC C12, C15, C17, C55, C57, C59, ELMA, RV2-16V470M-R
C63, C69
25 0.1µF C13, C23-C25, C27, C29, C31, SMEC, MCCE104K2NR-T1

C33, C35, C37, C39, C41, C43,
C44, C46-C48, C50, C52, C54,
C56, C58, C67, C68, C72
18 0.01µF C26, C28, C30, C32, C34, C36, SMEC, MCCE103K2NR-T1

C38, C40, C42, C45, C49, C51,
C60, C64-C66, C70, C71
1 470µF, +16V DC C53 ELMA, RV-16V471MH10R
2 15pF C61, C62 SMEC, MCCE150J2NO-T1
Jumpers
4 1 × 2, 2mm Header JG1, JG5, JG9, JG11 SAMTEC, TMM-102-02-S-S
2 2 x 2, 2mm Header JG2, JG8 SAMTEC, TMM-102-02-S-D
2 3 × 1, 2mm Header JG3, JG4 SAMTEC, TMM-103-02-S-S
1 5 x 2, 2mm Header JG6 SAMTEC, TMM-105-02-S-D
1 3 x 2, 2mm Header JG7 SAMTEC, TMM-103-02-S-D
1 4 × 2, 2mm Header JG10 SAMTEC, TMM-104-02-S-D
Test Points
4 Black Test Point TP1, TP3, TP6, TP7 Keystone, 5001
1 Red Test Point TP2 Keystone, 5000
1 White Test Point TP4 Keystone, 5002
1 Yellow Test Point TP5 Keystone, 5004
MOTOROLA DSP56858EVM Bill of Material B-3

Crystals
1 4.00MHz Crystal Y1 CTS, ATS04ASM-T
1 30.00MHz Crystal Y2 Epson, MA-306 30.000M-C2
Connectors
1 DB25M Connector P1 AMPHENOL, 617-C025P-AJ121
1 2.1mm coax P2 Switchcraft, RAPC-722

Power Connector
1 DE9S Connector P3 AMPHENOL, 617-C009S-AJ120

3 1/8” Stereo Jack P4 - P6 Switchcraft, 35RAPC4BHN2
2 51-Pin HD Connector J1, J2 BERG, 91930-21151
1 7 x 2 Bergstick J3 SAMTEC, TSW-107-07-S-D
1 10 x 2 RT Bergstick J4 SAMTEC, TSW-110-07-S-D-RT
1 Type B USB J5 Mill-Max, 897-30-004-90-000000
1 2-Pin Terminal Block TB1 On-Shore Technology, ED500/2DS
Switches
3 SPST Pushbutton S1 - S3 Panasonic, EVQ-PAD05R
2 3-Position DIP SW S4, S5 CTS, 209-3LPST
Transistors
1 2N2222A Q1 ZETEX, FMMT2222ACT
Miscellaneous
20 2mm Shunt SH1 - SH20 Samtec, 2SN-BK-G
4 Rubber Feet RF1 - RF4 3M, SJ5018BLKC
B-4 DSP56858EVM User’s Manual MOTOROLA

Index
C ESSI ix
EVM ix
Clock Source 2-7
Codec viii F
Connectors
Host Interface 2-22 FSRAM 2-3
D G
Daughter Card Connectors 2-18 GPIO ix

Daughter Card Expansion interface 2-1
Debugging 2-8
H
DIP viii
HI viii, ix
DSP viii
Host Parallel Interface Connector 2-9
DSP56858EVM
Host Target Interface 2-9
+12.0V DC power supply 2-14
1 M-bit Serial EEPROM/Data FLASH 2-1 I
128Kx16-bit of memory 2-1
16-bit +1.8V/+3.3V Digital Signal Processor 2-1 IC ix
16-bit stereo codec interface 2-1
4.00MHz crystal oscillator 2-1 J
Codec sample rate selector 2-1
connecting to the PC 1-4 JTAG ix, 1-1, 2-1
default jumper options 1-3 connector 2-10
Development Card 2-1 Jumper Group
external oscillator frequency input 2-1 JG1 1-3
FSRAM 2-1 JG10 1-3
GPIO compatible peripheral 2-2 JG11 1-3
Host Interface Connector 2-2 JG2 1-3
interconnection diagram 1-4 JG3 1-3
ISSI compatible peripheral 2-2 JG4 1-3
JTAG port interface 2-1 JG5 1-3
jumper settings 1-3 JG6 1-3
Memory Daughter Caard Expansion Connector 2-2 JG7 1-3
On-board power regulation 2-2 JG8 1-3
Parallel JTAG Host Target Interface 2-1 JG9 1-3
power connection cable connection 1-4 Jumper Options 1-3
real-time debugging 2-8 jumper settings 1-3
RS-232 interface 2-1
SCI compatible peripheral 2-2 L
SPI compatible peripheral 2-2
test points 2-22 LED ix
USB interface 2-2 LQFP ix
E M
EEPROM viii MPIO ix
EOnCE ix
MOTOROLA Index 1
O
Operating Mode 2-7
P
PCB ix
PLL ix
power supply, external 1-4
R
RAM ix
ROM ix
RS-232
interface 2-1, 2-6

level converter 2-6
schematic diagram 2-6
RS-232 Serial Communications 2-6
S
SCI ix
SPI ix
SRAM ix
external data 2-1
external program 2-1
SSI ix
stereo 16-bit codec interface 2-1
Stereo headphone interface 2-1
T
THD x
U
USB x, 2-20
schematic diagram 2-20
W
WS x
2 DSP56858EVM User’s Manual MOTOROLA




Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. Motorola,
Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their
respective owners. © Motorola, Inc. 2002.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334
Technical Information Center: 1–800–521–6274

HOME PAGE: http://www.motorola.com/semiconductors/
DSP56858EVMUM/D

DSP56858 Evaluation Module User's Manual: Order This Document by DSP56858EVMUM/D Rev. 2.0, 10/07/2002

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DSP56858 Evaluation Module User's Manual: Order This Document by DSP56858EVMUM/D Rev. 2.0, 10/07/2002

Uploaded by

Copyright:

Available Formats

Freescale Semiconductor, Inc.

Order this document by

DSP56858 Evaluation Module

© Motorola, Inc., 2002. All rights reserved.

For More Information On This Product,

For More Information On This Product,

1.3 DSP56858EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

MOTOROLA Table of Contents i

ii DSP56858EVM User’s Manual MOTOROLA

1-1 Block Diagram of the DSP56858EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

2-3 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

MOTOROLA List of Figures iii

iv DSP56858EVM User’s Manual MOTOROLA

1-1 DSP56858EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-5 JTAG Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

MOTOROLA List of Tables v

vi DSP56858EVM User’s Manual MOTOROLA

MOTOROLA Preface vii

Term or Value Symbol Examples Exceptions

Active High Signals No special symbol A0

Active Low Signals Noted with an WE In schematic drawings,

Hexadecimal Values Begin with a “$” sym- $0FF0

Decimal Values No special symbol 10

Binary Values Begin with the letter b1010

Numbers Considered positive 5 Voltage is often shown as

Blue Text Linkable on-line ...refer to Chapter 7,

Bold Reference sources, ...see:

Definitions, Acronyms, and Abbreviations

Codec COder/DECoder; a part used to convert analog signals to digital (coder)

viii DSP56858EVM User’s Manual MOTOROLA

and can only be set as an input, output or level-sensitive interrupt input

THD Total Harmonic Distortion

[2] DSP5685x 16-Bit Digital Signal Processor User’s Manual,

x DSP56858EVM User’s Manual MOTOROLA

The DSP56858EVM is designed for the following purposes:

1.1 DSP56858EVM Architecture

MOTOROLA Introduction 1-1

RESET SPI Data FLASH

IRQ IRQ Interface

MODE RS-232 DSub

Amp Headphone Jack

4.00MHz +1.8V, +3.3V Power Supply

Figure 1-1. Block Diagram of the DSP56858EVM

1.2 DSP56858EVM Configuration Jumpers

1-2 DSP56858EVM User’s Manual MOTOROLA

Figure 1-2. DSP56858EVM Jumper Reference

Table 1-1. DSP56858EVM Default Jumper Options

JG5 Enable on-board Parallel JTAG Host/Target Interface NC

JG7 Enable GPIO for CODEC control 1-2, 3-4, 5-6

JG8 Enable SCI0 Port to RS-232 transceiver 1–2, 3-4

JG9 Enable RS-232 output NC

JG11 Enable USB interface via CS3 1-2

MOTOROLA Introduction 1-3

1.3 DSP56858EVM Connections

Connect cable P2 TB1

Figure 1-3. Connecting the DSP56858EVM Cables

Perform the following steps to connect the DSP56858EVM cables:

1-4 DSP56858EVM User’s Manual MOTOROLA

• DSP56858 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]

MOTOROLA Technical Summary 2-1

• USB interface [U15and J5]

• Six on-board real-time user debugging LEDs [LED1-6]

• DSP56858 Technical Data, (DSP56858/D): Provides features list and