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Chap7 PDF
Chap7 PDF
• Introduction
• RAM structure: Cells and Chips
• Memory boards and modules
• Two-level memory hierarchy
• The cache
• Virtual memory
• The memory as a sub-system of the computer
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-2 Chapter 7- Memory System Design
Introduction
So far, we’ve treated memory as an array of words limited
in size only by the number of address bits. Life is seldom
so easy...
What other issues can you think of that will influence memory
design?
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-3 Chapter 7- Memory System Design
–more–
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-4 Chapter 7- Memory System Design
• The memory hierarchy: from fast and expensive to slow and cheap
• Example: Registers->Cache–>Main Memory->Disk
• At first, consider just two adjacent levels in the hierarchy
• The Cache: High speed and expensive
• Kinds: Direct mapped, associative, set associative
• Virtual memory–makes the hierarchy transparent
• Translate the address from CPU’s logical address to the
physical address where the information is actually stored
• Memory management - how to move information back and
forth
• Multiprogramming - what to do while we wait
• The “TLB” helps in speeding the address translation
process
• Overall consideration of the memory as a subsystem.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-5 Chapter 7- Memory System Design
m
MAR A0 – Am –1 0
w 1
b D0 – Db –1
MDR 2
w 3
R/W
Register
file 2m – 1
REQUEST
COMPLETE
Control signals
Sequence of events:
Read:
1. CPU loads MAR, issues Read, and REQUEST
2. Main Memory transmits words to MDR
3. Main Memory asserts COMPLETE.
Write:
1. CPU loads MAR and MDR, asserts Write, and REQUEST
-more- 2. Value in MDR is written into address in MAR.
3. Main Memory asserts©COMPLETE.
Computer Systems Design and Architecture by V. Heuring and H. Jordan 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-6 Chapter 7- Memory System Design
m
MAR A0 – Am –1 0
w 1
b D0 – Db –1
MDR 2
w 3
R/W
Register
file 2m – 1
REQUEST
COMPLETE
Control signals
Additional points:
•if b<w, Main Memory must make w/b b-bit transfers.
•some CPUs allow reading and writing of word sizes <w.
Example: Intel 8088: m=20, w=16,s=b=8.
8- and 16-bit values can be read and written
•If memory is sufficiently fast, or if its response is predictable,
then COMPLETE may be omitted.
•Some systems use separate R and W lines, and omit REQUEST.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-7 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-8 Chapter 7- Memory System Design
1 AB 1 CD
0 CD 0 AB
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-9 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-10 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-11 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-12 Chapter 7- Memory System Design
Select Select
DataIn
R/ W
R/W
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-13 Chapter 7- Memory System Design
DataIn D DataOut
R/W
Select
D D D D D D D D
R/W
d0 d1 d2 d3 d4 d5 d6 d7
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-14 Chapter 7- Memory System Design
2–4
decoder D D D D D D D D
2-bit
address
A1
D D D D D D D D
A0
D D D D D D D D
D D D D D D D D
R/W
R/W is common
d0 d1 d2 d3 d4 d5 d6 d7
to all.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-15 Chapter 7- Memory System Design
Column address: 8
1 256–1 mux
A8–A15 1 1–256 demux
There is little
difference between 64 each
this chip and the
previous one, except Column address: 6
that there are 4, 64-1 4 64–1 muxes
A8–A13 4 1–64 demuxes
Multiplexers instead of
1, 256-1 Multiplexer.
R/W
4
CS
This chip requires 24 pins including power and ground, and so will require
a 24 pin pkg. Package size and pin count can dominate chip cost.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-17 Chapter 7- Memory System Design
m0 m4
m0 m4 m8 m12
m1 m5 m9 m13
m1 m5
x0
2-4 Decoder
m2 m6 m10 m14
x0 x1
m2 m6
x1 m3 m7 m11 m15
m3 m7
2-4 Decoder
x2 x2
x2 x3
Fig 7.9 A 6 Dual rail data lines for reading and writing
bi bi
Transistor +5
Active
loads
cell
Word line wi
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-19 Chapter 7- Memory System Design
Memory
address
Read/write
CS
Data
tAA
Access time from Address– the time required of the RAM array to
decode the address and provide value to the data bus.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-20 Chapter 7- Memory System Design
Memory
address
Read/write
CS
Data
tw
Write time–the time the data must be held valid in order to decode address
and store value in memory cells.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-21 Chapter 7- Memory System Design
Switch to control
Fig 7.12 A Single bit line
b
i access to cell
(DRAM) Cell t
c no charge for
a0
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-22 Chapter 7- Memory System Design
Fig 7.13
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-23 Chapter 7- Memory System Design
RA S t RA S t Prechg RA S t RA S Prec hg
CAS CAS
R/ W W
Dat a Dat a
tA t DHR
tC tC
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-24 Chapter 7- Memory System Design
•Many chips use “CAS before RAS” to signal a refresh. The chip has an
internal counter, and whenever CAS is asserted before RAS, it is a signal to
refresh the row pointed to by the counter, and to increment the counter.
•Most DRAM vendors also supply one-chip DRAM controllers that encapsulate
the refresh and other functions.
•Page mode, nibble mode, and static column mode allow rapid access to
the entire row that has been read into the column latches.
•Video RAMS, VRAMS, clock an entire row into a shift register where it can
be rapidly read out, bit by bit, for display.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-25 Chapter 7- Memory System Design
Row
Decoder
00 Address
CS
1 0 1 0
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-26 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-27 Chapter 7- Memory System Design
•Memory modules:
•Satisfy the processor–main memory interface requirements
•May have DRAM refresh capability
•May expand the total main memory capacity
•May be interleaved to provide faster access to blocks of words.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-28 Chapter 7- Memory System Design
DRAM A<11..0>
A<11..0> DQ<31..0>
DQ<23..16> DQ<7..0> RAS.L
RAS.L CAS.L
CAS.L OE.L
OE.L WE.L
WE.L
DRAM
A<11..0>
DQ<7..0>
DQ<7..0>
RAS.L
CAS.L
OE.L
WE.L
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-29 Chapter 7- Memory System Design
D<31..0>
A<1..0>
A<24..13>
A<11..0>
A<11..0>
Y
DQ<31..0>
A<12..2>
B<10..0>
RAS.L
B<11> CAS.L
OE.L
A.L/B.L
WE.L
A<31..25>
ROW.L
WRITE.H RAS.L
CAS.L
OE.L
READ.H WE.L
DONE.H DONE..H
CLK
CLK
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-30 Chapter 7- Memory System Design
CLK
D
VALID VALID
READ
WRITE
DONE
RAS.L
ROW.L
CAS.L
WE.L
OE.L
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-31 Chapter 7- Memory System Design
D<31..0>
A<1..0>
A<24..13>
A<11..0>
A<11..0>
Y
DQ<31..0>
A<12..2>
B<10..0>
RAS.L
B<11> CAS.L
OE.L
A.L/B.L
WE.L
A<31..25>
ROW.L
WRITE.H RAS.L
CAS.L
OE.L
READ.H WE.L
Refresh
Counter
DONE.H DONE..H
GRNT.H
RQST.H
CLK
CLK
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-32 Chapter 7- Memory System Design
Refresh Counter
COUNTER
CLK
RQST.H
D Q
GRANT.H
CLK
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-33 Chapter 7- Memory System Design
READ REFRESH
WRITE
RAS.L RAS.L
ROW.L WE.L CAS.L
ROW.L ROW.L
CAS.L
RAS.L RAS.L ROW.L
WE.L RAS.L
GRNT.H
RAS.L RAS.L
CAS.L WE.L
DONE.H CAS.L
OE.L DONE.H
READ = READ.H * RQST.H’ * A<31> * A<30> * A<29> * A<28> * A<27> * A<26> * A<25>
WRITE = WRITE.H * RQST.H’ * A<31> * A<30> * A<29> * A<28> * A<27> * A<26> * A<25>
REFRESH = RQST.H
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-34 Chapter 7- Memory System Design
A ddress
A ddress
m Decoder
CS
Memory R/ W R/ W
m
Ce l l A ddress
A r r ay
Dat a
s
I/ O s s s
Mult ip lex er
Dat a
Bi-directional data bus.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-35 Chapter 7- Memory System Design
Selec t
Address
R/ W
CS CS CS
R/ W R/ W R/ W
Address A ddress A ddress
Dat a Dat a Dat a
s s s
p×s
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-36 Chapter 7- Memory System Design
k t o 2k
k Decoder
R/ W
CS CS CS
R/ W R/ W R/ W
A ddress A ddress A ddress
Fig 7.20 k
Horizontal
decoder
Chip m
Matrix R/W
Address
CS2
R/W
Chip q Data
Selects
decoder
Vertical
Multiple
chip select
lines
are used to
This scheme replace the
simplifies the last level of
decoding from gates in this
use of a (q+k)-bit matrix
decoder decoder
to using one scheme.
q-bit and one
k-bit decoder. s
One of 2m+q+k
s-bit words
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-38 Chapter 7- Memory System Design
CAS Enable
Fig 7.21 A kc
2kc decoder
Array address kr
2kr decoder
2kr decoder
RAS
R/W
Multiplexed
address m/2
RAS CAS RAS CAS
R/W R/W
•CAS is used to enable Address Address
top decoder in Data Data
decoder tree.
Data
w
•Use one 2-D array for
each bit. Each 2-D
array on separate RAS CAS
board. R/W
Address
Data
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-39 Chapter 7- Memory System Design
Chip/ board
selec t io n
Module Memory boards
Control signal generator: selec t and/ or
for SRAM, just strobes Read Co nt r o l
c h ip s
data on Read, Provides s ig n al
Wr it e generat or
Ready on Read/Write
Ready w
For DRAM–also provides
Dat a regist er
CAS, RAS, R/W, multiplexes
address, generates refresh Dat a
w
signals, and provides Ready.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-40 Chapter 7- Memory System Design
ee
e
q
s
tfr
selec t
RA S
Dy nam ic
Read Memory RAM Array
t iming CA S
Wr it e generat or
R/ W
Dat a lines
Ready w
Dat a regist er
w
Dat a
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-41 Chapter 7- Memory System Design
Module 0
lsbs
Module 0
j k k j
Two Kinds Address Address
Address Address
Organiz'n. Module select Module select
Memory Modules
are used to allow Module 2k – 1 Module 2k – 1
access to more Address Address
than one word Module select Module select
simultaneously.
(a) Consecutive words in consecutive (b) Consecutive words in the same
modules (interleaving) module
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-42 Chapter 7- Memory System Design
tb tc tb
For a read:
•return of data from memory
•transmission of completion signal
For a write:
•Transmission of data to memory (usually simultaneous with address)
•storage of data into memory cells
•transmission of completion signal
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-44 Chapter 7- Memory System Design
tc
( a) St at ic RAM behavior
Read or Writ e Row address & RAS Column address & CAS Precharge
Read or Writ e R/ W Complet e
Read Ret urn dat a
Wr it e Writ e dat a t o memory
Pending ref resh Ref resh Precharge
Complet e
ta
tc
PROPAGATION TIME FOR ADDRESS AND COMMAND TO REACH CHIP: 120 ns.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-46 Chapter 7- Memory System Design
Working set: The set of memory locations referenced over a fixed period of
time, or in a time window.
Notice that temporal and spatial locality both work to assure that the contents
of the working set change only slowly over execution time.
two adjacent
Computer Systems Design and Architecture by V. Heuring and H. Jordan
levels in the hierarchy
© 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-47 Chapter 7- Memory System Design
•As working set changes, blocks are moved back/forth through the
hierarchy to satisfy memory access requests.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-49 Chapter 7- Memory System Design
Hit Primary
Address in level
primary
memory
Word
Base address
Block Word
+ Word
Primary address
Primary address
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-51 Chapter 7- Memory System Design
Miss: the word was not found at the level from which it was requested.
(A miss will result in a request for the block containing the word from
the next higher level in the hierarchy.)
Demand paging: pages are moved from disk to main memory only when
a word in the page is requested by the processor.
Virtual memory
a Virtual Memory is a memory hierarchy, usually consisting of at
least main memory and disk, in which the processor issues all
memory references as effective addresses in a flat address space.
All translations to primary and secondary addresses are handled
transparently to the process making the address reference, thus
providing the illusion of a flat address space.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-53 Chapter 7- Memory System Design
Decisions in designing a
2-level hierarchy
•Translation procedure to translate from system address to primary address.
•Direct access to secondary level–in the cache regime, can the processor
directly access main memory upon a cache miss?
•Write through–can the processor write directly to main memory upon a cache
miss?
•Read through–can the processor read directly from main memory upon a
cache miss as the cache is being updated?
CPU
Cache Main memory
Word Block
Address
Mapping function
That same 32-bit address partitioned into two fields, a block field,
and a word field. The word field represents the offset into the block
specified in the block field:
Block Number Word
26 6
Cache block 0
2
?
Match
Cache block 2
3
4
6
To CPU
8
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-58 Chapter 7- Memory System Design
Disadvantages
•Large tag memory.
•Need to search entire tag memory simultaneously means lots of
hardware.
–next–
Direct mapped caches simplify the hardware by allowing each MM block
to go into only one place in the cache.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-59 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-62 Chapter 7- Memory System Design
Getting Specific:
The Original Intel Pentium Cache
•The Pentium actually has two separate caches–one for instructions and
one for data. Pentium issues 32-bit MM addresses.
MMX Pentium:
•16 KB code
•Each cache is 2-way set associative •16 KB data
•Each cache is 8K=213 bytes in size •4-way SA
•32 = 25 bytes per line.
•Thus there are 64 or 26 bytes per line, and therefore 213/26 or 27=128 groups
•This leaves 32-5-7 = 20 bits for the tag field:
31 0
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-64 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-65 Chapter 7- Memory System Design
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-66 Chapter 7- Memory System Design
Cache performance
ta = h • tC + (1-h) • tM
We define S, the speedup, as S= Twithout/Twith for a given process,
where Twithout is the time taken without the improvement, cache in
this case, and Twith is the time the process takes with the improvement.
Having a model for cache and MM access times, and cache line fill time,
the speedup can be calculated once the hit ratio is known.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-67 Chapter 7- Memory System Design
Address tag
64 sets
8 words 8 words
88 words
words 88 words
words
8 words
8 words 8 words
8 words
8 words 6464bytes
bytes8 words
20 bits 64 bytes
64 bytes
64 bytes
64 bytes
Line 63
•The PPC 601 has a unified cache - that is, a single cache for both
instructions and data.
•It is 32KB in size, organized as 64x8block set associative, with blocks being
8 8-byte words organized as 2 independent 4 word sectors for convenience in
the updating process
•A cache line can be updated in two single-cycle operations of 4 words each.
•Normal operation is write back, but write through can be selected on a per
line basis via software. The cache can also be disabled via software.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-68 Chapter 7- Memory System Design
Virtual memory
The Memory Management Unit, MMU is responsible for mapping logical
addresses issued by the CPU to physical addresses that are presented to
the Cache and Main Memory. CPU Chip
MMU
CPU Logical
Mapping
Physical
Address
Tables
Address
Cache Main Memory Disk
Virtual
Address
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-71 Chapter 7- Memory System Design
Main memory
Fig 7.38 FFF
Memory 0
Segment 5
management Gap
by 0 Segment 1
segmentation Virtual
Segment 6
Physical
memory
memory addresses
addresses 0
Gap
0 Segment 9
0 Segment 3 0000
•Notice that each segment’s virtual address starts at 0, different from its
physical address.
•Repeated movement of segments into and out of physical memory will result
in gaps between segments. This is called external fragmentation.
•Compaction routines must be occasionally run to remove these fragments.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-72 Chapter 7- Memory System Design
Main memory
Segmentation Offset in
Gap
Segment 1
Mechanism Virtual
segment
memory + Segment 6
address
from CPU
Segment Gap
No base
Bounds ≤ register Segment 9
error
Segment 3
Segment
limit
register
Secondary memory
Fig 7.41
Memory Virtual memory
management
by paging
Physical memory
Page n – 1
Program
unit
Page 2
Page 1
0 Page 0
•This figure shows the mapping between virtual memory pages, physical
memory pages, and pages in secondary memory. Page n-1 is not present in
physical memory, but only in secondary memory.
•The MMU that manages this mapping.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-75 Chapter 7- Memory System Design
Translation Hit.
Page table
Process Offset in
page table
Page in
primary memory.
Page placement
and replacement
Page tables are direct mapped, since the physical page is computed
directly from the virtual page number.
Page tables such as those on the previous slide result in large page
tables, since there must be a page table entry for every page in the
program unit.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-77 Chapter 7- Memory System Design
The answer: a small cache in the processor that retains the last few virtual
to physical translations: A Translation Lookaside Buffer, TLB.
The TLB contains not only the virtual to physical translations, but also the
valid, dirty, and protection bits, so a TLB hit allows the processor to access
physical memory directly.
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-78 Chapter 7- Memory System Design
Desired word
TLB miss.
Look for
physical page
in page table. Virtual Access- Physical
page control bits: page
number presence bit, number
To page table dirty bit,
valid bit,
usage bits
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-79 Chapter 7- Memory System Design
Virtual address
Search TLB Search cache Search page table Page fault. Get page
from secondary
memory
Y Y Y Page
TLB Cache Update MM, cache,
table
hit hit and page table
hit
Miss Miss Miss
Update cache
from MM
Generate physical
Generate physical address
address
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001
7-80 Chapter 7- Memory System Design
32-bit logical address from CPU
Seg
# Virtual pg # Word
Fig 7.45 4 9 7 12
The 4
16
Operation 7 15
and
misc.
32 Cache
UTLB 40
0 Set 1
0 Set 0
20
20-bit 40-bit virtual page
physical Miss—cache load
page
Compare 40
Miss—to
Compare
page table
search
“Segments” Hit
are actually
more akin to 127
large (256 MB)
blocks. 2–1 mux
Main Paging
CPU Cache Disk
memory DMA
Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan: Updated David M. Zar, February, 2001