Digital Control of a Three-Phase Four-Leg Inverter under Unbalanced

Voltage Conditions

I. Vechiu1, O. Curea1, H. Camblong1, S. Ceballos2, J. L. Villate2

(1)
LIPSI-ESTIA, Technopôle Izarbel, 64 210 Bidart, FRANCE
(2)
ROBOTIKER TECNALIA, Energy Unit, Basque Country, SPAIN
(1)Tel: + 33 (0) 559 438 474
(1)Fax: + 33 (0) 559 438 405
E-mail: i.vechiu@estia.fr
URL: http://www.estia.fr

Keywords
Converters control, Current control, Voltage control, Power Quality, Symmetrical Components,
Renewable energy systems, Hybrid power integration.

Abstract
In this paper, the implementation of an innovative inverter control strategy based on the symmetrical
components is presented. Symmetrical components of the inverter output voltage and current are
decomposed into dq DC quantities to control a three-phase four-leg inverter. This kind of inverter can
be a good choice for the applications with hybrid power system based on renewable energy used to
supply unbalanced loads. The addition of a fourth leg provides an extra degree of freedom, making
possible to handle the neutral current caused by the unbalanced load. Simulation results are compared
with experimental results for a prototype inverter to verify the validity of the proposed control
strategy.

I. Introduction
In recent years there is growing interest in four-leg converters for three-phase four-wire applications
[1][2], such as controlled rectifiers, active power filters and many others applications that require
neutral current control. One of the most promising applications of this topology is the Hybrid Power
Systems (HPS). An HPS (Figure 1) can be generally defined as an electricity production and
distribution system which consists of a combination of two or more types of electricity generating
sources (e.g. wind turbine generators, solar photovoltaic panels, picohydro plant, diesel generators…).
An HPS usually also includes an energy storage system. In such a system the different power
generators interconnected with the AC load in an isolated grid can be subject of unbalanced voltages.
Unbalanced utility grid voltages which is one of the most common utility voltage quality problem in
this kind of system, may arise due to the simultaneous supply of three-phase and single-phase loads, a
short-circuit or a starting up of a large induction machine. Such an unbalance in voltage at the point of
common coupling can cause increased losses in motor loads and abnormal operation of sensitive
electronic and electrical equipment. For low voltage distribution, when the HPS has a four wire
configuration to supply both single-phase and three-phase loads (Figure 1), a 0-sequence current flows
through the neutral conductor.
To solve the unbalanced voltage problem, an obvious solution is to use a regulation technique based
on an inner current loop and a voltage outer loop with PI-regulators in the rotating dq0-coordinate [1].
Additional control loops for the 0-sequence current and voltage must be implemented to ensure the
output voltage balance when the load is unbalanced. If the load is unbalanced, the d-, q- and 0-
components of the output voltages contain additional oscillating quantities. As a result, the PI-
regulator will only cause a phase shift and will not be able to cancel the error completely [3].

1
 va ia vA Z
IRW IDC
vb ib vB
Renewable
VDC Filter vC
Energy vc ic

vf iN vN Load

Storage
System

Fig. 1: Three-phase four-wire system for HPS application

This paper describes the real time digital implementation of an improved control strategy for the
simultaneous supply of three-phase and single-phase AC loads in a HPS application. The goal of the
system illustrated in Figure 1 is to supply the loads with constant amplitude sinusoidal voltage and
constant frequency.

II. Inverter Model

The topology of the four-leg inverter is shown in Figure 2. The midpoint of the additional fourth leg of
the inverter is connected to the star point of the load. Due to load unbalances, an intruding current
flows through the fourth wire between the load neutral point and the midpoint of the fourth leg of the
inverter, and a voltage drop occurs which distorts the symmetrical output voltage. The three phases of
the converter are independent of each other and the current flowing through each leg depends only on
the position of the associated switches and its phase voltage.

IDC
Filter
Lf Rf vA
ia
va
ib vB
VDC vf vb
vC
ic
vc
ic ib ia

LN RN Load
iN
vN

Fig. 2: Three-phase four-leg inverter for HPS application

The equations describing inverter voltages and currents in the circuit model are expressed as:
vaf  v AN  ia  ia  iN  iN 
      d     d  
vbf  = vBN  + R f ib  + L f dt ib  − RN iN  − LN dt iN  (1)
 vcf  vCN  ic  ic  iN  iN 
 
ia + ib + ic + i N = 0 (2)
where Rf, RN and Lf , LN are the resistances and the inductances of the inverter filter, vAN, vBN and vCN
are the line-to-neutral filter output voltages, ia, ib and ic are the three-phase inverter output currents and
iN is the neutral current. The DC bus current IDC is expressed as:
[ ]
I DC = d af d bf d cf ⋅ [ia ib ic ]
T
(3)
where daf, dbf, dcf are the duty cycles of the averaged model of the four-leg inverter.

2
III. Proposed Control Strategy
In light of the poor and unacceptable performance of the conventional solutions to unbalanced loading,
an innovative control strategy is proposed in this section. The main steps of this control strategy are
presented in Figure 3 and are detailed hereafter.

* *
v abc,p,n,h Sequence v abc 3D d*abc Inverter
PWM
composition SVM +
8
Filter

dq/abc
transformation

vdq,p,n,h vABC,p,n,h vABC

Current and abc/dq Sequence
* voltage idq,p,n,h transformation iABC,p,n,h decomposition iABC
v dq,p,n,h
regulation

DSP - CONTROLER

Fig. 3: Block-diagram of the innovative controller.

A. Symmetrical components of three-phase variables and rotating coordinate
transformation
In terms of control loop design, the conventional control strategy of the four-leg inverter uses voltage
and current dq0-components. If the load is balanced, the d- and q-components are DC quantities and
the 0-component is zero. If the load is unbalanced both d- and q-components contain an additional AC
quantity, which oscillates with the double frequency of the output voltage. The 0-component is not
zero and oscillates with the same frequency as the output voltage [3]. To solve this problem the
proposed control strategy uses the symmetrical components of the output voltage and current
decomposed into dq DC quantities.

According to the Fortescue theorem [4], three-phase variables can be symmetrically decomposed into
positive, negative and homopolar sequence components, as shown in Figure 4. Therefore, the inverter
output voltages can be expressed as:
v AN  v AN , p + v AN , n + v AN , h 
v  =  v 
 BN   BN , p + v BN , n + v BN , h . (4)
v CN   v CN , p + vCN ,n + vCN , h 
where ( v AN , p , v BN , p , vCN , p ) is the positive-sequence voltage, ( v AN , n , vBN ,n , vCN ,n ) is the negative-
sequence voltage and ( v AN , h , vBN ,h , vCN ,h ) is the homopolar-sequence voltage.

vC vC , p
vC , n
ω
ω
ω
vC ,h vB , h v A, h
120° 120°
120°

vA = 120° v A, p
+ v A ,n 120°
+ ω
120°

vB , p
v B ,n
vB

Fig. 4: Decomposition of a three-phase unbalanced system in three balanced systems

3
The details of the ABC signals transformation into symmetrical components has already been
presented in [3] and is therefore not duplicated here.

For the proposed control strategy, the sensed three-phase supply voltage and current are decomposed
into their symmetrical components using phasor representation. The separation method that allows
identifying the symmetrical components of the measured voltages is presented in Figure 5.

v ABC , p
[F ]
p

vABC T v ABC v ABC, n

+
4 j [Fn ]
Delay +
v ABC ,h
[Fh ]
Fig. 5: Sequence separation method

The proposed method implies delaying the measured voltage vABC by one fourth of a period at the
fundamental frequency (T=1/f, f=50Hz). The addition of the measured voltage and the same signal
delayed in space quadrature gives the phasor representation v ABC . Using this representation and the
transformation matrix [3] (Fp, Fn and Fh), the positive, negative and homopolar sequences separation is
obtained.

Because the symmetrical components are always balanced, voltage and current regulation is
performed in a dq synchronous reference frame rotating at the fundamental frequency. Thus, using a
positive reference frame, which rotates counterclockwise, the positive-sequence dq voltages and
currents appear as DC signals. In contrast, the DC quantities of the negative-sequence dq voltages and
currents are obtained using a negative reference frame, which rotates clockwise.
The homopolar-sequence voltage or current appears as a disturbance in the 0-variable at the
fundamental angular frequency ω in any rotating system reference frame, while d and q components
are inexistent. Thus, it is not possible to rotate the 0-variable voltage in order to transform it into a DC
signal and to facilitate its regulation.
As mentioned in [4], the vectors of the homopolar sequence system are in phase and equal in
amplitude. They are also independent, from the point of view of the amplitude, with regard to the
positive and negative-sequence systems. Thus, it is possible to apply a spatial displacement of 120°
and 240° to the homopolar phasors (Fig. 6).

v AN , h
v AN ,h vBN , h vCN , h

120°

vBN , h ω
ω
240°

vCN , h
Fig. 6: Homopolar sequence vectors displacement

The complete transformation of the measured voltages (currents) is shown in Fig.7. As it can be seen,
only the real part of the phasor representation is used to obtain DC signals.

4
 ω
abc vdq,p
Re
dq
v ABC -ω
vABC [Fp] vdq,n
T/4 + abc
Delay j [Fn] Re
dq
+ [Fh*] -ω
abc vdq,h
Re
dq

Fig. 7: Sequence decomposition and dq rotating frames transformation.

B. Voltage and current regulation
The voltage and current signals obtained after decomposition into symmetrical components are
regulated using an inner current loop controller and an outer voltage loop controller. Both loops are
disposed in three-channel arrangement (Figure 8). The first channel allows controlling the positive
sequence of the current and voltage, the second is for the negative sequence and the third is for the
homopolar sequence.

vABC_max i*d,p vd,p vid,p

+ + +
PI PI
vd,p - id,p - ωLf + +

vq,p - iq,p - ωLf

i*q,p + - viq,p
0 PI
+
PI
vq,p +
+
+ i*d,n vd,n +
0 PI + PI
vd,n - id,n - + - vid,n
ωLf
vq,n - iq,n - ωLf
i*q,n + + viq,n
0 PI
+
PI
vq,n +
+
+ i*d,h + vd,h +
0 PI PI
vd,h - id,h - + vid,h
vq,h - i*q,h iq,h - +
0 PI PI
+ + vq,h + viq,h
vdq,p idq,p
vdq,n idq,n
vdq,h idq,h
Fig. 8: Voltage and current regulation loops

In the inner current loop, the positive-sequence current (id,p, iq,p, in the first channel of the control
structure presented in Fig. 8) is regulated in the positive reference frame. The terms ωLfiq,p, -ωLfid,p are
inserted to decouple dq axes dynamics. The negative-sequence current (id,n, iq,n) in the second channel
of the control structure is controlled in the negative rotating reference frame. The homopolar-sequence
current (id,h, iq,h) in the third channel of the control structure is controlled in the negative rotating
reference frame.
The outer voltage loops give the reference currents {i* d,p, i*q,p, i*d,n, i*q,n, i*d,h, i*q,h} in order to keep the
measured voltages at constant values (Fig. 5). The positive-sequence voltage vd,p is compared with the

5
desired output voltage amplitude and the error is processed in a PI controller. All the remaining
sequence voltages are kept at zero value using the same procedure. These voltage set-points
correspond to a balanced three-phase AC voltage.

The control signals to be applied to the inverter are obtained using the inverse Park and Clarke
transformations with the addition of the symmetrical components, as shown in Fig. 10. The addition is
carried out phase by phase, using only one phase from the homopolar sequence:
C. 3D Space Vector Modulation
Extensive research on Space Vector Modulation (SVM) has been done for three-leg voltage source
inverter (VSI) [5][6]. The SVM for three-leg VSI is based on the representation of the three-phase
quantities as vectors in a two-dimensional (αβ) plane. This has been discussed in [6] and is illustrated
in Figure 9. A three-phase converter provides eight possible switching states, made up of six active
and two zero switching states. The desired three-phase voltages at the output of the inverter could be
represented by an equivalent vector V (Figure 9.a) rotating in the counterclockwise direction.
However, there is very limited research on how to realize SVM for four-leg VSI. The addition of a
fourth leg extends the space vectors from two to three dimensions, making the selection of the
modulation vectors more complex. Most of the algorithms that deal with this problem require a αβ0
Clarke transformation [7]. This representation seems heavy and implies complex calculations.
Because of its simplicity, the three-dimensional space vector modulation using ABC coordinates is
employed for the control of the investigated four-leg converter topology [8]. This method follows the
same procedure as classical SVM technique, keeping in mind that in this case the generated average
voltage vector, which must be equal to the reference voltage vector, is represented in 3D dimension.
Therefore, instead of selecting a region that usually is a 60 degree sector in αβ plane, a tetrahedron
composed of four vectors pointing to its corners has to be determined (Figure 9.b). Once the
tetrahedron is chosen, the duty cycles of each vector is calculated.

V4 V3

V
V5 V2

V 1=V 8

V6 V7

(a) (b)
Fig. 9: (a) Space vector representation of three-leg converter in the αβ plane; (b) Control region in
ABC coordinates, showing the switching vectors in a 3D-space for a four-leg converter

A balanced resistive load is used to show the inverter phase legs duty ratios da, db, dc and df plotted in
Figure 10.

6
 Fig. 10: Duty ratios of the inverter phase legs for balanced load during a line cycle
D. Implementation of digital controller
The control strategy and the three-dimensional space vector modulation algorithm are implemented in
a DS 1104 digital controller (Figure 11). The digital controller performs the following functions:
signal conversion from the sensed analog voltage and current signals to digital signals;
decomposition/composition into symmetrical components and coordinate transformation; voltage and
current regulation; select the switching vectors and calculate the corresponding duty ratios using three-
dimensional space vector modulation.

Hall
Sensors
4 leg IGBT Output Load
inverter Filter
+
-
VDC

Gate Drivers

PWM
TMS320F240 Low
ADC Pass
DSP
3×16 bit Filter
3×12 bit Insulated
Amplifiers
PowerPC
Processor Signals sensing and
Digital Controller
GNDIN conditioning
DS 1104 GND

Fig. 11: Block-diagram of a digital controller for the four-leg inverter

The DS 1104 controller board includes: a main processor PPC 603e that runs at 250 MHz, a slave
TMS320F240 DSP for input/output, 4 general-purpose timers and 4 A/D converter multiplexed
channels 16 bit and 4 A/D converter parallel channels 12 bit.
The inputs of the DS 1104 controller board are the line currents and the line to neutral voltages and the
output are the IGBTs gate driver pulses. The currents are sensed using Hall sensors and the voltages
are sensed through three insulated amplifiers. To attenuate unwanted high frequencies, especially the
fundamental and the harmonics of the switching frequency, the analogical signals are filtered using

7
anti-alias low pass filters. The IGBTs gate drivers serve as isolation amplifiers and provide also short-
circuit protection.

IV. Simulation and Experimental Results

To validate the proposed control strategy, many simulations have been carried out with an average
inverter model. Also, in order to test the proposed control strategy and to compare the experimental
results with simulation ones, a four-leg inverter prototype has been developed. It has been built with
MG50J2YSP IGBT’s (600 V, 50A), controlled by a fixed point DSP (TMS320F240). The
characteristics of the average inverter model and of the power inverter prototype are shown in Table I.

Table I: Parameters of the four-leg inverter

Parameters Value
Input/Output Rated Input Voltage (VDC) 70 [VDC]
Rated Output Voltage (vAN, 23 [Vrms],
vBN, vCN)
Rated Output Frequency 50 [Hz]
Rated Power (total) 700 [W]
Filter Filter inductance (Lf, LN) 3 [mH]
Components
Filter resistance (Rf, RN) 0.1 [Ω]

As shown in Table I, the prototype has been sized for 700 W rated power, but due to the DC voltage
source limitation during the tests presented below, the power of the inverter was limited to 100 W (31
rated DC input voltage).

Figures 12.a and 13.a illustrate the output current and voltage simulation results when the inverter
supplies a heavily unbalanced resistive load. The phase A of the load is loaded with 4,9 W, the phase
B is loaded with 24,5 W and the phase C is loaded with 9,8 W. In the same load conditions, Figures
12.b and 13.b show the results during the tests on the inverter prototype, when the output current and
voltage are first sensed and filtered and then measured with the ADC inputs of the DS 1104 controller
board. As can be seen in Figures 12 and 13, using a four-leg inverter and the proposed control
strategy, unbalanced output voltage due to unbalanced load can be corrected.
6 6
ic ic
ib ib
4 4
ia ia

2 2
i [A]

i [A]

0 0

-2 -2

-4 -4

-6 -6
1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.148 1.15 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.148 1.15
Time [s] Time [s]

(a) (b)
Fig. 12: (a) Simulation result of the AC-bus current; (b) Experimental result of the AC-bus current

8
 15 15

10 10

5 5

vc vc
v [V]

v [V]
0 vb 0 vb
va va

-5 -5

-10 -10

-15 -15
1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.148 1.15 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.148 1.15
Time [s] Time [s]

(a) (b)
Fig. 13: (a) Simulation result of the AC-bus voltage; (b) Experimental result of the AC-bus voltage

To quantify the level of the voltage unbalance, the percentage of negative-sequence unbalance is
expressed in accordance with the definition of the “degree of unbalance in three-phase system” [9].
Thus, the degree of the negative sequence unbalance of the investigated system for both, simulation
and experimental cases, is lower then 1,5 %. This value is tolerated by the international standards
which set the highest value of the negative sequence unbalance to 2% [9].

For the same load condition, in order to analyse the performances of the proposed control strategies
some internal variables are illustrated in Figures 14 and 15. Plots in Figures 14.a and 15.a show the
simulation results of the voltage and the current loops behavior. Plots in Figs. 14.b and 15.b show the
experimental results of the voltage and the current loops behavior.
The goal of the outer voltage regulation loop is to set the amplitude and the phase of the voltage at the
output of the inverter filter. The voltage error feeds the PI controllers having the current references as
output. The inverter current is regulated by the inner loop using PI-controllers.
The big advantage of this control strategy is its ability to control separately the positive, negative and
homopolar sequences. As can be seen in Figures 14 and 15, all voltage and current control signals are
DC quantities and consequently, the static error can be easily eliminated.

10 10
[V]

[V]

0 0
dq,p

dq,p
v

-10 -10

1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146

10 10
[V]

[V]

v v
d,pnh d,pnh
0 0
dq,n

dq,n

v v
q,pnh q,pnh
v

-10 -10

1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146

10 10
[V]

[V]

0 0
dq,h

dq,h
v

-10 -10

1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146
Time [s] Time [s]

(a) (b)
Fig. 14: (a) Simulation result of the outer voltage loop; (b) Experimental result of the outer voltage
loop

9
 4 4

[A]
2
[A]

dq,p
dq,p

0 0

i
i

-2 -2
1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146

0 id,pnh 0 i
d,pnh

[A]
[A]

-0.5 i * -0.5 i *
d ,pnh d ,pnh

dq,n
dq,n

i -1 iq,pnh
-1 q,pnh

i
i

i * iq*,pnh
-1.5 q pnh -1.5
1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146

2 2

[A]
1
[A]

dq,h
dq,h

0 0

i
i

-1 -1
1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146 1.13 1.132 1.134 1.136 1.138 1.14 1.142 1.144 1.146
Time [s] Time [ms]

(a) (b)
Fig. 15: (a) Simulation result of the inner current loop; (b) Experimental result of the inner current
loop

V. Conclusion
In this paper, the implementation of a digital control of a three-phase four-leg inverter is presented. To
attenuate the disturbances due to the unbalanced load, a fourth leg is included in the inverter and an
innovative control strategy is employed. This strategy is based on the decomposition of the supply
three-phase voltage and current into instantaneous positive, negative and homopolar sequence
components using phasor representation. The symmetrical components have been decomposed into dq
DC quantities to regulate the current and the voltage using PI-controllers. The control signals given by
the proposed control strategy have been used in three-dimensional space vector modulation algorithm
based on ABC coordinates to provide the eight duty cycles driving the four legs of the investigated
inverter. Simulations results have been confronted with the experimental results for a 700 W inverter
using DS 1104 controller board to demonstrate the performance and validate the proposed control
strategy.

References
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transformation matrix, IEEE, Transaction on Power Electronics, 2001, Volume 16, No. 5.
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362.
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