System Verilog Testbench

Training Lab Manual

Revision 2.0

Jan 15, 2019

Submit technical questions to

support@verikwest.com

Authors:
Loganath Ramachandran

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Contents

1 Overview........................................................................................................... 5
1.1 Outline .......................................................................................................................... 5
1.2 Design description ........................................................................................................ 5
1.3 AHB I/O ports description ............................................................................................ 7
1.3.1 Overview of AHB write and read operations .................................................... 8
1.4 Genif port description ................................................................................................... 9
1.5 Lab Exercises .............................................................................................................. 10
1.6 Assumptions................................................................................................................ 10

2 Checking out the lab data ............................................................................. 11

3 Lab1: SystemVerilog OOP ............................................................................ 12

3.1 Learning Objective ..................................................................................................... 12
3.2 Detailed instructions for the lab .................................................................................. 12
3.2.1 Edit the file lab1/vk_proj/verif/testbench/ahb_transaction_base.sv ................ 12
3.2.2 Edit the file lab1/vk_proj/verif/testbench/ahb_transaction.sv ......................... 13
3.2.3 Edit the file lab1/vk_proj/verif/testbench/testbench.sv.................................... 13
3.3 Compile and run simulation ........................................................................................ 14
3.4 Review simulation results ........................................................................................... 14
3.5 Summary ..................................................................................................................... 14

4 Lab2: Constrained Randomization .............................................................. 15

4.1 Learning Objective ..................................................................................................... 15
4.2 Detailed instructions for the lab .................................................................................. 15
4.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_transaction.sv ....................... 15
4.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv.................................. 16
4.3 Compile and run simulation ........................................................................................ 16
4.4 Review simulation results ........................................................................................... 16
4.5 Summary ..................................................................................................................... 17

5 Lab3: Functional Coverage........................................................................... 18

5.1 Learning Objective ..................................................................................................... 18
5.2 Detailed instructions for the lab .................................................................................. 18
5.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_cover_module.sv .................. 18
5.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv.................................. 19
5.3 Compile and run simulation ........................................................................................ 19
5.4 Review simulation results ........................................................................................... 20
5.5 Summary ..................................................................................................................... 20

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System Verilog Testbench Revision 2.0 Contents

6 Lab .................................................................................................................. 20

7 Lab 4: Clocking Blocks ................................................................................. 21

7.1 Learning Objective ..................................................................................................... 21
7.2 Detailed instructions for the lab .................................................................................. 21
7.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_interface.sv ........................... 21
7.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv.................................. 21
7.3 Compile and run simulation ........................................................................................ 21
7.4 Review simulation results ........................................................................................... 22
7.5 Summary ..................................................................................................................... 22

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Revision history

Revision Date Description

1.0 May 7, 2012 First release
1.0.2 Feb 10, 2013 Minor format updates
2.0 Jan 15, 2018 Added commands for VCS

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 Overview

1 Overview

1.1 Outline
This document contains 4 lab exercises that supplement the “Fundamentals of
SystemVerilog”, an onsite course offered by VeriKwest Systems Inc. This course is
intended for beginners who are interested in learning the basics of the SystemVerilog
language. It gives a broad perspective on the language, and can be taken by both design
and verification engineers for getting introduced to the basics of the SystemVerilog
language.
This course focuses on these important topics: (a) SystemVerilog scalar and array data
types, (b) SystemVerilog tasks and functions, (c) SystemVerilog packages and finally (d)
SystemVerilog interfaces.
For the purposes of these lab exercises, we will use a very small portion of the AMBA AHB
protocol. The complete AHB protocol is far more complex. You may obtain the complete
details of the AMBA architecture from ARM ™ Limited (http://www.arm.com).

1.2 Design description

These lab exercises focus on creating a slave module that can store and retrieve data
values from an internal memory. The external communication uses a subset of the AMBA
protocol with single read/write instructions. The purpose of the lab exercises is to get
familiarized with SystemVerilog language constructs. This is not intended to teach details
of the AMBA protocol and prior knowledge of AMBA AHB is not necessary to complete
these lab exercises.
Internally the design uses a simple interface (referred to as genif) to communicate within
the slave.
The overall architecture used in the labs is shown below. The test bench module
instantiates the AHB slave and all the other modules required for the labs.

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System Verilog Testbench Revision 2.0 Overview

ahb_slave_top
clk_gen

ahb_to_genif
reset_gen

flow_control
genif_monitor

genif_memory

The test bench module instantiates the slave (“ahb_slave_top”) and all the modules
needed to drive transactions into the slave. The different blocks used in the test bench
are:
Module Filename Description
ahb_slave_top ahb_slave_top.sv This module represents the AHB slave. It has
the I/O pins shown in Section 1.3.
ahb_to_genif ahb_to_genif.sv This module converts the AHB read/write
transactions to a transaction on the genif
interface.
genif_monitor genif_monitor.sv Monitors the genif interface bus and displays
a message when it observes a read or write
transactions
genif_memory genif_memory.sv This is the actual memory module where the
slave data is stored. It is attached to the genif
interface bus.
clock_gen clock_gen.sv A simple clock generator
reset_gen reset_gen.sv A reset generator which activates the reset for
the first few cycles
flow_control_block flow_control_block.sv Controls the flow of transactions on the slave
by setting the hready_in to be low at certain
times during the simulation.

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System Verilog Testbench Revision 2.0 Overview

1.3 AHB I/O ports description

The slave uses a subset of a typical AHB protocol. The slave I/O ports are shown in the
following figure.

hclk
hreset_n

hwrite

haddr

htrans

hburst AHB
hwdata
Slave

hrdata

hresp

hready hready_in

Signal Type Description

hclk logic Clock input for the slave module
hreset_n logic Reset – active low
hwrite logic Set high for a write operation, set low for a read operation
haddr logic_vector Address for the transaction
hwdata logic_vector Write Data value
hrdata logic_vector Read data value (returned by the slave)
hready logic “1” implies slave is ready, else slave is not ready to accept
transactions
hready_in logic Input to the slave indicating external module is not ready.
Can be used for flow control
htrans logic[1:0] Types of transfer {NONSEQUENTIAL, SEQUENTIAL,
IDLE, BUSY} . We will use NONSEQUENTIAL transfers
in this lab

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System Verilog Testbench Revision 2.0 Overview

hresp logic[1:0] Indicates status of the transfer. Types are {OKAY, ERROR,
RETRY, SPLIT}. We will set this signal to 0 to indicate
OKAY response for this lab.
hburst logic[2:0] Type of burst. We will not be supporting burst transfers in
this labl

1.3.1 Overview of AHB write and read operations

For a write operation the AHB protocol has two phases: (a) the address phase, where the
master writes the address on the haddr bus, and (b) the data phase where the
corresponding data is written. In the figure below, the master (or the test bench) sets the
haddr to 21 in the first cycle. It then sets the hwdata to 31 in the next cycle. Thus the first
two cycles represent a write operation where DATA (31) is written to ADDR (21).
If hreadyis not high, then the master is expected to hold the hwdata and haddr signals
steady. During the second write operation where the data value (32) is being written to
address 22, the master holds the data till the slave is ready.

hclk

haddr 21 22 23 24
(ADDR-A) (ADDR-B) (ADDR-C) (ADDR-D)

31 32 33
hwdata (DATA-A) (DATA-B)) (DATA-C)

hwrite

hready

The read operation shown below is very similar to the write operation. During the address
phase the master writes the address on the haddr bus, and during the data phase the
slave returns the value. In the figure shown below, the master sets the haddr is set to 21
in the first cycle. The slave sets the hrdata to 31 in the next cycle. Thus the first two cycles
represent a read operation where DATA (31) was read from ADDR (21).
If hready is low, then the master is expected to hold the hwdata and haddr signals steady.

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System Verilog Testbench Revision 2.0 Overview

hclk

haddr 21 22 23 24
(ADDR-A) (ADDR-B) (ADDR-C) (ADDR-D)

31 32 33
hrdata (DATA-A) (DATA-B)) (DATA-C)

hwrite

hready

1.4 Genif port description

Genif is a simple general purpose interface. The I/O port description of the genif interface is
shown in the following table.

Signal Type Description

genif_wdata logic_vector Write data on the genif interface
genif_rdata logic_vector Read data on the genif interface
genif_wenable logic Write enable. Current packet is a write operation
genif_renable logic Read enable. Current packet is a read operation.

genif_addr logic_vector Address for the current read or write operation.

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System Verilog Testbench Revision 2.0 Overview

1.5 Lab Exercises

Lab Description

Lab1 You will learn how to create classes and objects .

Lab2 You will learn how to use randomization to control the objects.
Lab3 You will learn how to create coverpoints and covergroups.
Lab4 You will learn how to use clocking blocks in SystemVerilog

1.6 Assumptions
The labs are tool agnostic. You can use a simulator of your choice. We will not cover the
details of any simulators. Separate courses offered by tool vendors can help you learn
more about Modelsim (Mentor Graphics), IUS (Cadence Design Systems) and VCS
(Synopsys).

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System Verilog Testbench Revision 2.0 Checking out the lab data

2 Checking out the lab data

Before running any of the exercises in this module you must checkout the lab data.
Follow the steps below to check out lab1. (You will need a linux shell to execute the
following commands).

1. Create a new directory for the labs in your home directory

$ mkdir svtb_training_labs
$ cd svtb_training_labs

2. Download the lab files from the Verikwest Web Site

 Get the user id and passwd from your instructor.

3. Uncompress and untar the lab archives in the directory

For example, use the following command to set up lab1

$ /pkg/gnu/bin/tar xvzf svtb_labs.tar.gz

This should create 4 lab directories. (lab1, lab2, lab3, lab4)

4. Change to the appropriate lab directory. For example if you workin on lab1, cd to
that directory.
$ cd lab1

5. You will find init.csh in each of the lab directories. Please modify the init.csh to ensure that
the simulation environments are correctly initialized for your company enviromnment.
Then source the init.csh using the following command.
$ source init.csh

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System Verilog Testbench Revision 2.0 Lab1: SystemVerilog OOP

3 Lab1: SystemVerilog OOP

3.1 Learning Objective

In this lab you will learn the basics of Object Oriented Programming. You will learn how to
specify a class in SV and create objects of the class. You will also use class inheritance
to derive a child class from a base class.
In this lab you will create ahb_transaction objects in the testbench and you will use the
interface to drive the transactions onto the DUT.

3.2 Detailed instructions for the lab

3.2.1 Edit the file lab1/vk_proj/verif/testbench/ahb_transaction_base.sv

Note that this file defines a class called ahb_transaction_base

Step 1: Declare the class members

Search for the marker //Fixme(begin): Lab1 (class_member)
Declare an integer variable m_id to store a transaction id for each transaction

Step 2: Declare class methods

Search for the marker: //Fixme(begin): Lab1 (class_method)

Declare two functions set_id and get_id

1. set_id accepts an integer and stores it in the member variable m_id
2. get_id returns the m_id to the caller

Declare both these functions as extern virtual.

Step 3: Specify the next state computation

Search for the marker //Fixme(begin): Lab1 (print definition)

Implement the print function in the class. The print function is expected to print
the m_id and m_name with the following format
Name :: aaaa
Id :: 3
Hint: use $display with appropriate formatting

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System Verilog Testbench Revision 2.0 Lab1: SystemVerilog OOP

3.2.2 Edit the file lab1/vk_proj/verif/testbench/ahb_transaction.sv

Note that this file defines a class called ahb_transaction

Step 1: Declare class members

Search for the marker //Fixme(begin): Lab1 (class_member)
(1) Declare a variable to hold the address of the ahb_transaction. The name of the
variable is m_address and the type is bit[AWIDTH-1:0]
(2) Declare a variable to hold the type of AHB command. The name of the variable is
m_type and the type is ahb_read_write_enum

Step 2: Define class methods

Search for the marker //Fixme(begin): Lab1 (class methods )
(1) implement class methods for get_address and set_address
(2) Implement class methods for get_type and set_type

Step 3: Define class methods

Search for the marker //Fixme(begin): Lab1 (print method )
(1) Implement class methods for print. The print method should use the get_methods to
access various members of the object and print it using $display. Use the super.print() to
ask the parent classto print its members.
(2) You can print the following members
m_type, m_ddress m_wdata and m_rdata

3.2.3 Edit the file lab1/vk_proj/verif/testbench/testbench.sv

Note that this file defines the testbench that will drive the transactions to the bus

Step 1: Declare objects

Search for the marker //Fixme(begin): Lab1 (declare objects)
Declare two variables trans1 and trans3 to hold two ahb_transaction objects

Step 2: Create a write transaction

Search for the marker //Fixme(begin): Lab1 (write transaction)
(a) Create a new object for trans1 using the constructor
(b) Update the address, data and trans type using the set routines
m_address = 20, m_wdata = 200, m_type = AHB_WRITE
(c) Call the print routine with the trans1 handle

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System Verilog Testbench Revision 2.0 Lab1: SystemVerilog OOP

Step 2: Create a read transaction

Search for the marker //Fixme(begin): Lab1 (read transaction)
(a) Create a new object for trans3 using the constructor
(b) Update the address, data and trans type using the set routines
m_address = 20, m_wdata = 200, m_type = AHB_READ
(c) Call the print routine with the trans3 handle

3.3 Compile and run simulation

Step 1: Setup the simulator
$ setenv VK_SIMULATOR simulator_name // simulator_name can be questa or vcs
Step 2: Change to the compile directory
$ cd lab1/verif/compile
Step 3: Compile the simulation
$ make compile
Step 4: Run the simulation in non-interactive mode
$ make runc
Step 5: Run the simulation in interactive mode
$ make run

3.4 Review simulation results

Review the logs in the output_vcs or output_questa directory. You will observe that this
test drove a write transaction followed by a read transaction.

--------------------
# Transaction::
# Name :: trans3
# Id :: 3
# Type :: 0
# Address :: 20
# rData :: 200
# --------------------
#
# MONITOR: ( 66) Reading data ( 200) from address 20
# -----------------
# Test Passed
# -----------------

3.5 Summary
In this lab exercise you learned how to use SystemVerilog classes. You created two
classes and create a couple of objects. After initializing the objects you used it to drive
the transaction onto the bus.

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System Verilog Testbench Revision 2.0 Lab2: Constrained Randomization

4 Lab2: Constrained Randomization

4.1 Learning Objective

In this lab you will learn how to use a constrained random verification to generated
transactions and drive it on to the interface. You will use rand variables in a class and use
the randomize() method on the objects to generate new values for the class members.
You will add constraints to make sure that the generated values follow the expected
behavior

4.2 Detailed instructions for the lab

4.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_transaction.sv

Step 1: Declare rand member variables

Search for the marker //Fixme(begin): Lab2 (rand member variables

Declare new variables to hold m_address, m_type, m_wdata, m_rdata. These should
be declared with the rand keyword in this lab as they will be randomized.

Step 2: Declare constraints

Search for the marker // Fixme(begin): Lab2 (constraints)

Declare two constraints c_m_address and c_m_type. Hint do not use the keyword
extern, although we will be defining these constraints outside the class.

Step 3: Define a set constraint

Search for the marker // Fixme(begin): Lab2 (set constraint)
Define the c_m_address constraint to make sure that the address is always chosen from
the set {'d20,'d40,'d60,'d80,'d100}.Hint: use the inside constraint specification

Step 4: Define an implication constraint

Search for the marker // Fixme(begin): Lab2 (implication constraint )
Use implication constraints to specify the constraint c_m_wdata. Under this constraint if
the m_type is AHB_WRITE then the m_wdata must be equal to 2 times the m_address.
// Hint: use if or implication constraints

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System Verilog Testbench Revision 2.0 Lab2: Constrained Randomization

4.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv

Step 1: Run randomization
Search for the marker //Fixme(begin): Lab2 (randomization
Create a for-loop that iterates 30 times. During each iteration randomize the transaction
object trans1 with an additional constraint that m_type should be equal to AHB_WRITE.
Call the drive_transaction method with the trans1 argument during each iteration
Hint: use obj.randomize() with {constraints}

4.3 Compile and run simulation

Step 1: Setup the simulator
$ setenv VK_SIMULATOR simulator_name // simulator_name can be questa or vcs
Step 2: Change to the compile directory
$ cd lab2/verif/compile
Step 3: Compile the simulation
$ make compile
Step 4: Run the simulation in non-interactive mode
$ make runc
Step 5: Run the simulation in interactive mode
$ make run

4.4 Review simulation results

In this simulation the test bench sends 30 transactions to the slave. The transactions are
intended to be targeted to a set of 5 potential addresses. You use the SystemVerilog
randomize method to drive the generate the random transactions.You will observe 30
write transactions as shown below.

--------------------
Transaction::
Name :: trans1
Id :: 1
Type :: 1
Address :: 100
wData :: 200
--------------------

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System Verilog Testbench Revision 2.0 Lab2: Constrained Randomization

4.5 Summary
In this lab exercise you learned how to define and use a System Verilog randomize()
method on the ahb_transaction object. This is the beginning of constrained driven
verification.

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System Verilog Testbench Revision 2.0 Lab3: Functional Coverage

5 Lab3: Functional Coverage

5.1 Learning Objective

In this lab you will learn how to use the functional coverage features of the SystemVerilog
language. You will create a cover module that contains coverpoints and covergroups and
add it to the testbench.

5.2 Detailed instructions for the lab

5.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_cover_module.sv

Step 1: Declare Coverpoint with several bins

Search for the marker //Fixme(begin): Lab3 (haddr coverpoint)

1. Create a cover point - create a coverpoint on haddr signal and name it as cp_haddr
2. Create 16 equal sized coverbins on it
Hint : Use haddr_rngVal defined above, to get size of the bins
Use haddr_maxVal define above, to get the max value of the bin

Step 2: Declare coverpoint with transition bins

Search for the marker // Fixme(begin): Lab3 (hwrite coverpoint)

1. Create a coverpoint on hwrite signal and name it as cp_hwrite

2. Create 4 bins to capture values
bin hwrite_lo for 0;
bin hwrite_hi for 1;
bin hwrite_lo_to_hi for 0-->1 transition
bin hwrite_hi_to_lo for 1-->0 transition

Step 3: Define cross coverpoints

Search for the marker // Fixme(begin): Lab3 (crosspoint)
1. Create a crosspoint between cp_hwrite and cp_hwdata
2. Create 4 bins to capture 4 sample ranges on hwdata when hwrite is 1
hwrite_hi_X_hwdata_0 cross between bins hwdata_0 && hwrite_hi
hwrite_hi_X_hwdata_1 cross between bins hwdata_5 && hwrite_hi
hwrite_hi_X_hwdata_2 cross between bins hwdata_10 && hwrite_hi
hwrite_hi_X_hwdata_3 cross between bins hwdata_15 && hwrite_hi

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System Verilog Testbench Revision 2.0 Lab3: Functional Coverage

Step 4: Instantiate covergroup

Search for the marker //Fixme(begin): Lab3 (covergroup instantiation)
1. Declare the instance of the cover group
2. Create an object of the cover group in the initial block
- Hint: use constructor
3. Sample the instance of the cover group on posedge of hclk in the always block
- Hint: use sample method

5.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv

Search for the marker //Fixme(begin) - Lab3 (Instantiate the cover module)

Step 1: Instantiate the cover module

1. Instantiate Cover Module - instance name is coverage_module_inst
2. Connect the signals to the ports of the cover module
// Hint: Similar to DUT instantiation

5.3 Compile and run simulation

Step 1: Setup the simulator
$ setenv VK_SIMULATOR simulator_name // simulator_name can be questa or vcs
Step 2: Change to the compile directory
$ cd lab3/verif/compile
Step 3: Compile the simulation
$ make compile
Step 4: Run the simulation in non-interactive mode
$ make runc
Step 5: Run the simulation in interactive mode
$ make run
Step 6: Generate the coverage
$ make coverage
Step 7: View the coverage
$make view_coverage

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System Verilog Testbench Revision 2.0 Lab

5.4 Review simulation results

In this simulation the test bench sends 4 transactions to the slave. The coverage module
samples these transactions and computes the coverage based on the functional
coverage model specified. View the generated cover model and try to justify the
numbers.

5.5 Summary
In this lab exercise you learned how to define and use a System Verilog functional
coverage. This is an important part of constrained driven verification.

6 Lab

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System Verilog Testbench Revision 2.0 Lab 4: Clocking Blocks

7 Lab 4: Clocking Blocks

7.1 Learning Objective

In this lab you will learn how to use the clocking block features of the SystemVerilog
language. You will specify a clocking block in the ahb_interface and use the clocking block
to drive the signals.

7.2 Detailed instructions for the lab

7.2.1 Open the file lab2/vk_proj/verif/testbench/ahb_interface.sv

Step 1: Specify a clocking block

Search for the marker //Fixme(begin): Lab4 (Clocking Block)

Specify the clocking event for the clocking block of the AHB Interface
1. Specify the sampling edge of the clock
2. Specify the inputs skew as input #1 and output skew as output #2
3. List the signals of the interface that are sampled and driven
- Hint : HADDR, HTRANS

7.2.2 Open the file lab2/vk_proj/verif/testbench/testbench.sv

Step 1: Use the clocking blockDeclare coverpoint with transition bins

Search for the marker // Fixme(begin): Lab4 (clocking block use)

1. Use the clocking block trigger as an event

// - Hint vif.cb_ahb
2. Use the clocking block cb_ahb to drive the HADDR and HWDATA signals

7.3 Compile and run simulation

Step 1: Setup the simulator
$ setenv VK_SIMULATOR simulator_name // simulator_name can be questa or vcs

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System Verilog Testbench Revision 2.0 Lab 4: Clocking Blocks

Step 2: Change to the compile directory

$ cd lab3/verif/compile
Step 3: Compile the simulation
$ make compile
Step 4: Run the simulation in non-interactive mode
$ make runc
Step 5: Run the simulation in interactive mode
$ make run

7.4 Review simulation results

In this simulation the test bench uses the clocking block to drive the output signals.
Since the driving delay is 2ns, you will see that the HADDR and HWDATA values
changes slightly after the posedge of the clock. You can observe this on the waveform
GUI.

7.5 Summary
In this lab exercise you learned how to define and use a System Verilog clocking blocks.

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