Floorplanning and Place and Route (Flat)

Module 3 Extraction, Timing Analysis, Optimization and CTS

Table of Contents

Lab 3-1 Extracting RC Data .............................................................................................................. 1

Calculating Delays..................................................................................................................... 2
Lab 3-2 Running Timing Analysis and Generating a Slack Report ................................................... 3
Lab 3-3 Running Timing Optimization ............................................................................................. 4
Lab 3-4 Running Clock Tree Synthesis............................................................................................. 5
Viewing the Clock Tree Results ................................................................................................ 5

Floorplanning and Place and Route (Flat)

Module 3 Extraction, Timing Analysis, Optimization and CTS

Lab 3-1 Extracting RC Data

Objective: To extract parasitic based on Trial Route.

In this lab, you extract RCs (resistance and capacitance). They are a prerequisite for
running timing analysis.

1. Start the Innovus software by

entering: innovus
2. Restore your design by choosing File – Restore
Design. Enter your previously save pr.enc file.
3. To run extraction, choose Timing – Extract RC.
4. Select the Rc corner to Ouput as rc_worst and click OK.
## With this the tool will extracts resistance and capacitance for the interconnects
and stores the results in an RC database.

Note: For the purposes of this lab, don’t save any files, because the generated files will
be very large. The extracted RC information is annotated in the design database.
Notice that the status of the design on the lower right corner changes from Routed to
RC Extracted.

Calculating Delays

Next, delays are calculated for the interconnect wires and include instance delays.

1. Choose Timing – Write SDF.

a. Select Ideal Clock if it is not selected, because you have not yet run clock
tree synthesis on the design.
b. Click OK.
The command writes delays to SDF format file.

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Module 3 Extraction, Timing Analysis, Optimization and CTS

Lab 3-2 Running Timing Analysis and Generating a Slack Report

Objective: To analyze timing and display violating paths.

After extracting parasitic, run timing analysis to generate timing reports.

1. Choose Timing – Report Timing.

The Timing Analysis form opens.

2. In the Timing Analysis form, make sure that the Pre-CTS option is selected because you
have not created a clock-tree for the design.
The Setup option is selected (default), because we are interested in generating
reports for setup under worst-case conditions.
The timing reports will be saved to the directory specified in the Output Directory field.
Note: The Pre-Place option considers a zero-wire load model while ignoring high-fanout
nets. This option is useful to check if there are any errors in your constraints file prior to
running placement for the first time.
3. Run timing analysis for setup by clicking OK.

4. After running the analysis, view the slack report by choosing Timing – Debug
Timing. This command brings up the Display/Generate Timing Report form.
5. Click OK.
The Timing Debug window comes up.
How many failing paths do you have in the design? Answer: __________
What is the Worst Negative Slack (WNS) and the Total Negative Slack (TNS)?
Answer: __________

6. Double-click one of the failing paths in the Path section of the Timing
Debug window. The selected path is highlighted in the Design window.
This choice will also display the Timing Path Analyzer with more details in the path.
7. Close the Timing Path Analyzer window by clicking the X at the top corner of the window.
8. Close the Global Timing Debug Tool by closing the window.

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Module 3 Extraction, Timing Analysis, Optimization and CTS
Lab 3-3 Running Timing Optimization
Objective: To run timing optimization to close the timing.
c
Now you can run optimization to fix setup violations.
1. Choose Eco – Optimize Design.
The Optimization form opens.
Note : we can run optimization by using below command
optDesign -preCTS | postCTS | postRoute
preCTS: Will perform timing optimization before clock tree is built and generates timing
reports
postCTS: Will perform timing optimization after clock tree is built and generates timing
reports
postRoute: Will perform timing optimization after routing and generates timing reports

2. Because you have not yet run clock tree synthesis (CTS), make sure that the pre -
CTS button is selected.
3. Click the Mode button.
The mode setup form appears.

a. Make sure that the Max Density is 0.95.

This setting limits the increase in area due to the addition of buffers during
optimization. As a recommendation, begin with a Core Utilization that is
approximately 5% lower than the final utilization.
b. Click OK to run optimization.
4. After optimization has finished, update the timing debug display by
selecting Timing – Debug Timing.
This command displays the Timing Debug window.

5. Select the file folder icon next to the Report File(s) parameter. This
option brings up the Display/Generate Timing Report Form.

6. Click OK to regenerate the timing report file and to update the timing display.
Did you close timing with a resulting positive slack? Answer: __________
7. When the optimization has finished, view the log file.
Compare the worst slack post-optimization slack to the pre-optimization slack.
8. Save the design.
a. Make sure that you save the file in the work directory and not in
the timingReports directory.
b. Choose file – Save Design.
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Module 3 Extraction, Timing Analysis, Optimization and CTS

Lab 3-4 Running Clock Tree Synthesis

Objective: To run clock tree synthesis with a clock specification file.

After running placement or pre-CTS optimization, you run clock tree synthesis, which requires a clock
specification file. This file specifies target skews, insertion delay and for the clocks in your design. We
need to create a ccopt Spec file as below:
We must have predefined NDR rules
We can create the NDR rules as below as per design requirement(1w1s or 2w2s)
1w1s It means single width and single spacing of metal layers
2w2s It means double width and double spacing

Example:
add_ndr –name 1w1s -width {metal1:metal4 0.20} –spacing {metal1:metal4 0.2}
Above command defines 1w1s rules for M1 to M4 (metalwidth and spacing defined from lef
files) add_ndr –name 2w2s -width {metal1:metal4 0.40} –spacing {metal1:metal4 0.4}
Above command defines 2w2s rules for M1 to M4 (metalwidth and spacing defined from lef files)

OR
The NDR rules can be defined through the NDR LEF file
Example:
We can define the clock tree spec file as below:
create_route_type -name route_ndr_name1 -non_default_rule <ndr_rule> -bottom_preferred_layer <layer_name> -
top_preferred_layer <layer_name>
create_route_type -name route_ndr_name2 -non_default_rule <ndr_rule> -bottom_preferred_layer <layer_name> -
top_preferred_layer <layer_name>
##The create_route_type commands creates a new route type and sets the routing properties for the nets.
## The -non_default_rule specifies the NDR rule associated with this route type.
## The –bottom_preffered_layer and –top_preffered_layer will define the bottom and top layers for route
type.
We can assign the routing rules and layers for clock routing

set_ccopt_property route_type -net_type trunk route_ndr_name1

set_ccopt_property route_type -net_type leaf route_ndr_name2

## The set_ccopt_property command is used to set different ccopt object properties.

## The –net_type switch specifies the net type to which the property applies.

set_ccopt_property target_insertion_delay <num value>

## The target_insertion_delay will specify the insertion delay to be
targeted. set_ccopt_mode -integration "native" \
-cts_inverter_cells "CLKINVcell1 CLKINVcell2" \ -
cts_buffer_cells "CLKBUFFcell1 CLKBUFFcell2" \
-cts_use_inverters true | false (If you want to use clkinverters set as true )

## The set_ccopt_mode command will set the global parameters for ccopt.

## The –cts_inverter_cells, -cts_buffer_cells will specify the inverter/buffer cells to be used to build the clock tree.

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Module 3 Extraction, Timing Analysis, Optimization and CTS

## The –cts_use_inverters will specify whether CCOpt should use inverters or buffers when balancing the
clock tree.

setCCOptMode -cts_target_skew <num value>

## The –cts_target_skew value will specify the targeted skew value for the design.

setCCOptMode -cts_target_slew <num value>

## The –cts_target_slew value will specifies the clock tree transition.

setCCOptMode -cts_target_nonleaf_slew <num value>

## The –cts_target_nonleaf_slew will specifies the transition time target for non-leaf nets.

create_ccopt_clock_tree_spec -filename ctsccopt.spec

## The create_ccopt_clock_tree_spec will generate a CCOpt spec file with a given file name. Open the
file analyze what it contains.

innovus 13> source ctsccopt.spec

innovus 13> ccopt_design (It will do the clockTreeSynthesis and post_cts_opt

also) If you want to build only cts then use ccopt_design -cts
Still timing is not met then you can go for optDesign -postCTS

Viewing the Clock Tree Results

1. Make sure that you are in the Physical View.

2. Under the Net field enable only clock for the visibility of the clock nets.

3 . To Generate clock reports:

Execute the below commands in innovus shell:
report_ccopt_clock_trees -file <filename>
## Above command reports a summary of all defined clock trees . In particular , this report
provides a summary of numbers of clock gates at different depths in each clock tree.
report_ccopt_skew_groups -file <filename>
## This command displays information about skew and insertion delay in skew
groups. report_clock_timing -type summary > clockSummary.rpt
report_clock_timing -type skew -verbose > clockSkew.rpt
report_clock_timing -type latency -verbose > clocklatency.rpt
## report_clock_timing command will dump clock reports
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Module 3 Extraction, Timing Analysis, Optimization and CTS

4. Save the design by choosing File – Save Design and entering the file name clock_tree_syn.enc

5.In your present working directory, find the clock report files as per above commands In
another terminal, open the files in the other terminal and go through the files.
What does this files contain? Answer: __________
Were all clock constraints met? If not, which constraints were not met? Answer: __________

6.The clock uncertainty value in the dtmf.sdc file includes both jitter and insertion delay.
Because you have a clock tree now, the actual insertion delay will be taken into account by the
timing analysis tool.
Therefore, you need to reduce the clock uncertainty number in the constraints file and leave in
the jitter value.
7. For updating uncertainties execute below command.

Set_clock_uncertainty <num value> –from [all_clocks] \ –to

[all_clocks]

8.Run timing analysis in post-CTS mode by running the following command:

timeDesign –postCTS
Note: Runs Early Global Route, extraction and timing analysis, and generates detailed timing
reports. The generated reports are saved in ./timingReports directory or the directory that you
specify using the -outDir parameter

9.View the DTMF_CHIP_postCTS.summary file in the timingReports directory and check the setup
time.
5.
Were post-clock tree timing constraints met? Answer: __________
What is your slack in your design? Answer: __________
10. Now run hold time analysis by entering:
timeDesign –postCTS -hold
What is your slack in your design? Answer: __________

11. If you have hold violations, run optimization for hold. What
is the slack after optimization? Answer: __________
If you have hold violations after running hold optimization, then routing the design might
improve or fix the negative slack. In later labs, you will route the design and rerun hold
checks to see if you still have violations.
12. Save your design as postCTSopt.enc.
13. Close the Innovus software.

Summary

In this lab, you extracted parasitics, ran timing analysis and ran an optimization. After
optimization, you ran clock-tree synthesis to build a clock tree in your design. You reran timing
analysis to check if there are any post-CTS timing violations. When you had violations, you reran
optimization to improve timing.

For a specific floorplan, you quickly got relatively accurate feedback on the timing of the design.

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