Code No: R1622054 R16 SET - 1

II B. Tech II Semester Model Examinations, March 2018

Computer Organization

Time: 3 hours Max. Marks: 70

Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any THREE Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Perform the following subtractions in the binary number system, using 2’s (4M)
complements : (i) 1111 – 110 (ii) 1110 – 1100
b) Differentiate between Micro operation and Macro Operation with an example (4M)
c) “Instruction Set Architecture has impact on the processors micro architecture” – (3M)
support this statement with proper reasoning.
d) Differentiate Micro programmed control and Hardwired control. (4M)
e) What is the impact of the cache on overall performance of the computer? (3M)
f) What do you understand by the term peripheral? Explain with some examples (4M)
PART -B
2. a) Explain different functional units of a digital computer with neat sketch. (8M)
b) Discuss the advantages, disadvantages, and applications of (8M)
i) Excess – 3 code ii) Gray Code
(Illustrate with one example each)

3. a) Explain memory reference instructions with an example each. (8M)

b) Write short note on i) BUN ii) BSA iii) ISZ (8M)

4. a) What do you mean by addressing mode? Explain the following addressing modes (8M)
with examples.
i) Index addressing mode ii) Relative addressing mode
b) Explain clearly the three types of CPU organizations with examples (8M)

5. a) Perform floating point addition using the numbers 0.5 and 0.4375 use the floating (8M)
point addition algorithm.
b) Explain the multiplication of positive numbers using array multiplier with a neat (8M)
sketch.

6. a) What is virtual memory? With the help of neat sketch explain the method of (8M)
virtual to physical address translation.
b) Explain the READ and WRITE operations in Associative Memory (8M)

7. a) Draw the block diagram of a DMA controller and explain its functioning? (10M)
b) Discuss any five key differences between subroutine and interrupt service routines (6M)

WWW.MANARESULTS.CO.IN
1 of 1

|''|'''||''||'''||||
Code No: R1622054 SET - 2
R16
II B. Tech II Semester Model Examinations, March 2018
Computer Organization
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any THREE Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) “2’s complement approach is preferable than sign magnitude for representing the (3M)
fixed point numbers” – Justify this statement
b) What are the functionalities of program counter, instruction register and data (3M)
register?
c) Explain the need of some bits of current microinstruction to generate address of (4M)
the next microinstruction with an example.
d) Perform the arithmetic operations below with binary numbers and with negative (4M)
numbers in signed 2’s complement. Use seven bit to accommodate each number
together with its sign. i) -35 + -40 ii) -35 + +40
e) Differentiate between static RAM and dynamic RAM (4M)
f) Distinguish between synchronous data transfer and asynchronous data transfer. (4M)
PART -B
2. a) Perform the following: (8M)
i) (110.101) 2 = ( )10 ii) (1.10101)2 = ( )10
iii) (11010.1)2 = ( )10 iv) 110.10 x 10.1
b) Discuss various generations of computer with the technological features and (8M)
devices that characterized each generation

3. a) Distinguish between circular shift and arithmetic shift with proper example. (8M)
b) Explain the design of accumulator logic. (8M)

4. a) Distinguish the characteristics of RISC and CISC (8M)

b) Explain the three basic types of data manipulation instructions. (8M)

5. a) Given signed decimal number +86 and -17. Perform (using 8 – bit representation) (8M)
i) 2’s complement Addition ii) 2’s complement Subtraction
b) Explain the steps for Floating Point Multiplication with neat diagram and suitable (8M)
example.

6. a) Draw a neat block diagram of memory hierarchy in a computer system. Compare (8M)
the parameters size, speed and cost per bit in the hierarchy.
b) Explain ROM and RAM with respect to their block diagrams (8M)

7. a) Explain in detail on i) Vectored Interrupt ii) Interrupt Nesting (8M)

b) Discuss on the following with neat sketches (8M)
i) Time – Shared Common bus ii) Multistage Switching Network

1 of 1
WWW.MANARESULTS.CO.IN
|''|'''||''||'''||||
 Code No: R1622054 R16 SET - 3
II B. Tech II Semester Model Examinations, March 2018
Computer Organization

Time: 3 hours Max. Marks: 70

Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any THREE Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the following decimal numbers to the bases indicated (4M)
i) 9872 to octal ii) 4689 to hexadecimal
b) What is the use of buffers? Explain about tri-state buffers. (3M)
c) Explain how different instruction formats influence the system. (4M)
d) Explain the concept of partial remainder (4M)
e) List and explain the advantages of virtual memory. (3M)
f) Distinguish isolated and memory mapped I/O (4M)
PART -B
2. a) What is a bus? Explain single bus and multiple bus structure used to interconnect (8M)
functional units in the computer system.
b) Distinguish between error detection and error correction. Explain with an example (8M)
how Hamming code is used for error detection.

3. a) Explain the following with respect to logic micro operations (8M)

i) Selective Set ii) Selective Complement
iii) Selective Clear iv) Mask
b) Explain various computer instruction formats with neat sketches (8M)

4. a) Draw and explain the micro-programmed control unit. (8M)

b) Explain various types of interrupts in detail. (8M)

5. a) Perform the restoring division for the binary numbers 1010 and 11. Draw the (8M)
circuit arrangement for binary division.
b) What are the steps involved in the addition of 2’s complement notation. Explain 8M
with an example.

6. a) A computer system has a MM capacity of a total of 1M 16 bits words. It also has a (8M)
4K words cache organized in the block set associative manner, with 4 blocks per
set & 64 words per block. Calculate the number of bits in each of the TAG, SET &
WORD fields of MM address format.
b) Explain the following (8M)
i) Memory management using segmentation
ii) Memory management using paging

7. a) Explain in detail i) Interrupt ii) An exception with an example (8M)

b) Differentiate serial arbitration logic and parallel arbitration logic with neat (8M)
sketches
WWW.MANARESULTS.CO.IN
1 of 1
|''|'''||''||'''||||
 Code No: R1622054
SET - 4
R16
II B. Tech II Semester Model Examinations, March 2018
Computer Organization
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any THREE Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the number (5675)8 into its decimal and hexadecimal (4M)
b) Discuss on RTL with suitable example. (4M)
c) What do you understand by register stack and memory stack? (3M)
d) Discuss the advantages and disadvantages of micro programmed control unit. (3M)
e) Define i) Memory access time ii) Memory cycle time (4M)
f) Differentiate between tightly coupled systems and loosely coupled systems. (4M)
PART -B
2. a) Describe basic operational concepts of computer in detail (8M)
b) “Parity checking can be used for error detection” – Justify your answer with an (8M)
example.

3. a) Explain the following with neat sketches (8M)

i) 4 – bit Binary adder ii) Binary Adder - Subtractor
b) Explain various phases of instruction cycle with an example (8M)

4. a) Explain how registers are connected to common bus in the computer with a neat (8M)
diagram.
b) What do you mean by addressing mode? Explain the following addressing modes (8M)
with examples.
i) Direct Addressing Mode ii) Immediate Addressing Mode

5. a) Explain subtraction of binary numbers in one’s complement notation with (8M)

examples.
b) Perform the following: (8M)
i) (110.101) 2 = ( )10 ii) (1.10101)2 = ( )10
ii) 1010.01 x 11.1 iv) 110.10 x 10.1

6. a) Explain the following mapping techniques used for cache mapping (8M)
i) Associative mapping cache ii)Direct mapping cache
iii) Block-set-associative mapping cache
b) Write short note on i) Magnetic Disks ii) Magnetic tapes (8M)

7. a) Explain the role of interrupts in Computer Organization. (8M)

b) Discuss the following interconnection structures (8M)
i) Crossbar Switch ii) Hypercube system

1 of 1
WWW.MANARESULTS.CO.IN
|''|'''||''||'''||||
Code No: R1622054 R16 SET - 1

II B. Tech II Semester Regular Examinations, April - 2018

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Write various ways to improve the clock rate. (2M)
b) With an example write about relative addressing. (2M)
c) Differentiate post-indexed and pre-indexed addressing with write back policy. (3M)
d) What is the use of PCI bus in a computer system? (2M)
e) Write the major functionalities of disk controllers? (3M)
f) Explain 3 steps a processor perform to execute instruction. (2M)
PART –B
2. a) What are the functional units of a computer system? Explain the way of (7M)
handling information by each of them.
b) Discuss the generations of computers based on the development technologies (7M)
used to fabricate the processors, memories an I/O units.

3. a) Differentiate the instruction execution for adding ‘n’ numbers using Straight (7M)
line sequencing and branching.
b) Write short notes on shift and rotate instructions. (7M)

4. a) Differentiate relative and absolute addressing modes for branch instructions (7M)
b) What is the format of arithmetic instruction in assembly language? Elaborate (7M)
variants of OP code in it.

5. a) How to meet device characteristics and addressing objectives by USB? (7M)

Explain.
b) Explain the usage of daisy chains and priority in simultaneous interrupt (7M)
handling.

6. a) Write about flash memory and read only memories. Explain their applications. (7M)
b) Write about locality of preference, write-through protocol, copy-back protocol (7M)
and early restart protocol in cache memory.

7. a) Explain the following. (4+5

a) Single bus organization of the data path inside a processor. +5M)
b) Micro program sequencing.
c) Micro instructions with next address field.
1 of 1
WWW.MANARESULTS.CO.IN
|''|'''||''||'''||||
Code No: R1622054 R16 SET - 2

II B. Tech II Semester Regular Examinations, April - 2018

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) What is optimizing compiler? (2M)
b) Write short notes on additional addressing modes. (2M)
c) How to determine branch target address? (2M)
d) Write about the transfer of control between programs through interrupts. (3M)
e) Differentiate logical and physical addresses. (2M)
f) What is micro programmed control and micro routines? (3M)
PART –B
2. a) Write about various general purpose registers involved in the typical computer (7M)
system
b) “System software is responsible for coordination of all activities in a (7M)
computing system”-Justify this statement with the functionalities of it.

3. a) Write about various means by which data are transferred between memory of a (7M)
computer and outside world.
b) Write the subroutines for parameter passing through registers. (7M)

4. a) Write in detail, about register operands, immediate operands and shifted (14M
immediate operands of arithmetic and logic instructions )

5. a) Explain typical read operation with various data transfer signals on the PCI (7M)
bus.
b) Write about two different approaches for bus arbitration. (7M)

6. a) Explain how large storage can be implemented with optical disks. (7M)
b) Discuss the possible methods for specifying the placement of memory blocks (7M)
in cache.

7. a) Explain the following. (4M+

a) Role of MDR in fetching a word from memory. 5M+
b) Control sequence that implements unconditional branch 5M)
instructions.
c) Block diagram of a complete processor.

1 of 1
WWW.MANARESULTS.CO.IN
|''|'''||''||'''||||
Code No: R1622054 R16 SET - 3

II B. Tech II Semester Regular Examinations, April - 2018

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Write a short note on bus structures used in computer system. (2M)
b) Give example for left and right shift operations. (2M)
c) Discuss load/store instructions for multiple operands. (3M)
d) What do you mean by vectored interrupts? (2M)
e) Differentiate static and dynamic RAMs. (2M)
f) Write a short notes on wide-branch addressing (3M)
PART –B
2. a) Explain the importance of instruction set in measuring the performance of a (7M)
computer system.
b) Discuss various computer types with their applications in real world (7M)
environment.

3. a) What is register transfer notation? Write and explain these notations to three- (7M)
address, two-address, single address and zero-address instruction types.
b) Illustrate the concept of assembly directives with an assembly language (7M)
program

4. What are the conditional branch instructions? Explain each with an example (14M)

5. a) What are the main phases involved in the operation of SCSI bus. (7M)
b) List the functionalities of I/O interface. Draw and explain a combined (7M)
input/output interface circuit.

6. a) Relate the access speed, size and cost of various memories in memory (7M)
hierarchy system.
b) “RAID disks offers excellent performance and large &reliable storage”- Justify (7M)
this statement through various levels.

7. Explain the following. (4M+

a) Basic operation of micro programmed control unit. 5M+
b) Input and output gating of ALU. 5M)
c) Storing a word in memory.
WWW.MANARESULTS.CO.IN 1 of 1

|''|'''||''||'''||||
Code No: R1622054 R16 SET - 4

II B. Tech II Semester Regular Examinations, April - 2018

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) What is the use of pipelining and superscalar operations?
(3M)
b) List basic input and output operations.
(2M)
c) Write the instruction format of ARM.
(2M)
d) What is bus arbitration?
(2M)
e) How to encode bits using Manchester encoding?
(2M)
f) Explain basic organization of micro programmed control unit.
(3M)
PART –B
2. a) What is the role of Processor clock, clock rate in the performance of computer (7M)
system? Explain.
b) Suppose two numbers located in memory are to be added. What are the (7M)
functional units of digital computer system will carry out this? Explain how.

3. In how many ways the location of an operand is specified in an instruction? (14M)

Explain each mode with suitable examples.

4. How to perform AND, OR, NAND, NOR and XOR logic instructions? Give (14M)
example

5. a) Discuss the implementation of nested interrupts to handle multiple devices. (7M)

b) Explain the importance of handshake control for data transfer in asynchronous (7M)
bus.

6. a) What are the possible configurations of ROM? Explain with advantages and (7M)
disadvantages
b) Write about organization accessing of data on a disk? Elaborate the role of (7M)
operating systems and disk controllers in it.

7. Explain the following. (5M+

a) Conditional branching micro program. 5M+
b) Vertical /horizontal organization of micro instructions. 4M)
c) Fetching a word from memory.

WWW.MANARESULTS.CO.IN
1 of 1

|''|'''||''||'''||||
Code No: R1622054 R16 SET - 1

II B. Tech II Semester Regular Examinations, November - 2018

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) List the functions of system software? (2M)
b) What is interrupt? How the interrupts are processed? (3M)
c) Write about the fetch routine in symbolic microinstructions. (2M)
d) Explain in detail about stored program concept (3M)
e) List out several of characteristics of multi processors. (2M)
f) Define the Inter Process Arbitration. (2M)
PART -B
2. a) With the help of a diagram, review about Arithmetic logic shift unit. (7M)
b) Describe Selective -Set, Selective - Complement, Selective-Clear and mask (7M)
operation with an example.

3. a) Draw and illustrate the instruction cycle state diagram. (7M)

b) Represent the decimal number 8620 in (i) BCD; (ii) excess-3 (7M)
(iii) 2421 code (iv) As a binary number.

4. a) Arrange the organizations of micro programmed control unit with neat sketch. (7M)
b) Explain the following with respect to stack organization. (7M)
i) Stack Operations ii) Reverse Polish Notation

5. a) Distinguish the following mapping functions (14M)

i) Associative mapping. ii) Direct mapping iii) Set Associative mapping
6. a) Summarize the following secondary storage devices (7M)
i) Magnetic disk. ii) Magnetic tape.
b) Explain how the technique of pegging can be implemented? (7M)

7. a) A two-way set associative cache memory uses blocks of four words. The cache (7M)
can accommodate a total of 2048 words from main memory .the main memory
size is 128K×32.
i) Formulate all pertinent information required to construct the cache memory.
ii) What is the size of the cache memory?
b) Write short notes on Arithmetic pipeline (7M)

WWW.MANARESULTS.CO.IN
1 of 1
|''|'''||''||'''||||
Code No: R1622054 R16 SET - 1

II B. Tech II Semester Regular/ Supplementary Examinations, April/May - 2019

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Define system software.
b) Mention different types of Bus structures.
c) Write about microprogramming.
d) What is an interrupt cycle?
e) What are optical disks?
f) Define hardwired control?
PART –B
2. a) Explain the structure of a computer system.
b) Write about logical structure of a simple personal computer.

3. a) Illustrate with examples logic instruction and shift instructions.

b) What are different addressing modes? Explain.

4. a) Explain the 4 bit binary adder with a diagram.

b) Differentiate between ROM and PROM.

5. a) What is meant by micro-program sequencing? Mention its importance.

b) Write the advantages and usage of universal serial bus(USB).

6. a) Write about basic memory circuits.

b) Write about enabling and disabling interrupts.

7. a) What are magnetic hard disks? Mention the purpose of its usage.
b) What is meant by interleaving? Explain.

1 of 1

|''|'''||''||'''|||| www.manaresults.co.in
Code No: R1622054 R16 SET - 2

II B. Tech II Semester Regular/ Supplementary Examinations, April/May - 2019

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) What is microprocessor, how it is different from micro computer?
b) Write about I/O controller.
c) What is a register transfer language?
d) What is cache memory?
e) What is Direct Memory Access?
f) What are different shift micro-operations?
PART –B
2. a) Explain the organization of a computer system and its input-output processor.
b) Illustrate with examples rotate instruction?

3. a) What are different addressing modes? Explain.

b) Write about real time computers.

4. a) What is instruction cycle? Explain with flowchart.

b) Write the advantages and usage of peripheral component Interconnect Bus?

5. a) What is flash memory, how it is different from cache memory?

b) Mention the standard I/O interfaces and describe the each one.

6. a) Differentiate between virtual memory and main memory.

b) What is micro programmed control?

7. a) Differentiate between EPROM and EEPROM.

b) Write the basic instruction types.

1 of 1

|''|'''||''||'''|||| www.manaresults.co.in
Code No: R1622054 R16 SET - 3

II B. Tech II Semester Regular/ Supplementary Examinations, April/May - 2019

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) What is instruction cycle?
b) Write about hierarchy of memory.
c) Explain the components of the computer system?
d) What is the use of priority interrupts.
e) Differentiate between main memory and cache memory.
f) What are shift micro- operations?
PART -B
2. a) Differentiate between synchronous and Asynchronous modes of data transfer.
b) Explain the basic organization of micro-programmed control unit.

3. a) Explain about associative memory.

b) Explain diary chain priority interrupts.

4. a) Briefly explain various peripheral devices used in computer system.

b) Explain the basic components of memory management unit?

5. a) Differentiate between shift and rotate instructions.

b) Write about optical disks.

6. a) How data transfer can be controlled using handshaking technique?

b) Differentiate between flash memory and cache memory.

7. a) What is interrupt? Explain different types of interrupts.

b) Write about Direct memory Access.

1 of 1

|''|'''||''||'''|||| www.manaresults.co.in
Code No: R1622054 R16 SET - 4

II B. Tech II Semester Regular/ Supplementary Examinations, April/May - 2019

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Write differences between RISC and CISC.
b) Mention the advantages of memory hierarchy?
c) What is micro-operation?
d) What is cache memory? Mention its importance?
e) What are i/o peripherals? Mention its advantages.
f) What is Direct Memory Access?
PART -B
2. a) What is micro operation? Briefly explain the arithmetic micro operation.
b) Explain the organization of registers?

3. a) Explain the function of typical i/p-o/p interfaces.

b) Explain the components of the system.

4. a) Write about logic instruction and its significance.

b) Write about magnetic hard disks.

5. a) Differentiate between peripheral component interconnect (PCI) Bus and

universal serial Bus.
b) Differentiate between EPROM and EEPROM.

6. a) Write about different types of addressing modes.

b) Write about branch instruction and its significance.

7. a) What are different forms of parallelism?

b) What is parity? Give its significance.

1 of 1

|''|'''||''||'''|||| www.manaresults.co.in
Code No: R1622054 R16 SET - 1

II B. Tech II Semester Supplementary Examinations, November - 2019

COMPUTER ORGANIZATION
(Com to CSE, IT, ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Explain different types of data representation? (2M)
b) Differentiate multi computers and multi processors. (2M)
c) Explain with example the implementation of register transfer? (2M)
d) List out addressing modes. (2M)
e) What are memory reference instructions? (2M)
f) Explain about memory interleaving. (4M)
PART -B
2. a) What are the differences between CISC and RISC processors?-Compare. (7M)
b) Represent the number (+46.5)10 as a floating point binary number with 24 bits. (7M)
The normalized fraction mantissa has 16 bits and exponent has 8 bits.

3. a) With the help of the example, explain in detail various types of memory reference (7M)
instructions.
b) Explain 4-bit binary incremented with a circuit diagram to increment 0110. (7M)

4. a) Convert the following numerical arithmetic expression into reverse polish notation (7M)
and show the stack operations for evaluating (3+4) [10(2+6) +8].
b) Illustrate different classes of interrupts. (7M)

5. a) Define addressing mode. Explain different types of Addressing modes. (7M)

b) A two word instruction is stored in memory at an address designated by the (7M)
symbol ‘W’. The address field of the instruction (stored at W+1) is designated by
the symbol ‘Y’. The operand used during the execution of the instruction stored at
an address symbolized by ‘Z’. An index register contains the value ‘X’. State how
‘Z’ is calculated from the other addresses if the addressing mode of the instruction
is 1.Direct 2.Indirect 3.Relative 4.Indexed

6. a) Define Virtual Memory. Explain the process of converting virtual addresses to (7M)
physical addresses with a neat diagram.
b) Differentiate the following (i) Pipeline conflict (ii) Network interlock (7M)

7. a) How the logical address is translated into physical address in paging?-Give details. (7M)
b) Explain about asynchronous data transfer and asynchronous communication (7M)
interface.

1 of 1

||''|''||''|''|||'|| www.manaresults.co.in