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~d Semester B.E. Degree Examination, Dec.2017/Jall',zo 8
" ;~,.Av nal09 and Digital Electronics (ADI;)i~
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Time:' 3 hrs. ~~> ~\~~/ ~
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Note: Answer 6~E full question, choosing one fuD questio j\=q each module .
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1 a. Ex.plain the oper (~~nd :haracteristic.s ofN-channel JFE~T (08 Marks) (S;V.
b. With block diagram, ~)"p1~mthe operation ofa Astable m lV& tor usmg IC 555.
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W. It Circuit iagrarn, ~x~ am tfl~ oyera~lon o. a \ Cia a Ion OSCI,ator.

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a. (~6Mar~)
b. Fig. Q2(b), shows a Biasing co~fj'gl!!:atlon usmg(})~OSFET given that the saturation dram
current is 8mA and the pinch 0~1~~~ is -~\}_\
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Determine the value o,(rilite1iource voltage drain current of:.t1ra:i~ource voltage. (06 Marks)
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c. Write the advantages of-J~SFET over JFET. '\::,---;/::'\ (04 Marks)
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3 a. Give the si~
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)ogic circuit for following logic equation whereQ -r~sents don't care
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condition f~~}iawing locations:


. ~(1i~ D).= Im(7) + d (10, .II, 12, 1~, 14, 1.5). (06 Mar~) ~(ckl
b. StmphP?)h 'followl~g Boolean function by usmg Qume - McClusky met~fO $") .
F~,;~,C, D) - Im (0,2,3,6, 7, 8, 10, 12, 13). .c-: (10 Marks)
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o a1--~'Vhai are Hazards? Explain the types of Hazards and it covers. (~}S)
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b";'---f:.)iscussBriefly an HDL Implementation models. (~~'rks)
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C. Explain the concept of Duality in Digital circuits. (04 Marks)


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5 a. Wh~\lltiplexer? Design a 32:1 multiplexer using 16:1 MUX and o~,~tmultiplexer,
\~) , i.,::;<:~~. (05 Marks)
b. Show l1OYVlus~ga 3 to 8 Decoder and multi input OR Gates follow~{~,~olean Expressions

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can be rd('l~~~ultaneously. (6\-:,,'--' (06 Marks)
F(A, B, C) dv~»_~O,4, 6) , '-~(,' ;
F(A, B, C) = 2#-W?'
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F(A, B, C) = ~)1~~f,5~ (~'\
c. Show how two 1'ttrJ 6 9fMUX can be connected to get 1 ~DEMUX. (05 Marks)
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6 a. Explain parity Generatori'a(ddbeckers using suitablC';~amples, (05 Marks)


b. What is Magnitude Compar'at~t'? Explain 1 bit magn.n.~~'ecomparator. (05 Marks)

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c. What is PLA? Design seven sew~ Display usijig,l>,LA. (06 Marks)
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7 a.
b.
Explain 4 bit serial in parallel out re~T.~>·,) (04 Marks)
Explain a 3 bit binary Ripple up counter~(Give the block diagram, truth table and output
waveforms. !'-::::::-,'> \'-:> (06 Marks) ib
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c. Explain the working of JK master S:l<Ni-fhp,):-,U5'p along with implementation using NAND
Gates. "' < .;,;::;' (06 Marks) t'~ ! "

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8 a. Design synchronous MOD ~cbunter with truth ta~Ie:~~tate diagram, (06 Marks)
b. What is universal shift ~¥~T1 Explain any one apPliq,air~n.,)ofuniversal shift register with
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blo~k diagram an~ tru~~~' -; :-_-;~' (06 Marks)


c. Write the compaTIsoQ"1Set\~eenSynchronous and Asynchro'n6us-counter. (04 Marks)
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9 a. Expla~ 5 ?it ~~iYe divider with ?iagr~m.. . . '- «,-j (06 Marks)
b. Expla~n wrt~o~~~1ilagram the working principle of Digital clock. \\.:.i (05 Marks)
Explam ths::, ~1'S' Accuracy and Resolution for D/A converter. (:(V.,
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c. (05 Marks)

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10 Ex~~~1th Block diagram the operation of successive approximation conve~~J:.')~8 Marks)


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