Practice QB#1

ECE213: DELD
A quantity having continuous values is
(A) A digital quantity (B) an analog quantity (C) a binary quantity (D) none of them

Ans: B

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The term bit means

(A) A small amount of data (B) a 1 or a 0 (C) binary digit (D) both B and C

Ans: D

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The time interval on the leading edge of a pulse between 10% and 90% of the
amplitude is the

(A) rise time (B) fall time (C) pulse width (D) period

Ans: A
A pulse in a certain waveform occurs every 10 ms. The frequency is
(A) 1 kHz (B) 1 Hz (C) 100 Hz (D) 10 Hz

Answer: C

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In a certain digital waveform, the period is twice the pulse width. The duty cycle
is,

(A) 100% (B) 200% (C) 50% (D) 25%

Answer: C

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An inverter
(A) performs the NOT operation (B) changes a HIGH to a LOW (C) changes a
LOW to a HIGH (D) Does all of the above

Answer: D
The output of an AND gate is HIGH when
(A) Any input is HIGH (b) all inputs are HIGH (C) no inputs are HIGH (D) both
answers A and B

Solution: B
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The output of an OR gate is HIGH when

(A) Any input is HIGH (b) all inputs are HIGH (C) no inputs are HIGH (D) both
answers A and B

Answer: D
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The device used to convert a binary number to a 7-segment display format is the

(A) Multiplexer (B) encoder (C) decoder (D) register

Answer: C
An example of a data storage device is
(A) the logic gate (B) the flip-flop (C) the comparator (D) the register (E) both B
and D.

Answer: E
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A fixed-function IC package containing four AND gates is an example of
(A) MSI (B) SMT (C) SOIC (D) SSI

Answer: D
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An LSI device has a circuit complexity of form
(A) 10 to 100 equivalent gates (B) more than 100 to 10,000 equivalent gates (C)
2000 to 5000 equivalent gates (D) more than 10,000 to 100,000 equivalent gates

Answer: D
VHDL is a
(A) logic device (B) PLD programming language (C) computer language (D) very
high density logic

Answer: B
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A CPLD is a

(A) Controlled program logic device (B) complex programmable logic driver (C)
complex programmable logic device (D) central processing logic device

Answer: C
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An FPGA is a
(A)Field programmable gate array (B) fast programmable gate array (C) field
programmable generic array (D) flash process gate application

Answer: A
The binary number (1101) is equal to the decimal number
(A) 13 (B) 49 (C) 11 (D) 3
Answer: A
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The sum of 11010 + 01111 equals
(A) 101001 (B) 101010 (C) 110101 (D) 101000
Answer: A
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The difference of 110 – 010 equals
(A) 001 (B) 010 (C) 101 (D) 100
Answer: D
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The 1’s complement of 10111001 is
(A) 01000111 (B) 01000110 (C) 11000110 (D) 10101010
Answer: B
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The 2’s complement of 11001000 is
(A) 00110111 (B) 00110001 (C) 01001000 (D) 00111000
Answer: D
The decimal number +122 is expressed in the 2’s complement form as
(A) 01111010 (B) 11111010 (C) 01000101 (D) 10000101
Answer: A
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The decimal number -34 is expressed in the 2’s complement form as
(A) 01011110 (B) 10100010 (C) 11011110 (D) 01011101
Answer: C
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In the 2’s complement form, the binary number 10010011 is equal to the decimal number
(A) -19 (B) +109 (C) +91 (D) -109
Answer: D
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The binary number 101100111001010100001 can be written in octal as
(A) (5471230)8 (B) (5471241)8 (C) (2634521)8 (D) 23162501)8
Answer: B
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The binary number 10001101010001101111 can be written in hexadecimal as
(A) (AD467)16 (B) (8C46F)16 (C) (8D46F)16 (D) (AE46F)16
Answer: C
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The binary number for (F7A9)16 is
(A) 1111011110101001 (B) 11101111101001 (C) 1111111010110001 (D)
11110111010101001
Answer: A
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The BCD number for decimal 473 is
(A) 111011010 (B) 110001110011 (C) 010001110011 (D) 010011110011
Answer: C
 Unit 2: Gates
When the input to an inverter is HIGH (1), the output is
(A) HIGH or 1 (B) LOW or 1 (C) HIGH or 0 (D) Low or 0
Answer: D
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An inverter performs an operation known as
(A) Complementation (B) assertion (C) inversion (D) both A and C
Answer: D
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The output of an AND gate with inputs A, B, and C is a 1 (HIGH) when
(A) A = 1, B = 1, C = 1 (B) A = 1, B = 0, C = 1 (C) A = 0, B = 0, C = 0, (D) None of them
Answer: A
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The output of an OR gate with inputs A, B, and C is a 1 (HIGH) when
(A) A = 1, B = 1, C = 1 (B) A = 0, B = 0, C = 1 (C) A = 0, B = 0, C = 0 (D) Answers A, B and C
Answer: C
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The complement of a variable is always
(A) 0 (B) 1 (C) equal to the variable (D) The inverse of the variable
Answer: D

The Boolean expression ABCD is

(A) A sum term (B) A product term (C)A literal term (D) Always 1
Answer: B

According to the commutative law of addition,

(A) AB = BA (B) A = A + A (C) A + (B + C) = (A + B) + C (D) A + B = B + A
Answer: D

According to the associative law of multiplication,

(A) B = BB (B) A(BC) = (AB)C (C) A + B = B + A (D) B = B(B + 0)
Answer: B

According to the distributive law,

(A) A(B + C) = AB + AC (B) A(BC) = ABC (C) A(A + 1) = A (D) A + AB = A
Answer: A
Which one of the following is not a valid rule of Boolean algebra?
(A) A + 1 = 1 (B) A = Ā (C) AA = A (D) A + 0 = A
Answer: B

A 3-variable Karnaugh map has

(A) Eight cells (B) three cells (C) sixteen cells (D) four cells
Answer: A

In a 4-variable Karnaugh map, a 2-variable product term is produced by

(A) A 2-cell group of 1s (B) an 8-cell group of 1s (C) a 4-cell group of 1s (D) a 4-cell
group of 0s
Answer: c

On a Karnaugh map, grouping the 0s produces

(A) a product-of-sums expression (B) a sum-of-products expression (C) a “don’t care”
condition (D) AND-OR logic
Answer: A
Which of the following rules states that if one input of an
AND gate is always 1, the output is equal to the other input?

(A)A+1 = 1 (B) A + A = A (C) A.A = A (D) A.1 = A

Answer: D

The Boolean expression X = AB + CD represents

(A) Two ORs ANDed together (B) A 4-input AND gate (C) two
ANDs ORed together (D) an exclusive-OR
Answer: C

A 5-variable Karnaugh map has

(A) Sixteen cells (B) thrity-two cells (C) sixty-four cells (D)
None of these
Answer: B
An example of a sum-of-products expression is
(A) A + B(C+D) (B) A’B’ + AC’ + AB’C (C) (A’+B+C)(A+B’+C) (D) both answers A and B
Answer: B

Boolean algebra can be used to

(A) Simplify any algebraic expressions (B) Minimize the number of switches in a circuits (C) Solve the
mathematical problem (D) Perform arithmetic calculation
Answer: A

An inverter gates can be developed using

(A) Two diodes (B) A resistance and capacitance (C) A transistor (D) An inductance and capacitance
Answer: C

If an input A is given to an inverter, the output will be

(A) 1/A (B) 1 (C) A (D) None of these

The minterm designator of the term A’BCD is

(A) 4 (B) 5 (C) 11 (D) None of these
Answer C

The maxterm designator of the term A’+B’+C+D’ is

(A) 2 (B) 13 (C) 10 (D) None of these
Answer: A
A logic circuit with an output X = AB’C + AC’ consists of

(A) Two AND gates and one OR gate (B) Two AND gates, one OR gate, and two inverters (C) Two
OR gates, one AND gate, and two inverters (D) Two AND gates, one OR gate, and one inverter

Ans: B
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To implement the expression A’BCD + AB’CD + ABC’D’, it takes one OR gate and
(A) One AND gate (B) Three AND gates (C) Three AND gates and four inverters (D) Three AND
gates and three inverters.

Ans: C
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The output expression for an AND-OR circuit having one AND gate with inputs A, B, C, and D
and one AND gate with inputs E and F is

(A) ABCDEF (B) A + B + C + D + E + F (C) (A + B + C + D)(E + F) (D) ABCD + EF

Ans: D
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The expression A’BCD + ABCD’ + AB’C’D
(A) Cannot be simplified (B) Can be simplified to A’BC + AB’ (C) Can be simplified to ABCD’ + A’BC’ (D) None of these
answers is correct.

Ans: A
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The AND operation can be produced with
(A) Two NAND gates (B) Three NAND gates (C) One NOR gate (D) Three NOR gates

Ans: A
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The OR operation can be produced with

(A) Four NOR gates (B) Three NAND Gates (C) Four NAND gates (D) Both answers (A) and (B)

Ans: D
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When using dual symbol in a logic diagram.
(A) Bubble outputs are connected to bubble inputs (B) The NAND symbols produce the AND operations (C) The
negative-OR symbols produce the OR operations (D) All of these answers are true

Ans: D
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All Boolean expressions can be implemented with
(A) NAND gates only (B) NOR gates only (C) Combinations of NAND and NOR gates (D) All of them

Ans: D
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A half-adder is characterized by
(A) Two inputs and two outputs (B) Three inputs and two outputs (C) Two inputs and three
outputs (D) Two inputs and one output

Ans: A

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A full-adder is characterized by
(A) Two inputs and two outputs (B) Three inputs and two Outputs (C) Two inputs and three
outputs (D) Two inputs and one output

Ans: B
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3. The inputs to a full-adder are A = 1, B = 1, Cin = 0. The outputs are
(A) Sum = 1, Cout = 1 (B) Sum = 1, Cout = 0 (C) Sum = 0, Cout = 1 (D) Sum = 0, Cout = 0

Ans: C
4. A 4-bit parallel adder can add
(A) Two 4-bit binary numbers (B) Two 2-bit binary numbers (C) Four bits at a time (D) Four bits in sequence

Ans: A
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To expand a 4-bit parallel adder to an 8-bit parallel adder, you must

(A) Use four 4-bit adders with no interconnections (B) Use two 4-bit adders and connect the sum outputs of
one to the bit inputs of the other (C) Use eight 4-bit adders with no interconnections (D) Use two 4-bit
adders with the carry output of one connected to the carry input of the other

Ans: D
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If a 74HC85 magnitude comparator has A = 1011 and B = 1001 on its inputs, the outputs are
(A) A > B = 0, A < B = 1, A = B = 0 (B) A > B = 1, A < B = 0, A = B = 0 (C) A > B = 1, A < B = 1, A = B = 0 (D) A > B =
0, A < B = 0, A = B = 1

Ans: B

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If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what are the
inputs?

(A) A3A2A1A0 = 1010 (B) A3A2A1A0 = 1110 (C) A3A2A1A0 = 1100 (D) A3A2A1A0 = 0100

Ans: C
A BCD – to – 7 segment decoder has 0100 on its inputs. The active outputs are
(A) a, c, f, g (B) b, c, f, g (C) b, c, e, f (D) b, d, e, g

Ans: B
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If an octal-to-binary priority encoder has its 0. 2. 5, and 6 inputs at the active level, the active- HIGH binary output is

(A) 110 (B) 010 (C) 101 (D) 000

Ans: A
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In general, a multiplexer has

(A) One data input, several data outputs, and selection inputs (B) One data input, one data output, and one selection input (C) Several data inputs,
several data outputs, and selection inputs (D) Several data input, one data output, and selection inputs

Ans: D

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Data selectors are basically the same as

(A) Decoders (B) De-Multiplexers (C) Multiplexers (D) Encoders

Ans: C

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Which of the following codes exhibit even parity?

(A) 10011000 (B) 01111000 (C) 11111111 (D) both (B) and (C)

Ans: D
A very large scale integration VLSI chip has
(A) 12 to 99 gates (B) 10,000 to 99,999 gates (C) More than 100,000 gates (D) 100 to 0,000 gates

Answer: B
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A RTL consists of
(A) Resistor, Transistor and inductors (B) Resistors, diodes and bipolar junction transistor (C)
Resistors, capacitors and diodes (D) Resistors and transistors

Answer: D
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Which of the following logic family dissipates minimum power?
(A) CMOS (B) ECL (C) TTL (D) DTL
Answer: A

Which of the logic family has complementary outputs?

(A) CMOS (B) PMOS (C) I square L (D) ECL

Answer: D