Experiment No: 01

Experiment Name: Introduction to DSCH and MICROWIND softwares.

Objectives:

 To know about the simulation softwares DSCH and MICROWIND.

 To know how to use the symbols within the softwares to design logic circuit and layout.

Theory:

DSCH Software: DSCH is a software for logic design. Based on primitives, a hierarchical
circuit can be built and simulated. It also includes delay and power consumption evaluation.
With the help of this software one can implement digital circuits at its basic gate primitives or
at its transistor level.

The DSCH program is a logic editor and simulator. DSCH is used to validate the architecture
of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly
environment for hierarchical logic design, and fast simulation with delay analysis, which
allows the design and validation of complex logic structures. DSCH also features the symbols,
models and assembly support for 8051 and PIC16F84 controllers. Designers can create logic
circuits for interfacing with these controllers and verify software programs using DSCH.
Following figure shows the DSCH3 user interface.

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 Figure: DSCH3 user interface and Symbol Library

Features:

 User-friendly environment for rapid design of logic circuits.

 Supports hierarchical logic design.
 Added a tool on fault analysis at the gate level of digital. Faults: Stuck-at-1, stuck-at-
0.The technique allows injection of single stuck-at fault at the nodes of the circuit.
 Improved interface between DSCH and Winspice.
 Handles both conventional pattern-based logic simulation and intuitive on screen
mouse-driven simulation.
 Built-in extractor which generates a SPICE netlist from the schematic diagram
(Compatible with PSPICETM and WinSpiceTM).
 Generates a VERILOG description of the schematic for layout conversion.
 Immediate access to symbol properties (Delay, fanout).
 Model and assembly support for 8051 and PIC 16F84 microcontrollers.
 Sub-micron, deep-submicron, nanoscale technology support.
 Supported by huge symbol library.

How to simulate DSCH?

 Select the foundry using the command File > Select Foundry Select 0.25-micron
process by selecting “cmos025.tec” file. Click Open tab to continue.
 Save the design as “Lab01” using the command File > Save as.
 Click on the Run Tab on the Tool bar menu to start the simulation or using the command
 Simulate > Start Simulation.

Symbol Library:

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There are two types of symbol libraries. One is used for Basic circuits and another is for
Advanced circuits design.

MICROWIND Software: The Microwind software allows the designer to simulate and design
an integrated circuit at physical description level. Born in Toulouse (France), Microwind is an
innovative CMOS design tool for educational market.

Microwind is developed as comprehensive package on windows platform to enable students to

learn smart design methods and techniques with more practice. With inbuilt layout editing
tools, mix-signal simulator, MOS characteristic viewer and more, it allows students to learn
complete design process with ease.

Microwind unifies schematic entry, pattern based simulator, SPICE extraction of schematic,
Verilog extractor, layout compilation, on layout mix-signal circuit simulation, cross sectional
& 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and sign-off correlation to
deliver unmatched design performance and productivity.

With its approach for CMOS design education, Microwind has gained lot followers worldwide.
Universities across the globe are using Microwind for budding engineers to teach CMOS
concepts with ease. Following figure shows the MICROWIND 2 user interface:

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 Figure: MICROWIND 2 user interface and Palette.
Features:

 Microwind editor: We may edit boxes, using a palette of layers. We may cut, past,
duplicate, generate matrix of layout, use the layout editor to insert contacts, MOS
devices, pads, complex contacts and path in one single click.
 Microwind 2D viewer: Use the 2D viewer to see the cross-section of the fabricated
integrated circuits.
 Microwind 3D viewer: Use this 3D viewer to see the step-by-step fabrication of any
portion of layout.
 Interactive 3D views: Impressive animated 3D views of the layout are now available
in Microwind3.1 through the new command "3D view of the IC".

How to simulate Microwind?

 Start Microwind2. By default the software is configured with 0.25μm technology. Click
“File -> Open”.
 Select “INV3”. Click “Simulate-> Start Simulation”. The oscillation figure appears.
 Click “Close”.
 Click “File -> Select Foundry”. Click “cmos08.rul”.

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  Run again the simulation. Observe the change of VDD and the slowdown of the
oscillating frequency.

Palette:

The Palette is just like the symbol library. Using this library we can draw stick diagram of logic
circuits.

Discussion: We have learnt several features of DSCH and MICROWIND software and also
learnt how to work with these simulators.

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Experiment No: 02

Experiment Name: Design a CMOS NOT, NAND, NOR logic gate using simulator DSCH
and show layout using MICROWIND.

Objectives:

The objective of this experiment is to implement CMOS NOT, NAND, NOR gate using DSCH
and MICROWIND.

Theory:

The structure of a CMOS logic gate is based on complementary networks of n-channel and p-
channel MOS circuits. Recall that the pMOS switch is good at passing logic signal '1', while
nMOS switches are good at passing logic signal '0'.

NOT gate: The CMOS NOT design is detailed in the following figure. Here one p-channel
MOS and one n-channel MOS transistors are used as switches. The channel width for pMOS
devices is set to twice the channel width for nMOS devices.

When the input signal is logic 0, the nMOS is switched off while the PMOS passes VDD
through the output, which turns to 1. When the input signal is logic 1.the pMOS is switched
off while the nMOS passes VSS to the output, which goes back to 0. In that simulation, the
MOS is considered as a simple switch. The n channel MOS symbol is a device that allows the
current to flow between the source and the drain when the gate voltage is "1".

Figure: Symbol, Truth Table and CMOS NOT gate

Working procedure:

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  Opening Dsch3.exe.
 Selecting the nNMOS transistor from Symbol Library on top right and dragging
it to the main screen.
 Selecting the nNMOS transistor from Symbol Library on top right and dragging
it to the main screen.
 Similarly selecting supply and ground symbols from Symbol Library and dragging
them to the main screen.
 Connecting all symbols as shown in the figure, We can use Add a line
command to connect different nodes of these symbols
 Adding a Button Symbol to the input and Light symbol to the output of the circuit
from Symbols library.
 This completes schematic entry.

Logic circuit of the CMOS NOT gate:

Figure: CMOS NOT gate logic circuit in DSCH

The logic simulation of the NOT gate:

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 Figure: Logic simulation of CMOS NOT gate in DSCH

The layout of CMOS NOT gate looks like as follows:

Figure: Layout of CMOS NOT gate in Microwind

NAND gate: A NAND gate can be implemented using four FETS i.e. two pFETs and two
nFETs as the inputs of the gate is two. pFETs are connected in parallel while nFETs are
connected in series, Vdd is supplied to the parallel combination of pFETs while the series
combination of nFETs is grounded. Inputs a & b are applied to the gate terminals of all FETs,
and the output f is obtained from the common junction of these series and parallel combinations
as illustrated in NAND circuit.

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 Figure: Symbol, Truth Table and CMOS Circuit of NAND gate

Logic circuit of the CMOS NAND gate:

Figure: CMOS NAND gate logic circuit in DSCH

The logic simulation of the NAND gate:

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 Figure: Logic simulation of NAND gate in DSCH

The layout of CMOS NAND gate looks like as follows:

Figure: Layout of CMOS NAND gate

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NOR gate: The two-input NOR gate shown on the left is built from four transistors. The
parallel connection of the two n-channel transistors between GND and the gate-output ensures
that the gate- output is driven low (logical 0) when either gate input A or B is high (logical 1).
The complementary series-connection of the two transistors between VCC and gate-output
means that the gate-output is driven high (logical 1) when both gate inputs are low (logical 0).

Figure: Symbol, Truth Table and CMOS Circuit of NOR gate

Logic circuit of the CMOS NOR gate:

Figure: Logic circuit of CMOS NOR gate in DSCH

The logic simulation of the NOR gate:

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 Figure: Logic simulation of CMOS NOR gate in DSCH

The layout of CMOS NOR gate looks like as follows:

Figure: Layout of CMOS NOR gate in Microwind

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Discussion: We have completed this experiment satisfactorily. We have learnt about the
CMOS NOT, NAND and, NOR gates. We have learnt how to draw and simulate these in Dsch
and Microwind.

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