Ldic Lab Manual

KIT-EEE-III SEMESTER LDIC LAB Page 1
EX.
EX. NO:
NO: -- DATE:-
DATE:-
STUDY
STUDY OF
OF LOGIC
LOGIC GATES
GATES
AIM:-
To verify the truth table of the following gates OR gate, AND gate, NOT gate, NAND gate, NOR gate,
EX-OR gate.
APPARATUS REQUIRED:-
SL.No. EQUIPMENT RANGE / QUANTITY
TYPE
1. DC Power Supply (0-5) V 1
2. Resistor 330 Ω 1
3. OR gate (IC 7432) - 1
4. AND gate (IC 7408) - 1
5. NOT gate (IC 7404) - 1
6. NAND gate (IC 7400) - 1
7. NOR gate (IC 7402) - 1
8. EX-OR gate (IC 7486) - 1
9. LED - 1
10. Bread Board - 1
THEORY:-
OR GATE(IC 7432):-
The OR gate performs logical addition, OR gate with two inputs as X and Y has output F is given
by the Boolean expression F=X+Y. here (+) is the OR operator. In this gate pin-1 and pin-2 are taken as input
and pin-3 are taken as output OR otherwise select the input and output pin. If pin-14 is connected to 5V and
pin-7 is connected to ground. Output of all possible input condition where as an OR gate output goes high
when any input is high or both inputs are high and output is low both inputs are low. The same operation is
characteristics of OR Gates with more than two inputs.

AND GATE (IC 7408):-
The AND gate performs logical multiplication considering, the OR gate with two inputs as X and
Y has output F is given by the Boolean expression F=X∙Y. here (∙) is the AND operator. In this gate pin-1 and
pin-2 are taken as input and pin-3 are taken as output (OR) otherwise select the input and output pin. If pin-
14 is connected to 5V and pin-7 is connected to ground. Output of all possible input condition where as an
AND output goes low when any input is high or both inputs are zero and output is high both inputs are high.
The same operation is characteristics of AND Gates with more than Two inputs.
NOT GATE(IC 7404):-
The NOT gate performs an inversion or complement and hence it is called as an inverter. NOT gate
always has a single output and hence the output is always in implement to that of input which is given by the
Boolean expression F = X .In this gate pin-1 is taken as input and pin-2 is taken as output (OR) otherwise
select the input and output pin. If pin-14 is connected to 5V and pin-7 is connected to ground.
NAND GATE(IC 7400):-
It is a combination of AND gate and NOR gate. The NAND gate with two inputs X and Y has
output F is given by the Boolean expression F=X·Y. In this gate pin-1 and pin-2 are taken as input and pin-3
are taken as output (OR) otherwise select the input and output pin. If pin-14 is connected to 5V and pin-7 is
connected to ground. Output of all possible input condition where as an NAND gate output goes high when
any input is high or both inputs are low and output is high both inputs are low. The same operation is
characteristics of NAND Gates with more than two inputs.
NOR GATE(IC 7402):-
The NOR gate operations like an OR gate felt owned by an inverter. The NOR gate output is exact
the inverse of the OR gate. The NOR gate with two inputs X and Y has output F is given by the Boolean
expression F= X+Y. In this gate pin-2 and pin-3 are taken as input and pin-1 are taken as output (OR)
otherwise select the input and output pin. If pin-14 is connected to 5V and pin-7 is connected to ground.
Output of all possible input condition where as an NOR gate output goes low when any input is high or both
inputs are high and output is high both inputs are low. The same operation is characteristics of OR Gates with
more than two inputs.
EX-OR GATE(IC 7486):-
In this gate pin-1 and pin-2 are taken as input and pin-3 are taken as output (or) otherwise select
the input and output pin. If pin-14 is connected to 5V and pin-7 is connected to ground. Output of all possible
input condition where as an EX-OR gate output goes low both inputs are same and output goes high when
any input is high.

EX-NOR GATE:-
In this gate pin-1 and pin-2 are taken as input and pin-3 are taken as output (or) otherwise select
the input and output pin. If pin-14 is connected to 5V and pin-7 is connected to ground. Output of all possible
input condition where as an EX-NOR gate output goes high both inputs are same and output goes low when
any input is high.
PROCEDURE:-
1. The connections are given as per the circuit diagram.

2. When the supply (VCC) is given it is taken to HIGH (‘1’) and when it is cut-off (Ground) it is taken as
LOW (‘0’).
3. The input is given as truth table and output is verified, if LED glows it indicates ‘1’ or if not LED
glows it indicates ‘0’
4. The same procedure is following for all the gates.

EX NOR(IC 7486 & IC 7404):-
TRUTH TABLE: - K MAP:-
INPUT OUTPUT B
A B A B
0 0 1
0 1 0
1 0 0
1 1 1
Y= A B
RESULTS:-
Thus the truth table of OR GATE, AND GATE, NOT GATE, NAND GATE, NOR GATE, EX-OR GATE was
verified

CIRCUIT DIAGRAM:

EXPT NO : 2 DESIGN & IMPLEMENTATION OF
BOOLEAN FUNCTIONS

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DATE :
DESIGN
DESIGN &
& IMPLEMENTATION
IMPLEMENTATION OF
OF BOOLEAN
BOOLEAN FUNCTIONS
FUNCTIONS
AIM:
To design the logic circuit and verify the truth table of the
given Boolean expression, F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9,
10)
APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY

1. Digital IC trainer kit - 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. Connecting wires As required
PROCEDURE:
1. Connections are given as per the circuit diagram
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the given Boolean
expression.

DESIGN:
Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
TRUTH TABLE:
INPUT OUTPUT
S.No A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0
The output function F has four input variables hence a four variable
Karnaugh Map is used to obtain a simplified expression for the
output as shown,
From the K-Map,

F = B’ C’ + D’ B’ + A’ C’ D
Since we are using only two input logic gates the
above expression can be re-written as, F = C’ (B’ + A’
D) + D’ B’
Now the logic circuit for the above equation can be drawn.
KIT-EEE-III SEMESTER LDIC LAB

Page 12
RESULT:
The truth table of the given Boolean expression was verified.
KIT-EEE-III SEMESTER LDIC LAB

Page 13
EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN &
& IMPLEMENTATION
IMPLEMENTATION OF
OF ADDER/
ADDER/ SUBTRACTOR
SUBTRACTOR CIRCUITS
CIRCUITS
AIM:-
To design and implement of combinational circuits (half adder, full adder, half
subtractor and full subtractor) using logic gates and verify its truth table.
SL.No. EQUIPMENT RANGE / TYPE QUANTITY

1. Digital IC trainer kit - 1
3. LED - 2
4. OR gate (IC 7432) - 1
5. AND gate (IC 7408) - 1
6. NOT gate (IC 7404) - 1
7. EX OR gate(IC 7486) - 1
8. Connecting wires - As required
THEORY:-
HALF ADDER:-
Combinational circuits that perform the addition of two bits is called as half
adder. The input variables A and B are added and the output variables are sum and
carry. The simplified SOP versions of half adders are
Sum = A’B + B’A = A  B

Carry = AB
FULL ADDER:-
A Combinational circuit that performs addition of three bits is called full added.
The SOP expressions are,
Sum = A’B’C+A’BC’+AB’C+ABC = A  B  C
Carry = AB+BC+CA
HALF SUBTRACTOR:-
A half subtractor is a combination circuit that subtractor two bits and produces
their difference and borrow.

Difference = A’B + B’A = A  B
Borrow = A’B
FULL SUBTRACTOR:-
A full subtractor is a combination circuit that subtractor three bits and produces
their difference and borrow.
Difference = A’B’C+A’BC’+AB’C+ABC = A  B  C
Borrow = A’B + A’C +BC
LOGIC DIAGRAM:
HALF ADDER
TRUTH TABLE:
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-Map for SUM: K-Map for CARRY:
SUM = A’B + AB’ CARRY = AB
LOGIC DIAGRAM:
FULL ADDER

FULL ADDER USING TWO HALF ADDER
TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC
K-Map for CARRY:
CARRY = AB + BC + AC
LOGIC DIAGRAM:
HALF SUBTRACTOR
TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
K-Map for DIFFERENCE:
DIFFERENCE = A’B + AB’
K-Map for BORROW:
BORROW = A’B
LOGIC DIAGRAM:
FULL SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC
K-Map for Borrow:
Borrow = A’B + BC + A’C
PROCEDURE:-
1. The connections are given as per the circuit diagram.

2. When the supply (VCC) is given it is taken to HIGH (‘1’) and when it is cut-off
(Ground) it is taken as LOW (‘0’).
3. The input is given as truth table and output is verified, if LED glows it indicates
‘1’ or if not LED glows it indicates ‘0’.
4. The same procedure is following for all the functions.

RESULTS:-
Thus the truth table of half adder, full adder, half subtractor and full subtractor
using logic gates was constructed and verified.
 B
EX.
EX. NO:
NO: -- 1 DATE:-
DATE:-
DESIGN
DESIGN AND
AND IMPLEMENTATION
IMPLEMENTATION OF
OF CODE
CODE CONVERTORS
CONVERTORS
AIM:-
To design and implement 4-bit
1. Binary to gray code converter
2. Gray to binary code converter
3. BCD to excess-3 code converter
4. Excess-3 to BCD code converter
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. Connecting wires - As required
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this
circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE:
| Binary input | Gray code output
|
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-Map for G3:
G3 = B3
K-Map for G2:

K-Map for G1:
K-Map for G0:

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE:
| Gray Code | Binary Code
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:
B3 = G3
K-Map for B2:
K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:
| BCD input | Excess – 3 output
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map for E3:
E3 = B3 + B2 (B0 + B1)
K-Map for E2:
K-Map for E1:

K-Map for E0:
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:
| Excess – 3 Input | BCD Output
X1 X2 X4 E0 A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map for A:
A = X1 X2 + X3 X4 X1
K-Map for B:

K-Map for C:

K-Map for D:
PROCEDURE:
i. Connections were given as per circuit diagram.
ii. Logical inputs were given as per truth table
iii. Observe the logical output and verify with the truth tables.

RESULT:-
Thus binary code is converted into gray code and vice versa using logic gates and
output was verified using corresponding truth table.
CIRCUIT DIAGRAM:-
PARITY GENERATOR:-

TRUTH TABLE: - K – MAP:-
D2 D3
INPUT OUTPUT
D1 00 01 11 10
0 1 1
D1 D2 D3 P
1 1 1
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0 P = D1  D2 
1 0 0 1 D3
1 0 1 0
1 1 0 0
1 1 1 1

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND
AND IMPLEMENTATION OF PARITY GENERATOR AND PARITY
PARITY
CHECKER
CHECKER
AIM:-
To design and implement of parity generator and parity checker using logic gates
and to verify the truth table.

TYPE
3. LED - 1
4. EX-OR gate (IC 7486) - 1
5. Bread Board - 1
THEORY:-
The circuit that generates the parity bit in the transmitter is called parity
generator. The circuit that checks the parity bit in the receiver is called parity checker.
Exclusive - OR functions are very useful in systems requiring error detection and
correction codes. A parity bit is used for the purpose of detecting errors during
transmission of binary information.
A parity bit is an extra bit included with a binary message to make a number of
1's either odd or even. The message, including the parity bit, is transmitted and then
checked at the receiving end for errors. An error is detected if the checked parity does not
correspond with the one transmitted.
PROCEDURE:-
1. The circuit connections are given as per the circuit diagram.

2. Give the input as per the truth table.
3. Verify the output by using the truth table.
CIRCUIT DIAGRAM:-
PRAITY CHEKER:-

TRUTH TABLE: -
RESULT:-
Thus the parity generator and parity checker circuits

are designed and was verified the truth table.
ENCODER:-
CIRCUIT DIAGRAM:-

Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7
IC7432
1
3 LED
2
IC7432
1 R= 220Ω
3
IC7432 2
1
3 A = Y4 + Y 5+ Y 6 + Y 7
2
GND
IC7432
1
3 LED
2
IC7432
1 R= 220Ω
3
IC7432 2
1
3 B = Y2+Y3+ Y6+Y7
2
GND
IC7432
1 LED
3
2 IC7432
1 R= 220Ω
3
2
IC7432
1 C= Y1 + Y3+ Y5 +Y 7
3
2
GND
TRUTH TABLE:-
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND
AND IMPLEMENTATION
IMPLEMENTATION OF
OF ENCODER
ENCODER AND
AND DECODER
DECODER
AIM:-
To design and implement encoder and

decoder using logic gates.
S.No. EQUIPMENT RANGE / QUANTITY

TYPE
3. LED - 4
4. Not gate (IC 7404) - 1
5. OR gate (IC 7432) - 3
6. 3 Input NAND gate(IC 7410) - 1
7. Bread Board - 1
THEORY:-
ENCODER:-
An encoder is digital circuits that perform

inverse operation of a decoder. An encoder has 2n
input lines and n output lines. In encoder the output
lines generates the binary code corresponding to the
input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that
generate the corresponding binary code. In encoder it
is assumed that only one input has a value of one at
any given time otherwise the circuit is meaningless.
That when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0 = 1.

DECODER:-
CIRCUIT DIAGRAM:-
TRUTH TABLE:-
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

DECODER:-
A decoder is a multiple input multiple

output logic circuit which converts coded input into
coded output where input and output codes are
different. The input code generally has fewer bits
than the output code. Each input code word produces
a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block
diagram of decoder circuit the encoded information
is present as n input producing 2 n possible outputs. 2n
output values are from 0 through out 2n – 1.
PROCEDURE:-
1. The circuit connections are given as per the

circuit diagram.

PIN CONFIGURATION:-
RESULTS:-
Thus the encoder and decoder using basic

gates is designed and verified the truth table.
4 X 1 MULTIPLEXER:-
BLOCK DIAGRAM:-
D0
INPUT D1 4X1
Y (OUTPUT) Multiplexer
D2
D3
S0 S1 (Selection
Line)
CIRCUIT DIAGRAM:-
TRUTH TABLE:-
INPUT OUTPUT
D0 D1 D2 D3 S0 S1 F
1 0 0 0 0 0 D0
0 1 0 0 0 1 D1
0 0 1 0 1 0 D2
0 0 0 1 1 1 D3

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER
AIM:-
To design and implement of 4x1- multiplexer

and 1x4-demultiplexer using logic gates and to verify
the truth table.

TYPE
3. LED - 1
4. NOT gate (IC 7404) - 1
5. AND gate (IC 7411) - 2
6. OR gate (IC 7432) - 1
7. Bread Board - 1
THEORY:-
MULTIPLEXER:-
A multiplexer is a combinational circuit that
selects binary information from one of many input
lines and directs it to a single output line. The
selection of a particular input line is controlled by a
set of selection lines. Normally, there are 2 n input
lines and n selection lines whose bit combinations
determine which input is selected.
A 4-to-1-line multiplexer is each of the four

inputs “I0” through “I3, is applied to one input of an
AND gate. Selection lines S1 and S0 are decoded to
select a particular AND gate. The outputs of the AND
gates are applied to a single OR gate that provides
the 1-line output. The function table lists the input
that is passed to the output for each combination of
the binary selection values. To demonstrate the
circuit operation, consider the case when S1 S0= 10.
The AND gate associated with input I2 has two of it
inputs equal to 1 and the third input connected to I 2.
The other three AND gates have at least one input

equal to 0, which makes their outputs equal to 0. The
OR gate output is now equal to the value of I 2,
providing a path from the selected input to the
output. A multiplexer is also called a data selector,
since it selects one of many inputs and steers the
binary information to the output line.
1 X 4 DEMULTIPLEXER:-
BLOCK DIAGRAM:-
D0
INPUT E 1X4
D1
OUTPUT Demultiplexer
D2
D3
S0 S1 (Selection
Line)
CIRCUIT DIAGRAM:-

TRUTH TABLE:-
INPUT OUTPUT
E S0 S1 D
1 0 0 D0
1 0 1 D1
1 1 0 D2
1 1 1 D3
DEMULTIPLEXER:-
A decoder with enable input can function as

a demultiplexer. A demultiplexer is a circuit that
receives information from a single line and directs it
to one of 2n possible output lines. The selection of a
specific output is controlled by the bit combination of
n selection lines.
A 1-to-4-line demultiplexer when E is taken

as a data input line and S0 and S1 are taken as the
selection inputs. The single input variables E has a
path to all four outputs, but the input information is
directed to only one of the output lines, as specified
by the binary combination of the two selection lines
S0 and S1. This can be verified from the truth table of
the circuit.
PROCEDURE-

circuit diagram.

PIN CONFIGURATION:-
RESULTS:-
Thus the 4x1- multiplexer and 1x4-

demultiplexer using basic gates is designed and
verified the truth table.

CIRCUIT DIAGRAM:-
S R FLIP FLOP:-
TRUTH TABLE:-
Input Output Comments
R S CLK Q Q’
0 0 Q Q’ No change
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q Q’ Invalid
D – FLIP FLOP:-
TRUTH TABLE:-
D CLK Q Q’
0 Q Q’ Reset
1 1 0 Set
EX.
EX. NO:
NO: -- DATE:-
DATE:-
STUDY
STUDY OF
OF FLIP
FLIP FLOP
FLOP
AIM:-

To study and verify the given flip flop using
logic gates and IC’s.

TYPE
3. LED - 1
4. NOT gate (IC 7404) - 1
5. NAND gate (IC 7410) (3 input) - 1
6. NAND gate (IC 7400) - 1
7. Bread Board - 1
THEORY:-
Flip flops are synchronous bistable devices.

The term synchronous means the output changes
state only when the clock input is triggered. That is,
changes in the output occur in synchronization with
the clock.
Flip flop is a kind of multivibrator. There are
three types of multivibrators: monostable
multivibrator (also called one shot) has only one
stable state. It produces a single pulse in response to
a triggering input.
Bistable multivibrator exhibits two stable states. It is
able to retain the two SET and RESET states
indefinitely. It is commonly used as a basic block for
counters, registers and memories.
Astable multivibrator has no stable state at
all. It is used primarily as an oscillator to generate
periodic pulse waveforms for timing purposes.
The general digital system contains
combinational logic gates and memory elements. The
memory element in digital system contains flip flop.
Flip flop can have one or more input status and two
possible output statuses flip flop is also called latch.
A latch can be limited using two NAND and two
level NOR gates. RS latch has two inputs s and RS are
called set and R is called reset. The S input is used to
produce a 1 in Q i.e. it state binary 1 in flip flop. This
type of flip flop is some time called as coupled RS flip
flop.

JK FLIP FLOP:-
TRUTH TABLE:-
J K CLK Q Q’
0 0 Q Q’ No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q’ Q Complement
T – FLIP FLOP:-
TRUTH TABLE:-
T CLK Q Q’
0 Q Q’ No change
1 1 0 Complement
Since RS flip flop contain an ambiguous state

to estimate the condition. We can ensure that S and R

are never equal. This is done by the D flip flop. D flip
flop is made a delayed flip flop or buffer or gate D
latch. JK flip flop is similar to RS flip flop. Which has
an synchronous control input when J = K = 1. The flip
flop toggles except the feedback connect to the circuit
as that of a RS flip flop. When two inputs of JK flip
flop are shorted T flip flop is formed, When T is zero
the state of the flip flop doesn’t change. When T is
one, the state is complemented.
PROCEDURE:-
1. The circuit is connected as shown in the figure.
2. The output is verified for various combinations

of inputs using truth table by giving connection
of input to corresponding pins.
3. The outputs are verified with the help of truth

table.
RESULT:-
Thus the flip flop using gates & IC is

constructed and the truth table is verified.

4 – BIT SYNCHRONOUS COUNTER:-
CIRCUIT DIAGRAM:-
EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND
AND IMPLEMENTATION
IMPLEMENTATION OF
OF SYNCHRONOUS
SYNCHRONOUS COUNTER
COUNTER

AIM:-
To design and implement 4- bit synchronous

counter using JK flip flops.

TYPE
3. LED - 4
4. AND gate (IC 7408) - 1
5. JK Flip Flop (IC 7476) - 2
6. Function Generator 1 MHz 1
7. Bread Board - 1
THEORY:-
When the counter is clocked such that each

flip flop in the counter is triggered at the same time.
Hence clock signal is connected in parallel to clock
input of both flip flops. But output of the first stage is
used to drive the J and K input of the 2 nd stage. When
the positive edge of 1st clock is applied to the flip flop
with toggle. Because of JA= KA=1, where the flip flop
B output will remain 0. Because JA=JB=0. After 1st
clock pulse A=1 & B=0. At negative going edge of 2 nd
order pulse both flip flop with toggle. Because J A= KA
=0. Because the condition on their J and K inputs.
PROCEDURE:-
1. Connect the IC’s on bread board.

2. Connect the LED’s to the output.
3. Give the serial input to JK flip flop.
4. Verify the truth table for the output.

PINDIAGRAM:-
CLK1 1 16 K1
Pre 2 I 15 Q1
Clr 3 C 14 Q1
J1 4 7 13 Gnd
VCC 5 4 12 K2
CLK2 6 7 11 Q2
Pre 7 6 10 Q2
Clr 8 9 J2
TRUTH TABLE:-
Clock OUTPUT
pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
RESULT:-
Thus the 4-bit synchronous counter using

JK flip flop is designed and output is verified.

4 – BIT ASYNCHRONOUS COUNTER:-
CIRCUIT DIAGRAM:-

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER
AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER
AIM:-
To design and implement 4- bit synchronous

counter using JK flip flop.

TYPE
3. LED - 4
4. JK Flip Flop (IC 7476) - 2
6. Bread Board - 1
THEORY: -
A binary ripple on asynchronous counter

consists of a series connection of complementing flip
flop. With the output of each flip flop connected to
the clock input of the next higher order flip flop. The
flip flop is holding the least significant bit receiver the
incoming clock pulses. A complementing flip flop can
be obtained from a JK flip flop with J and K inputs
tied together. A third alternate is to use a D flip flop
with the complemented output connected to the D
input explains the 4- bit asynchronous counter using
JK flip flops.
Clock signals are connected to the clock input

of only first stage flip flop. The clock input of the 2 nd
stage flip flop is triggered by the Q output of the first
stage can never exactly the same time. Therefore the
flip flops are never simultaneously trigger, which
results in asynchronous counter operation.
PROCEDURE:-
1. Connections are made as per the circuit

diagram.

2. Clock inputs are given to a flip flop from its
previous flip flop.
3. The output is verified with the truth table.
PINDIAGRAM:-
CLK1 1 16 K1
Pre 2 I 15 Q1
Clr 3 C 14 Q1
J1 4 7 13 Gnd
VCC 5 4 12 K2
CLK2 6 7 11 Q2
Pre 7 6 10 Q2
Clr 8 9 J2
TRUTH TABLE:-
Clock OUTPUT
pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1 RESULT:-

Thus the 4-bit Asynchronous counter using
JK flip flop is designed and output is verified.
CIRCUIT DIAGRAM:-
Serial in Serial out:-
PINDIAGRAM:-
TRUTH TABLE:-
R1 1 14 VCC Clock INPUT Q4
pulse
D1 2 I 13 R2 R1 & (Q0)
(CLK)
CLK1 3 C 12 D2 R2 1 1 0
2 1 0
S1 4 7 11 CLK2 3 1 0
4 1 1
Q1 5 4 10 S2
5 0 1
Q1 6 7 9 Q2 6 0 1
7 0 1
GND 7 4 8 Q2
8 0 0
CLEAR (RESET),
CLK1 & CLK2 CLOCK PULSE
D1 & D2 D FLIP FLOP, S1 & S2

PRESET

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN AND
AND IMPLEMENTATION
IMPLEMENTATION OF
OF SHIFT
SHIFT REGISTER
REGISTER
AIM:-
To design and implement of shift register

using flip flops and verify the truth table serial in
serial out, serial in parallel out, parallel in serial out,
parallel in parallel out.

TYPE
3. LED - 4
4. D Flip-Flops (IC 7474) - 2
5. NOT gate (IC 7404) - 1
6. AND gate (IC 7411) - 2
7. OR gate (IC 7432) - 1
9. Bread Board - 1
THEORY:-
A Register is a group of flip-flops, since each

flip-flop is a binary cell capable of storing one bit of
information.
A Register capable of shifting its binary

information either to the right or left is called a Shift
register. The logical configuration of a shift register
consists of a chain of flip-flops connected in cascade,
with the output of one flip-flop connected to the
input of the next flip-flop. All flip-flops receive a
common clock pulse that causes the shift from one
stage to the next.
There are four types of shift registers, they are

1. Serial in serial out
2. Serial in parallel out
3. Parallel in serial out
4. Parallel in parallel out

SERIAL IN PARALLEL OUT:-
CIECUIT DIAGRAM:-
T
RU
TH
TA
BL
E:-
Clock pulse Input Q0 Q1 Q2 Q3
(CLK)
1 1 1 0 0 0
2 1 1 1 0 0
3 1 1 1 1 0
4 1 1 1 1 1
5 0 0 1 1 1
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0
PARALLEL IN SERIAL
OUT:-
CIRCUIT DIAGRAM:-

SERIAL IN SERIAL OUT:-
A basic four-bit shift register can be

constructed using four D flip-flops, as shown
below. The operation of the circuit is as follows.
The register is first cleared, forcing all four
outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop on
the left (FFO). During each clock pulse, one bit is
transmitted from left to right. Assume a data
word to be 100 1. The least significant bit of the
data has to be shifted through the register from
FFO to FF3.
SERIAL IN PARALLEL OUT:-
For this kind of register, data bits are

entered serially in the same manner as discussed
in the last section. The difference is the way in
which the data bits are taken out of the register.
Once the data are stored, each bit appears on its
respective output line, and all bits are available
simultaneously.
PARALLEL IN SERIAL OUT:-
The circuit uses D flip-flops and NAND

gates for entering data (i.e. writing) to the register.
DO, D 1, D2 and D3 are the parallel inputs, where
DO is the most significant bit and D3 is the least
significant bit. To write data in, the mode control

line is taken to LOW and the data is clocked in.
The data can be shifted when the mode control
line is HIGH as SHIFT is active high. The register
performs right shift operation on the application
of a clock pulse.
PARALLEL IN PARALLEL OUT:-
For parallel in - parallel out shift registers,

all data bits appear on the parallel outputs
immediately following the simultaneous entry of the
data bits.
PROCEDURE:-

circuit diagram.
2. Apply the first bit to the input of shift register.
3. Apply the clock pulse from clock generator.
4. Repeat step 2 and step 3 up to entire bit is shift
out from the register.
TRUTH TABLE:-
Clock INPUT OUTPU
pulse T
Q0 Q1 Q2 Q3
(CLK)
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 1
5 0 1 1 1 1
6 0 0 1 1 1
7 0 0 0 1 1
8 0 0 0 0 0
PARALLEL IN PARALLEL OUT:-
CIRCUIT DIAGRAM:-
TRUTH TABLE:-
Clock INPUT OUTPUT

pulse A B C D Q0 Q1 Q2 Q3
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 0 1 0 1 0 1 0 1
6 0 1 1 0 0 1 1 0
7 0 1 1 1 0 1 1 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 1 0 0 1
10 1 0 1 0 1 0 1 0
11 1 0 1 1 1 0 1 1
12
KIT-EEE-III SEMESTER LDIC0LAB
1 1 0 1 1 0 0 Page 67
13 1 1 0 1 1 1 0 1
14 1 1 1 0 1 1 1 0
15 1 1 1 1 1 1 1 1
RESULT:-
Thus a 4 - bit shift register is designed,
implemented and truth table is verified.
MONOSTABLE MULTIVIBRATOR:-
CIRCUIT DIAGRAM:-

+ VCC = 5V
4 8
RA =
10KΩ
3 O U TPU T
7
TO C RO
IC 5 5 5
T R IG G E R
2
IN P U T
6 5
1
C=
0.01µF
C = 0.01µF
GND
PIN DIAGRAM:-
GND 1 8 +VCC
T R IG G E R 2 7 D IS C H A RG E
IC 5 5 5
O U TPU T 3 6 TH E RSH O LD
RESET 4 5 C O NTRO L V O LTA G E
EX.
EX. NO:
NO: -- DATE:-
DATE:-
STUDY
STUDY OF
OF NE
NE 555
555 TIMER
TIMER IN
IN ASTABLE,
ASTABLE, MONOSTABLE
MONOSTABLE OPERATION
OPERATION
AIM:-

To design and testing of a Astable and
Monostable Multivibrators using NE555 timer.
S.No. COMPONENTS RANGE / QUANTITY
TYPE
1. NE555 - 1
2. Resistor 6.8KΩ, 1 1
3.3KΩ, 1
470Ω
3. Capacitors 0.01µF 2
4. Regulated power supply 5V 1
5. CRO 30 MHz 1
6. Function generator 1 MHz 1
7. Bread Board - 1
DESIGN:-
Assume, f = 9 KHz, C = 0.01µF, Time = 1.1RC
Frequency = 1/ (1.1RC)
9 x 103 Hz = 1/ (1.1xRx0.01x10-6)
R = 10 K Ω
ASTABLE MULTIVIBRATOR:-
Assume, f = 10 KHz, RA = 6.8KΩ, C = 0.01µF
Time = 0.693 (R1 + 2R2) C
Frequency = 1.45/ ((RA + 2RB) C)
10x103 Hz = 1.45/ ((6.8 x103 + 2RB) 0.01x10-6)
RB = 3.3 x103Ω
RB = 3.3 KΩ
OUTPUT TON in TOFF in T = TON+TOFF Frequency Amplitude

ms ms in ms in Hz in Volts
Trigger wave input
Square wave output (pin 3)

Capacitor Wave output
(pin 2 & 6)
TABULATION:-
MODEL GRAPH:-
Vin in Trigger wave input

Volts
Time in ms
Capacitor wave output (pin

2 & 6)
Vout in
Volts
Time in ms
Square wave output (pin3)
Vout in
Volts
Time in ms
FORMULA:-
Theoretical:-
TOTAL TIME = 1.1RC

Frequency =1 / (1.1RC)
Practical:-
TOTAL TIME = TON + TOFF
Frequency = 1/T
Theoretical:-
TOTAL TIME = 0.693 (RA + 2RB) C
TON = 0.693(RA + RB) C
TOFF = 0.693 (RB) C
Frequency =1 / (0.693 (RA + 2RB) C)
Duty Cycle Time TD = (RA + RB)/ (RA +2RB) X
100 %
Practical:-
TOTAL TIME = TON + TOFF
Frequency = 1/T
Duty Cycle Time TD = TON/T X 100 %
THEORY:-
Trigger is a negative going pulse (it is a

narrow pulse with a quiescent value +V CC). Initially,
the capacitor is uncharged, when the trigger voltage
falls below Vcc/3, the output comparator 2 is ‘1’ and
the output of comparator 2 is ‘0’. This causes S =0,
R=1, input condition for the flip flop. Its output, Q=0,
Q =0. Now, the transistor is cut-off and hence there is
no path for the capacitor to discharge and supply
voltage (+VCC) now charges capacitor. The negative
trigger pulse now goes ‘high’ and hence output of
comparator 2 is ‘0’. As long as comparator 2 is less
than 2VCC/3, the output of comparator 1 is ‘0’. This
condition (S = 0, R =0) does not change the output.
Hence Q =0, Q =1 and transistor is cut off.

CIRCUIT DIAGRAM:-
+ VCC = 5V
4 8
RA =
6.8 KΩ
3 O U TPU T
7
TO C RO
IC 5 5 5
RB =
3.3 KΩ
6 5
2 1
C= 0.01µF C=
0.01µF
GND
OUTPUT TON in TOFF in T = TON+TOFF Frequency in Amplitude Duty Cycle

ms ms in ms Hz in Volts in percenta
Square wave
output (pin 3)
Capacitor
Wave output
(pin 2 & 6)
TABULATION:-

When the capacitor voltage exceeds 2V CC/3,
then the output of comparator 1 is ‘1’. The output
comparator 2 is anyway ‘0’. And hence S = 1, R =0.
This sets the Q =0 and, Q =0. Now transistor enters
saturation and capacitor starts discharging through
the transistor. Thus capacitor becomes less than
2VCC/3 and ultimately becomes’0’. This result in S =
0, R =0. This maintains Q =1 and, Q =0. When the
trigger goes low, S = 0, R =1, Q =0 and, Q =1, i.e.,
cycle repeats.
The time duration between pulses is known

as the ‘period’, and usually designated with a T. The
pulse is on for TON seconds, then off for T OFF seconds.
The total period is.
TOTAL TIME = 1.1RC
The frequency of operation of the monostable
circuit is dependent upon the values of R and C. The
frequency can be calculated with the formula:
Frequency = 1/T =1/ (1.1RC)
Comparing with monostable operation, the

timing resistor is now split into two sections RA and
RB. pin 7 of discharging transistor Q1 is connected to
the junction RA and RB. When the power supply VCC is
connected, the external timing capacitor C charges
towards VCC with a time constant (R A + RB) C. During
this time, output (pin 3) is high (equals V CC) as reset
R=0 and set S = 1 and this combination makes Q= 0
which has unclamped the timing capacitor C.
When capacitor voltage equals (to be precise
is just greater then), (2/3)VCC the upper comparator
triggers the control flip-flop so that Q= 1. This, in
turn, makes transistor Q1 on and capacitor C starts
discharging towards ground through RB and
transistor Q1 with a time constant R BC. Current also
flows into transistor Q1 through RA. resistors RA and
RB must be large enough to limit this current and
prevent damage to the discharge transistor Q 1. the
minimum value of RA is approximately equal to

VCC/0.2 where 0.2 A is maximum current through the
on transistor Q1.
During the discharge of the timing capacitor
C, as it reaches VCC/3, the lower comparator is
triggered and at this stage, S = 1, R =0, which turns Q
=0. Now Q =0 unclamps the external timing capacitor
C. The capacitor C is thus periodically charged and
discharged between (2/3)VCC and (1/3)VCC
respectively.
The time duration between pulses is known

as the ‘period’, and usually designated with a T. The
pulse is on for TON seconds, then off for T OFF seconds.
The total period is T = TON + TOFF.
TOTAL TIME = TON + TOFF =
0.693 (R1 + 2R2) C
TON = 0.693(R1 + R2) C
TOFF = 0.693 (R2) C
MODEL GRAPH:-
Vout in Square wave output (pin 3)

Volts
Time in ms
Capacitor wave output (pin 2 & 6)
Vout in
Volts
Time in ms

The frequency of operation of the astable
circuit is dependent upon the values of R1, R2, and C.
The frequency can be calculated with the formula:
Frequency = 1/T =1/0.693
(R1 + 2R2) C
The time intervals for the on and off portions
of the output depend upon the values of R 1 and R2.
The ratio of the time duration when the output pulse
is high to the total period is known as the duty-cycle.
The duty – cycle can be calculated with the formula:
Duty Cycle Time TD
= TON/T X 100 %
TD = (R1 + R2)/ (R1
+2R2) X 100 %
The 555 can produce duty-cycles in the range
of approximately 55 to 95%. A duty-cycle of 80%
means that the output pulse is on or high for 80% of
the total period. The duty-cycle can be adjusted by
varying the values of R1 and R2.
PROCEDURE:-
1. Circuit connections as per the circuit
diagram.

2. Power supply is given to the pin no:4 & 8
3. Take the output pin no: 3 and measure the
amplitude and time period.
4. Also, measure the charging and discharging
of the capacitor across pin no: 2 & 6 using
CRO.
RESULT:-
Thus the Astable and Monostable
Multivibrators using NE555 and wave forms were
obtained.
INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-

Rf = 100KΩ
Vcc =
7
R1 =10KΩ
+12V
2
-
To CRO
6
3 IC741
+
V 0 = -(R f/ R 1 )V i
Vcc =
4
- 12V
R=
A u d io O s c il la t o r V in = 1 V 10KΩ
RL =
100KΩ
GND
GND
GND
NON - INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf = 100KΩ
Vcc =
7
R1 =10KΩ
+12V
2
-
To CRO
6
3 IC741
+
V 0 = ( 1 + ( R f / R 1 ) ) V in
Vcc =
4
- 12V
R=
RL =
10KΩ
GND 100KΩ
A u d io O s c il la t o r V in = 1 V
GND
GND
EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN OF
OF INVERTING
INVERTING AND
AND NON-INVERTING
NON-INVERTING AMPLIFIER
AMPLIFIER

AIM:-
To construct and test an inverting, non -
inverting and slew rate using operational amplifier
IC741.
S.No. COMPONENTS RANGE / QUANTITY
TYPE
1. Dual Regulated Power Supply ( 0 – 30) V 1
2. OP AMP( IC741) - 1
3. Resistor 10 kΩ, 100KΩ 2 2
5. CRO 30 MHz 1
6. Bread Board - 1
FORMULA:-
Closed loop gain ACL = - (Rf / R1)
(Theoretical)
Closed loop gain ACL = (V0/Vi) (Practical)
NON-INVERTING AMPLIFIER:-
Closed loop gain ACL = 1 + (Rf / R1)
(Theoretical)
Closed loop gain ACL = (V0/Vi) (Practical)
PINDIAGRAM:-

O FFSET NULL 1 8 N O C O N N E C T IO N
IN V E R T IN G P O S IT I V E
2 7
IN P U T IC 7 4 1 SUPPLY
NO NINV E RTING
3 6 O U TPU T
IN P U T
N E G A T IV E
4 5 O FFSET NULL
SUPPLY
THEORY:-
The circuit is shown in fig, the output voltage

V0 is fed back to the inverting input terminal through
the Rf – R1 network where Rf is the feedback resistor.
Input signal Vi (ac or dc) is applied to the inverting
input terminal through R1 and non – inverting
terminal of op-amp is grounded.
The output voltage V0 = - Vi (Rf / R1)
The closed loop gain ACL = (V0/Vi) = - (Rf /

R1)
◦
The negative sign indicates a phase shift of 180
between Vi and V0. Also since inverting input
terminal is at virtual ground, the effective input
impedance is R1. The value of R1 should be kept fairly
large to avoid loading affect. This however, limits the
gain that can be obtained from this circuit.
NON - INVERTING AMPLIFIER:-
If the signal is applied to the non inverting

input terminal and feedback is given as shown in fig,
the circuit amplifies without inverting the input
signal. Such a circuit called non – inverting amplifier.
It may be noted that it is also negative feed-back
system as output is being fed back to inverting input
terminal.
As the differential voltage Vd at the input

terminal of op-amp is zero, the voltage at node ‘a’ in
fig is Vi, same as the input voltage applied to non –
inverting input terminal. Now Rf and R1 forms a
potential divider. Hence

Vi = (V0 / (Rf + R1)) x Ri
As no current flows into the op-amp, thus for non –

inverting amplifier the voltage gain,
ACL = (V0/Vi) = 1 + (Rf / R1)
TABULATION:-
S.NO Input signal Output signal
Vin (Volts) Time in ms Vo (Volts) Time in ms Gain (Acl)
= (Vo/Vin)
NON – INVERTING AMPLIFIER:-

Vin (Volts) Time in ms Vo (Volts) Time in ms Gain (Acl)
= (Vo/Vin)
PROCEDURE:-

circuit diagram.
2. Check the polarity of the supply voltage.
3. Switch on the power supply to the circuit.
4. Set the input using signal generator and
measure the output voltage using CRO.

MODEL GRAPH:-
INVERTING AMPLIFIER: -
NON -INVERTING AMPLIFIER:-
Vin in Input Signal Vin in

Input Signal
Volts
Volts
Time in ms
Time in ms
Output Signal
Output Signal
Vout in
Vout in
Volts
Volts
Time in ms
Time in ms

RESULT:-
Thus the inverting, non-inverting and slew

rate curves are constructed and tested using IC741
op-amp.
ADDER:
CIRCUIT DIAGRAM:-
Rf = 10 KΩ
Vcc =
7
+12V
2
Va -
6 To CRO
R = 10 KΩ IC741
3 V 0 = - (V a + V b + V c )
+
Vb
Vcc =
Rb =10 KΩ
- 12V
4
Vc
Rc =10 KΩ R=
2.5 KΩ
GND
TABULATION:-
S.NO Input Voltage in Volts Output voltage in volts (V0)
Va in Volts Vb in Volts Vc in Volts Practical Theoretical

EX.
EX. NO:
NO: -- DATE:-
DATE:-
DESIGN
DESIGN OF
OF ADDER,
ADDER, INTEGRATOR
INTEGRATOR AND
AND DIFFERENTIATOR
DIFFERENTIATOR USING
USING OPERATIONAL
OPERATIONAL
AMPLIFIER
AMPLIFIER
AIM:-
To design and test an adder, differentiator
and Integrator using operational amplifier IC741.
S.No. EQUIPMENT RANGE / TYPE QUANTITY
1. Regulated Power Supply (Dual) ( 0 – 30) V (0 2 1
-5)V
2. IC741 (OP AMP) - 1
3. Resistor 1kΩ, 33kΩ, 3kΩ, 1, 1, 1, 2, 2, 4, 1

100Ω, 3.3kΩ,
10KΩ, 2.5KΩ
4. Capacitor 0.1 µF, 1 µF 1, 1
6. CRO 30 MHz 1
7. Bread Board - 1
8. Mulitimeter 1
DESIGN:-
SUMMER:-
Output voltage,
Volts
Let Ra = Rb = Rc = 10kΩ = R
V0 = - (Rf/R) (Va + Vb +Vc) [Gain, A = (Rf/R)]

V0 = - Gain (Va + Vb +Vc)
Gain = (Rf/R) = (10KΩ/10KΩ) = 1 (unity)

So, V0 = - (Va + Vb +Vc)
Rcomp = R1//R2//R3//Rf =3.3 KΩ//10 KΩ = 2.5 KΩ
DIFFERENTIATOR:-
CIRCUIT DIAGRAM:-
Cf = 0.1 µF
Rf = 1 KΩ
C1 = 1 µF Vcc =
7
R1 = 100 Ω
+12V
2
-
To CRO
6
3 IC741
+
V o u t = - R f C 1 ( d V i/ d t )
Vcc =
F u n ctio n
V in
4
- 12V
G e n e ra to r R=
100 Ω
GND
GND
INTEGRATOR:-
CIRCUIT DIAGRAM:-

Cf = 0.1µF
Rf = 33 KΩ
Vcc =
7
R1 = 3.3 KΩ
+12V
2
-
To CRO
6
3 IC741
+
V o u t = - ( 1 / R f C F ) ∫ V i( t ) d
Vcc =
4
- 12V
F u n c tio n R=
V in 3.3 KΩ
RL =
G e n e ra to r 3 KΩ
GND
GND
GND
DESIGN:-
DIFFERENTIATOR:-
(i) let fa = 150 Hz
Assuming C1 = 1 µF,
Rf = 1/(2πfaC1) = 1.06 KΩ
(ii) let fb = 10 Hz and fa = 1.5 KHz
C1 = 0.1 µF
R1 = 1/(2πfaC1) = 106.1 Ω
(iii) For a Differentiator,
R 1 C1 = R f Cf
Therefore Cf = (R1 C1/ Rf) = 0.1 µF
(iv) Rcomp = R1 || Rf = R1 Rf /R1 +Rf = 96.44 Ω
Rcomp =100 Ω
INTEGRATOR:-
Design an integrator circuit operating at the

frequency of 3 kHz
The period of the input signal = 1 / 3 kHz =
0.33 x 10-3 s
(i) Choose R1Cf =0.33 x 10-3, Cf = 0.01 μF => R1 =
0.33 x 10-3 / 0.01 x 10-6 =3.3 kΩ

R1~ = 3.3kΩ
(ii) For integrator Rf = 10 R1=10 x 3.3 kΩ =33 kΩ
(iii) Rcomp = R1 || Rf = R1 Rf /R1 +Rf =(3.3 x 103 x
33 x 103) / (3.3 x 103 + 33 x 103)
= 3 kΩ
THEORY:-
ADDER:
Adder a adder circuit. Here, the output is a
linear summation of a number of input signals. For
simple analysis, we assume ideal op.amp. Thus, a
virtual ground exits at the inverting input.
Furthermore the input current to the ideal amplifier
is zero. Hence the current i is given as
and V0 = -Rf i, Then
For non ideal Op-amp, a resistor is connected to

the non inverting input to minimize the effect of
input bias current.
DIFFERENTIATOR:-
TABULATION:-
Signal Vin (Volts) Time in ms Signal Vo (Volts) Time in ms
1. Sinusoidal Output
wave form wave form
2. Square wave Spike wave
form form
MODEL GRAPH:-
Vin in Input form Vin in
Square wave form

Volts
Volts
Time in ms
Time in ms
Output form
Spike wave form
Vout in
Vout in
Volts
Volts
Time in
ms Time in ms
DIFFERENTIATOR:-
One of the simplest of the op-amp circuits
that contain capacitor is the differentiating amplifier, t
or differentiator. The differentiator circuit performs
the mathematical operation of differentiation, i.e., the
output waveform is the derivative of input
waveform. A differentiator circuit is shown in fig.
The output voltage V0 = -RfC1

(dVi/dt)
A good differentiator may be designed as per the

following steps:

1. Choose fa equal to the highest frequency of
the input signal. Assume a practical value of
C1 (< 1 µF) and then calculate Rf.
2. Choose fb = 10 fa. Now calculate the values of

R1 and Cf, so that R1 C1 = Rf Cf.
INTEGRATOR:-
If we interchange the resistor and capacitor

of the differentiator, the circuit becomes integrator.
The circuit thus provides an output voltage which is
proportional to the time integral of the input and R f Cf
is the time constant of the integrator. It may be noted
that there is a negative sign in the output voltage, and
therefore this integrator is also known as an inverting
integrator. A resistance Rcomp = R1 is usually
connected to the non-inverting input terminal to
minimize the effect of bias current.
A simple low pass RC circuit can also work

as an integrator when time constant is very large.
This requires very large values of R and C. The
components R and c cannot be made infinitely large
because of practical limitations. The gain of integrator
decreases with increasing frequency. Thus integrator
circuit does not have any high frequency problem
unlike a differentiator circuit.
The output voltage V0 = -
(1/R1 CF) ∫ Vi (t) dt + V0 (0)

0
Where V0(0) = is the initial

output voltage
PROCEDURE:-
1. Connections are given as per the circuit

diagram.
2. + Vcc and - Vcc supply is given to the power
supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency
knobs of the function generator, appropriate
input voltage is applied to the input terminal
of the Op-Amp.
4. The output voltage is obtained in the CRO
and the input and output voltage waveforms
are plotted in a graph sheet.

INTEGRATOR:-
TABULATION:-
Signal Vin (Volts) Time in ms Signal Vo (Volts) Time in ms
1. Sinusoidal Output
wave form wave form
2. Square wave Triangular
form wave form
MODEL GRAPH:-
Vin in Input form

Vin in Square wave form
Volts
Volts
Time in ms
Time in ms
Output form
Triangular wave form Vout in
Vout in
Volts
Volts
Time in
ms Time in ms

RESULT:-
Thus the adder, differentiator, integrator

using operational amplifier IC741 was designed
and tested.
CIRCUIT DIAGRAM:
+15V
10 KΏ
8 6
2KΏ
4
3
20 KΏ
NE566
PIN
DIAGRAM:
7 1
0.01µF
The frequency of the output waveforms is

approximated by Fo=2(VCC-VC )/ CT RT VCC
INTERNAL DIAGRAM:

EX.
EX. NO:
NO: -- DATE:-
DATE:-
STUDY
STUDY OF
OF VCO
VCO
AIM:
To obtain square wave and triangular wave using voltage controlled oscillator
APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY

1. Digital IC trainer 1
2. VCO NE566 1
4. Resistor 2K, 10K 2
5. Capacitor 0.01µF 1
7. POT 20K 1
9. Connecting wires and probes As required
THEORY:
In most cases, the frequency of an oscillator is determined by the time constant RC. However, in
cases or applications such as FM, tone generators, and frequency-shift keying (FSK), the frequency is to
be controlled by means of an input voltage, called the control voltage. This can be achieved in a voltage-
controlled oscillator (VCO). A VCO is a circuit that provides an oscillating output signal (typically of
square-wave or triangular waveform) whose frequency can be adjusted over a range by a dc voltage. An
example of a VCO is the 566 IC unit, that provides simultaneously the square-wave and triangular-wave
outputs as a function of input voltage. The frequency of oscillation is set by an external resistor R 1 and a
capacitor C1 and the voltage Vc applied to the control terminals. Figure shows that the 566 IC unit
contains current sources to charge and discharge an external capacitor C v at a rate set by an external
resistor R1 and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch the
current sources between charging and discharging the capacitor, and the triangular voltage produced
across the capacitor and square-wave from the Schmitt trigger are provided as outputs through buffer
amplifiers. Both the output waveforms are buffered so that the output impedance of each is 50 f2. The
typical magnitude of the triangular wave and the square wave are 2.4 Vpeak.to-peak and 5.4Vpeak.to.peak.
PROCEDURE:
1. Connections are made as shown in diagram.

2. The square and triangular wave is obtained in terminal 3&4 respectively.
3. The Modulating Input at Pin 5 Is Changed by varying rheostat the voltage at pin 5 and
corresponding frequency at output are noted and characteristics were drawn
RESULT:
Thus the voltage controlled oscillator using NE566 was done and the output was verified
CIRCUIT DIAGRAM:-
FREQUENCY MULTIPLIER:-
+ 6V
R=
20 KΩ
C = 10 µF
R=
2 KΩ
10 8
C1 = 0.001 µF
7
2
V C O O u tp u t
IC 5 6 5
4
+ 6V
V in
5 fin
3
5
1 9
IC 7 4 9 0 RC =
11
4.7 KΩ
2 3 6 7 10 1
GND CT =
0.01 µF
GND 2N22222
RB = 10 KΩ
GND
- 6V
GND
PIN DIAGRAM:-
-V c c 1 14 NC
In p u t 1 14 In p u t 2
In p u t 2 13 NC
R1 2 13 NC
In p u t 3 12 NC
R2 3 12 Qa
IC 5 6 5
V C O o u tp u t 4 11 NC
IC 7 4 9 0
NC 4 11 Qd
V C O in p u t 5 10 +Vcc
Vcc 5 10 GN D
R e fe re n c e o u tp u t 6 9 E x te rn a l c o m p o n e n t
fo r V C O S1 6 9 Qb
D e m o d u la te d o u t p u t 7 8 E x t e rn a l r e s is t o r
fo r V C O S2 7 8 Qc
EX.
EX. NO:
NO: -- DATE:
DATE: --
STUDY
STUDY OF
OF PLL
PLL
AIM:-
To construct and test the frequency multiplier using PLL 565.
S.No. COMPONENTS RANGE / TYPE QUANTITY

1. RPS (0-30) Volts 2
2. Signal generator 1MHz 1
3. CRO 20MHz 1
4. Resistors 20KW,2KW,4.7KW,10KW 1
5. PLL Counter IC565,IC7490 1
6. Capacitors 0.01µF, 0.001µF, 10µF 1
7. Transistor 2N2222 1
THEORY:-
In the frequency multiplier using PLL565, a divided by N network is inserted
between the VCO output and the phase comparator input. Since the output of the
comparator is locked to the input frequency fin, the VCO is running at a multiple of the
input frequency. Therefore in the locked state the VCO output frequency fo is given by,
fo= Nfin
TABULATION:-
INPUT WAVEFORM OUTPUT WAVEFORM
Square wave Signal Square wave Signal
Amplitude in volts
Time Period in ms
MODEL GRAPH:-
Vin in Square wave input

Volts
Time in ms
Vin in
Square wave output
Volts
Time in ms
PROCEDURE:-
1. Rig up the circuit of frequency multiplier

2. Connect the signal generator output to the input terminal of PLL
3. Connect the CRO probes to display the input and output signals
4. Set the input signal at 1Vpp square wave at 1khz
5. Vary the VCO frequency by adjusting the 20KW potentiometer till the PLL is locked
6. Measure the output frequency, it should be 5 times that of the input frequency
7. Repeat the steps for different range of frequencies
RESULT:-
Thus the frequency multiplier using PLL were designed and waveform were plotted.
EE6311 – LDIC LAB 98
K.I.T.

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KIT-EEE-III SEMESTER LDIC LAB Page 1

3. OR gate (IC 7432) - 1

4. AND gate (IC 7408) - 1

5. NOT gate (IC 7404) - 1

6. NAND gate (IC 7400) - 1

7. NOR gate (IC 7402) - 1

8. EX-OR gate (IC 7486) - 1

10. Bread Board - 1

KIT-EEE-III SEMESTER LDIC LAB Page 2

NOT GATE(IC 7404):-

NAND GATE(IC 7400):-

NOR GATE(IC 7402):-

EX-OR GATE(IC 7486):-

KIT-EEE-III SEMESTER LDIC LAB Page 4

1. The connections are given as per the circuit diagram.

KIT-EEE-III SEMESTER LDIC LAB Page 6

TRUTH TABLE: - K MAP:-

KIT-EEE-III SEMESTER LDIC LAB Page 8

KIT-EEE-III SEMESTER LDIC LAB Page 9

KIT-EEE-III SEMESTER LDIC LAB Page 10

S.No. COMPONENT SPECIFICATION QTY

1. Connections are given as per the circuit diagram

KIT-EEE-III SEMESTER LDIC LAB Page 11

From the K-Map,

KIT-EEE-III SEMESTER LDIC LAB

The truth table of the given Boolean expression was verified.

KIT-EEE-III SEMESTER LDIC LAB

SL.No. EQUIPMENT RANGE / TYPE QUANTITY

4. OR gate (IC 7432) - 1

5. AND gate (IC 7408) - 1

6. NOT gate (IC 7404) - 1

8. Connecting wires - As required

Sum = A’B + B’A = A  B

KIT-EEE-III SEMESTER LDIC LAB Page 14

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

KIT-EEE-III SEMESTER LDIC LAB Page 15

K-Map for SUM:

KIT-EEE-III SEMESTER LDIC LAB Page 16

K-Map for CARRY:

KIT-EEE-III SEMESTER LDIC LAB Page 17

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

K-Map for Difference:

KIT-EEE-III SEMESTER LDIC LAB Page 19

K-Map for Borrow:

Borrow = A’B + BC + A’C

1. The connections are given as per the circuit diagram.

KIT-EEE-III SEMESTER LDIC LAB Page 20

To design and implement 4-bit

1. Binary to gray code converter

2. Gray to binary code converter

3. BCD to excess-3 code converter

4. Excess-3 to BCD code converter

2. AND GATE IC 7408 1

4. NOT GATE IC 7404 1

6. Connecting wires - As required

KIT-EEE-III SEMESTER LDIC LAB Page 22

K-Map for G3:

K-Map for G2:

KIT-EEE-III SEMESTER LDIC LAB Page 24