Chapter 2: Programmable Logic Devices

Outline
• Digital Systems Implementation Platforms
• Logic circuit design review
• Programmable Logic Devices
• SPLD
• CPLD
• FPGA
• ASICs
Digital Systems Implementation Platforms

Digital IC

PLDs ASIC

SPLD CPLD FPGA Semi-Custom Full-Custom

PLA PAL Standard cell Gate Array

This course
Outline
• Digital Systems Implementation Platforms
• Logic circuit design review
• Programmable Logic Devices
• SPLD
• CPLD
• FPGA
• ASICs
Logic circuit design review
• Sum of Product
• To get the desired canonical SOP expression we will add the min-terms
(product terms) for which the output is 1 (F=1).

• F = A’B + AB’ + AB
• Product of Sums (POS)
• To get the desired canonical POS expression we will multiply the max-
terms (sum terms) for which the output is 0 (F=0).

• F = (A+B) . (A’+B’)
Outline
• Digital Systems Implementation Platforms
• Logic circuit design review
• Programmable Logic Devices
• SPLD
• CPLD
• FPGA
• ASICs
 Simple Programmable Logic Device (SPLD)
• Programmable Array Logic (PAL)
• Generic Array Logic (GAL)
• The structure of PAL and GAL is composed of the programmable AND
followed by the programmable OR gate.
• PAL, GAL can be used to configure the Sum of Product logic circuit.

Input lines
Input buffer
A B A B A A B B
A B A B A
Fix connection
B
Product
2
X X=AB+AB+AB
term
2
X=AB+AB+AB 2
lines

Fuse blown Fuse intact

(noconnection) (connection)
Example of PAL configuration
PAL /GAL
Macrocell
Or array
I1
OR Output
I2 Programmable logic O1
GATE
I3 logic array

PAL: one time OR Output

programmable GATE logic O2

GAL:
reprogrammable
OR Output
logic O3
GATE

In-1 OR Output
In logic Om
GATE
Macrocell

Tristate control Tristate control

From Output/input
From output and gate
and gate array
array

Tristate control
From Output/input
and gate
array
Programmable fuse
Complex Programmable Logic Device (CPLD)
• CPLD is consist of SPLDs

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
PIA
SPLD SPLD
Programmable
Interconnect
Logic Array array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

Logic Array Logic Array

I/O block (LAB) block (LAB) I/O
SPLD SPLD
Field Programmable Gate Array)

Programmable
Configurable Logic Block (CLB)
interconnections
IO IO IO IO
block block block block
IO IO
block block

CLB CLB CLB CLB

IO IO
block block

CLB CLB CLB CLB

IO IO
block block

CLB CLB CLB CLB

IO IO
block block

IO IO IO IO
block block block block
FPGA
CLB

CLB CLB
Logic module Logic module

Logic module Logic module

Logic module Logic module

Local Local
interconnect interconnect

Logic module Logic module

Global column
Global row
interconnect
interconnect
Logic Module – Lookup table (LUT)

Logic section LUT

Memory cells
A 2A 1A 0 1
A0 SOP
A 2A 1A 0 0
A1 output
I/O A 2A 1A 0 0
A2 LUT Associated A0 A 2A 1A 0 1 SOP
logic A1
A2 A 2A 1A 0 0 output
An-1
Logic module A 2A 1A 0 1
A 2A 1A 0 0
A 2A 1A 0 1 A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0

LUT
LUT

A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0

Logic section LUT

Memory cells
A2A1A0 0
A2A1A0 1
A2A1A0 0
A0 A2A1A0
A1 1 SOP
A2 A2A1A0 1 output
A2A1A0 1
A2A1A0 1
A2A1A0 0
Outline
• Digital Systems Implementation Platforms
• Logic circuit design review
• Programmable Logic Devices
• SPLD
• CPLD
• FPGA
• ASICs
ASICs
• Full-Custom ASICs: custom chip
• Some (possible all) logic cells are customized and all mask layers are
customized
• Complete flexibility to decide the size of the chip, the number of transistors
the chip contains, the placement of each transistor on the chip, and the way
the transistors are connected together chip layout process
• Ex: Microprocessors and memory chips
• Semi-custom ASICs: Standard-cell based and Gate-array-based ASICs
• Does not need complete flexibility for the layout of each individual transistor
in a custom chip
• All logic cells are predesigned (defined in cell library) and some (possibly all)
of the mask layers are customized
https://www.xilinx.com/video/hardware/what-is-the-difference-between-an-fpga-and-an-asic.html
No. FPGA ASIC
1 Reconfigurable circuit. FPGAs can be reconfigured with a different design. Permanent circuitry. Once the
They even have capability to reconfigure a part of chip while remaining application specific circuit is taped-out
areas of chip are still working! This feature is widely used in accelerated into silicon, it cannot be changed. The
computing in data centres. circuit will work same for its complete
operating life.
2 Design is specified generally using hardware description languages (HDL) Same as for FPGA. Design is specified
such as VHDL or Verilog. using HDL such as Verilog, VHDL etc.
3 Easier entry-barrier. One can get started with FPGA development for as Very high entry-barrier in terms of cost,
low as USD $30. learning curve, liaising with
semiconductor foundry etc. Starting
ASIC development from scratch can cost
well into millions of dollars.
4 Not suited for very high-volume mass production. Suited for very high-volume mass
production.
5 Less energy efficient, requires more power for same function which ASIC Much more power efficient than FPGAs.
can achieve at lower power. Power consumption of ASICs can be
very minutely controlled and optimized.
6 Limited in operating frequency compared to ASIC of similar process node. ASIC fabricated using the same process
The routing and configurable logic eat up timing margin in FPGAs. node can run at much higher frequency
than FPGAs since its circuit is optimized
for its specific function.
No. FPGA ASIC
7 Analog designs are not possible with FPGAs. Although FPGAs may contain specific ASICs can have complete analog circuitry, for
analog hardware such as PLLs, ADC etc, they are not much flexible to create for example WiFi transceiver, on the same die
example RF transceivers. along with microprocessor cores. This is the
advantage which FPGAs lack.
8 FPGAs are highly suited for applications such as Radars, Cell Phone Base Stations etc ASICs are definitely not suited for application
where the current design might need to be upgraded to use better algorithm or to a areas where the design might need to be
better design. In these applications, the high-cost of FPGAs is not the deciding factor. upgraded frequently or once-in-a-while.
Instead, programmability is the deciding factor.

9 Preferred for prototyping and validating a design or concept. Many ASICs are It is not recommended to prototype a design
prototyped using FPGAs themselves! Major processor manufacturers themselves use using ASICs unless it has been absolutely
FPGAs to validate their System-on-Chips (SoCs). It is easier to make sure design is validated. Once the silicon has been taped
working correctly as intended using FPGA prototyping. out, almost nothing can be done to fix a
design bug (exceptions apply).

10 FPGA designers generally do not need to care for back-end design. Everything is ASIC designers need to care for everything
handled by synthesis and routing tools which make sure the design works as from RTL down to reset tree, clock tree,
described in the RTL code and meets timing. So, designers can focus into getting the physical layout and routing, process node,
RTL design done. manufacturing constraints (DFM), testing
constraints (DFT) etc. Generally, each of the
mentioned area is handled by different
specialist person.
https://numato.com/blog/differences-between-fpga-and-asics/