This document contains a 25 question exam on Digital Electronics for a II/III year Biomedical Engineering course. The exam covers topics such as logic families, universal gates, hazards, ROM, Karnaugh maps, shift registers, flip-flops, sequential circuits, and programmable logic devices. Students are instructed to answer all 25 multiple choice questions, each worth 2 marks, for a total of 50 marks.
This document contains a 25 question exam on Digital Electronics for a II/III year Biomedical Engineering course. The exam covers topics such as logic families, universal gates, hazards, ROM, Karnaugh maps, shift registers, flip-flops, sequential circuits, and programmable logic devices. Students are instructed to answer all 25 multiple choice questions, each worth 2 marks, for a total of 50 marks.
This document contains a 25 question exam on Digital Electronics for a II/III year Biomedical Engineering course. The exam covers topics such as logic families, universal gates, hazards, ROM, Karnaugh maps, shift registers, flip-flops, sequential circuits, and programmable logic devices. Students are instructed to answer all 25 multiple choice questions, each worth 2 marks, for a total of 50 marks.
This document contains a 25 question exam on Digital Electronics for a II/III year Biomedical Engineering course. The exam covers topics such as logic families, universal gates, hazards, ROM, Karnaugh maps, shift registers, flip-flops, sequential circuits, and programmable logic devices. Students are instructed to answer all 25 multiple choice questions, each worth 2 marks, for a total of 50 marks.
SREE SASTHA INSTITUTE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF BIOMEDICAL ENGINEERING
CYCLE TEST - II
SUB. NAME : Digital Electronics SUB. CODE : EC8392
YEAR / SEM : II/III DURATION : 1.30 Hrs MAX.MARKS : 50 DATE : Part - A (25x2= 50 marks)
Answer ALL Questions
1. What is a prime implicant? [CO-3]
2. Give the classification of logic families. [CO-3] 3. Which gates are called as the universal gates? [CO-3] 4. Why totem pole outputs cannot be connected together. [CO-3] 5. Simplify the following expression Y = (A + B) (A + C’) (B' + C’) [CO-3] 6. What is hazard? Classify it. [CO-3] 7. Define Dynamic Hazard and Primitive Flow chart. [CO-3] 8. Explain ROM and classify its types. [CO-3] 9. Define races and cycles. [CO-3] 10. What is a karnaugh map & State the limitations of karnaugh map. [CO-3] 11. What are the different types of shift registers? [CO-3] 12. Explain the flip-flop excitation tables for RS FF [CO-3] 13. Explain the flip-flop excitation tables for D flip-flop [CO-2] 14. Define sequential circuit. [CO-2] 15. Give the comparison between combinational circuits and sequential circuits. [CO-2] 16. What is pulse mode asynchronous machine? [CO-2] 17. What is fundamental mode? [CO-2] 18. What do you mean by present state? [CO-2] 19. What do you mean by next state? [CO-2] 20. State the types of sequential circuits and define it? [CO-2] 21. What is field programmable logic array? [CO-2] 22. List the major differences between PLA and PAL [CO-2] 23. Define PLD. [CO-2] 24. Give the classification of PLDs. [CO-2] 25. Define PROM,PLA,PAL. [CO-2]
Question Paper Prepared By Dept.Exam Cell Coordinator HOD
REG. NO:
SREE SASTHA INSTITUTE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF BIOMEDICAL ENGINEERING
CYCLE TEST - II
SUB. NAME : Digital Electronics SUB. CODE : EC8392
YEAR / SEM : II/III DURATION : 1.30 Hrs MAX.MARKS : 50 DATE : Part - A (25x2= 50 marks)
Answer ALL Questions
1. What is a prime implicant? [CO-3]
2. Give the classification of logic families. [CO-3] 3. Which gates are called as the universal gates? [CO-3] 4. Why totem pole outputs cannot be connected together. [CO-3] 5. Simplify the following expression Y = (A + B) (A + C’) (B' + C’) [CO-3] 6. What is hazard? Classify it. [CO-3] 7. Define Dynamic Hazard and Primitive Flow chart. [CO-3] 8. Explain ROM and classify its types. [CO-3] 9. Define races and cycles. [CO-3] 10. What is a karnaugh map & State the limitations of karnaugh map. [CO-3] 11. What are the different types of shift registers? [CO-3] 12. Explain the flip-flop excitation tables for RS FF [CO-3] 13. Explain the flip-flop excitation tables for D flip-flop [CO-2] 14. Define sequential circuit. [CO-2] 15. Give the comparison between combinational circuits and sequential circuits. [CO-2] 16. What is pulse mode asynchronous machine? [CO-2] 17. What is fundamental mode? [CO-2] 18. What do you mean by present state? [CO-2] 19. What do you mean by next state? [CO-2] 20. State the types of sequential circuits and define it? [CO-2] 21. What is field programmable logic array? [CO-2] 22. List the major differences between PLA and PAL [CO-2] 23. Define PLD. [CO-2] 24. Give the classification of PLDs. [CO-2] 25. Define PROM,PLA,PAL. [CO-2]
Question Paper Prepared By Dept.Exam Cell Coordinator HOD