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T104XRDB

Page Description Version Control


1 SCHEMATIC PAGE LISTING
A Version Date Modifications A
2 SYSTEM BLOCK DIAGRAM
3 T104X DDR4 MEMORY INTERFACE V0.1 2014/10 First release of Schematics
4 T104X IFC INTERFACE
5 T104X NOR and NAND FLASH INTERFACE V1.0 2014/12 Released to Manufacturing
6 T104X SPI FLASH and SDHC INTERFACE
7 T104X SYSTEM LOGIC INTERFACE
8 T104X ETHERNET and SERDES INTERFACE
9 SERDES and MDIO MUX/DEMUX SWITCHs
10 T104X USB INTERFACE
11 T104X QE-TDM/DIU MUX/DEMUX
12 T104X POWER SUPPLY
13 T104X PLL FILTERs and GROUND
B B
14 T104X DUART and I2C DEVICE INTERFACE
15 TDM RISER INTERFACE
16 HDMI DISPLAY INTERFACE
17 LVDS PANEL INTERFACE
18 PROFIBUS INTERFACE
19 RGMII ETHERNET PORT 1
20 RGMII ETHERNET PORT 2
21 SGMII ETHERNET PORT
22 SGMII ETHERNET PORT 1
23 SGMII ETHERNET PORT 2
24 QSGMII PHY 1
C
25 QSGMII PHY 2 C
26 QSGMII ETHERNET PORTs
27 PCIe X1 SLOT, MINI PCIe and SATA CONNECTORs
28 AURORA PORT
29 CPLD
30 SYSTEM CLOCK GENERATORs
31 SYSTEM CLOCK GENERATORs (cont.)
32 T104X CORE POWER CONVERTOR
All information is subject to change without notice.
33 SYSTEM POWER CONVERTORs No warranty, expressed or applied, is made as to the
34 SYSTEM POWER CONVERTORs (cont.) accuracy of the information contained herein. This
schematic is provided for reference purposes only.
35 SYSTEM POWER SWITCHs Contact your Freescale representative to obtain the
36 SYSTEM POWER INPUT latest information on this product.

D
37 MECHANICALs D

38 CHANGE LIST

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 1 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM BLOCK DIAGRAM

A A

RS232 UART1 DDR4


RS232 XCVR DDR4 UDIMM ATX Power
I2C1
DB9 72bit, 2/4GB
12V
2x1 5V
RS232 UART2
RS232 XCVR IFC NOR FLASH
16bit, 128MB VCORE
1.0V
USB1 I2C EEPROM 1.0V_SVDD
USB1
USB Conn. USB Protect & USB2 AT24C256 1.2V Power
USB2 Power Switch
TypeA x2 USB CTL NAND FLASH 1.35V_XVDD Regulators
8bit, 1GB 1.5V
Thermal Monitor 1.8V
SGMII ADT7461 2.5V
MDI MDI SGMII PHY 2.5V_VPP
RJ45 Magnetics
RTL8211DN EMI1 ALTERA CPLD 3.3V
EPM570G
SPI SPI FLASH 5V
RGMII 64MB 12V
MDI MDI RGMII PHY
Magnetics
RTL8211E-VL
RJ45
B B
SDHC SDHC SD Card
Protect
2x1 RGMII SDHC/SDXC
MDI MDI RGMII PHY
Magnetics
RTL8211E-VL
JTAG JTAG
1.8V<->3.3V COP Conn.

MDI MDI T1040


MDI MDI QSGMII JTAG JTAG
QSGMII 1.8V<->3.3V
MDI MDI PHY
/T1042 Aurora Conn.
MAGNETICS

MDI MDI F104S8A EMI1


AURORA
RJ45 x8

T1040
MDI MDI
PCIe
MDI MDI QSGMII
QSGMII I2C2CH4 PEX x1 SLOT
MDI MDI PHY
MDI MDI F104S8A
PCIe
I2C2CH1 Mini PCIe Conn.

SGMII
MDI MDI SGMII PHY PCIe
RJ45 Magnetics EMI1
RTL8211DN I2C2CH2 Mini PCIe Conn.
C C
T1042
SATA
MDI MDI SGMII PHY SATA Conn.
RJ45 Magnetics SGMII
RTL8211DN

QE
SPI TDM Riser Card Conn.
I2C2CH3

I2C1
TMDS
TMDS DVI XCVR
HDMI I2C Protect QE PROFIBUS
CH7301C DIU ISOLATE HEADER
DIU MUX
QE
DIU 74CB3Q3253
LVDS LDI XCVR
LCD
DS90C387R

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 2 of 38


1 2 3 4 5
1 2 3 4 5

U1A
DDR_ECC[0..7]
DDR_ECC0 L24
DDR CONTROLLER
T27 DDR_MCK0_P
T104X DDR4 MEMORY INTERFACE
J1A 1V2_SLP decoupling caps on page 13
J1B

DDR_ECC1 D1_MECC0 1 of 15 D1_MCK0 DDR_MCK0_N DDR_MA[0..15] DDR_DQ[0..63]


N23 T28 1 96
DDR_ECC2 T23 D1_MECC1 D1_MCK0_B R27 DDR_MCK1_P DDR_MA0 79 5 DDR_DQ0 1V2_SLP 145 NC1_12V GND0 2
DDR_ECC3 U23 D1_MECC2 D1_MCK1 R28 DDR_MCK1_N DDR_MA1 72 A0 DQ0 150 DDR_DQ1 1V2 NC13_12V GND1 4
DDR_ECC4 L23 D1_MECC3 D1_MCK1_B K22 DDR_MA2 216 A1 DQ1 12 DDR_DQ2 59 GND2 6
DDR_ECC5 M23 D1_MECC4 TEST_OUT4 M22 DDR_MA3 71 A2 DQ2 157 DDR_DQ3 C1 0.1uF 61 VDD0 GND3 9
DDR_ECC6 R24 D1_MECC5 TEST_OUT5 U22 DDR_MA4 214 A3 DQ3 3 DDR_DQ4 C5 0.1uF 64 VDD1 GND4 11
DDR_ECC7 T24 D1_MECC6 TEST_OUT6 P22 DDR_MA5 213 A4 DQ4 148 DDR_DQ5 C6 0.1uF 67 VDD2 GND5 13
DDR_DQ[0..63] D1_MECC7 TEST_OUT7 DDR_MA6 69 A5 DQ5 10 DDR_DQ6 C7 0.1uF 70 VDD3 GND6 15
A DDR_DQ0 C21 A24 DDR_MDQS0_P DDR_MA7 211 A6 DQ6 155 DDR_DQ7 C2 0.1uF 73 VDD4 GND7 17 A
DDR_DQ1 A22 D1_MDQ00 D1_MDQS0 D26 DDR_MDQS1_P DDR_MA8 68 A7 DQ7 16 DDR_DQ8 C8 0.1uF 76 VDD5 GND8 20
DDR_DQ2 A26 D1_MDQ01 D1_MDQS1 G24 DDR_MDQS2_P DDR_MA9 66 A8 DQ8 161 DDR_DQ9 C9 0.1uF 80 VDD6 GND9 22
DDR_DQ3 B26 D1_MDQ02 D1_MDQS2 L25 DDR_MDQS3_P DDR_MA10 225 A9 DQ9 23 DDR_DQ10 C10 0.1uF 83 VDD7 GND10 24
DDR_DQ4 B21 D1_MDQ03 D1_MDQS3 W25 DDR_MDQS4_P DDR_MA11 210 A10/AP DQ10 168 DDR_DQ11 C14 0.01uF 85 VDD8 GND11 26
DDR_DQ5 A21 D1_MDQ04 D1_MDQS4 AA23 DDR_MDQS5_P DDR_MA12 65 A11 DQ11 14 DDR_DQ12 C15 0.01uF 88 VDD9 GND12 28
DDR_DQ6 B24 D1_MDQ05 D1_MDQS5 AE25 DDR_MDQS6_P DDR_MA13 232 A12/BC DQ12 159 DDR_DQ13 C17 1000pF 90 VDD10 GND13 31
DDR_DQ7 A25 D1_MDQ06 D1_MDQS6 AG24 DDR_MDQS7_P DDR_MA14 234 A13 DQ13 21 DDR_DQ14 C18 1000pF 92 VDD11 GND14 33
DDR_DQ8 C23 D1_MDQ07 D1_MDQS7 R23 DDR_MDQS8_P DDR_MBA[0..2] DDR_MA15 A17/NC20 DQ14 166 DDR_DQ15 204 VDD12 GND15 35
DDR_DQ9 C24 D1_MDQ08 D1_MDQS8 DDR_MBA0 81 DQ15 27 DDR_DQ16 209 VDD13 GND16 37
DDR_DQ10 F25 D1_MDQ09 A23 DDR_MDQS0_N DDR_MBA1 224 BA0 DQ16 172 DDR_DQ17 Decoupling between 212 VDD14 GND17 39
DDR_DQ11 F26 D1_MDQ10 D1_MDQS0_B D25 DDR_MDQS1_N DDR_MBA2 63 BA1 DQ17 34 DDR_DQ18 1V2 and 1V2_SLP
215 VDD15 GND18 42
power split located under UDIMMS.
DDR_DQ12 D22 D1_MDQ11 D1_MDQS1_B G23 DDR_MDQS2_N 207 BG0 DQ18 179 DDR_DQ19 Place these caps around DDR 217 VDD16 GND19 44
DDR_DQ13 D23 D1_MDQ12 D1_MDQS2_B K25 DDR_MDQS3_N BG1 DQ19 25 DDR_DQ20 Power Pin areas to stitch return 220 VDD17 GND20 46
D1_MDQ13 D1_MDQS3_B DQ20 current flow for Address and VDD18 GND21
DDR_DQ14 B27 V25 DDR_MDQS4_N 62 170 DDR_DQ21 command signals. 223 48
DDR_DQ15 E25 D1_MDQ14 D1_MDQS4_B Y23 DDR_MDQS5_N ACT DQ21 32 DDR_DQ22 226 VDD19 GND22 50
DDR_DQ16 E23 D1_MDQ15 D1_MDQS5_B AF25 DDR_MDQS6_N DDR_MCK0_P 74 DQ22 177 DDR_DQ23 229 VDD20 GND23 53
DDR_DQ17 E24 D1_MDQ16 D1_MDQS6_B AH24 DDR_MDQS7_N DDR_MCK0_N 75 CK0_P DQ23 38 DDR_DQ24 231 VDD21 GND24 55
DDR_DQ18 J23 D1_MDQ17 D1_MDQS7_B P23 DDR_MDQS8_N CK0_N DQ24 183 DDR_DQ25 233 VDD22 GND25 57
DDR_DQ19 K23 D1_MDQ18 D1_MDQS8_B DDR_MDM[0..8] DDR_MCK1_P 218 DQ25 45 DDR_DQ26 236 VDD23 GND26 94
DDR_DQ20 F22 D1_MDQ19 B22 DDR_MDM0 DDR_MCK1_N 219 CK1_P DQ26 190 DDR_DQ27 206 VDD24 GND27 98
DDR_DQ21 H22 D1_MDQ20 D1_MDM0 C25 DDR_MDM1 CK1_N DQ27 36 DDR_DQ28 VDD25 GND28 101
DDR_DQ22 H23 D1_MDQ21 D1_MDM1 F23 DDR_MDM2 DDR_MDQS0_P 153 DQ28 181 DDR_DQ29 VPP 142 GND29 103
DDR_DQ23 J24 D1_MDQ22 D1_MDM2 K26 DDR_MDM3 DDR_MDQS0_N 152 DQS0_P DQ29 43 DDR_DQ30 143 VPP1 GND30 105
B D1_MDQ23 D1_MDM3 DQS0_N DQ30 VPP2 GND31 B
DDR_DQ24 H26 U26 DDR_MDM4 DDR_MDQS1_P 164 188 DDR_DQ31 286 107
DDR_DQ25 J25 D1_MDQ24 D1_MDM4 Y24 DDR_MDM5 DDR_MDQS1_N 163 DQS1_P DQ31 97 DDR_DQ32 1V2_SLP 287 VPP3 GND32 109
DDR_DQ26 P26 D1_MDQ25 D1_MDM5 AD24 DDR_MDM6 DDR_MDQS2_P 175 DQS1_N DQ32 242 DDR_DQ33 VTT 288 VPP4 GND33 112
DDR_DQ27 N25 D1_MDQ26 D1_MDM6 AF24 DDR_MDM7 DDR_MDQS2_N 174 DQS2_P DQ33 104 DDR_DQ34 VPP5 GND34 114
DDR_DQ28 G25 D1_MDQ27 D1_MDM7 N24 DDR_MDM8 DDR_MDQS3_P 186 DQS2_N DQ34 249 DDR_DQ35 C21 77 GND35 116
DDR_DQ29 H25 D1_MDQ28 D1_MDM8 DDR_MDQS3_N 185 DQS3_P DQ35 95 DDR_DQ36 MVREF 221 VTT1 GND36 118
DDR_DQ30 M26 D1_MDQ29 DDR_MDQS4_P 245 DQS3_N DQ36 240 DDR_DQ37 0.1uF VTT2 GND37 120
DDR_DQ31 M25 D1_MDQ30 DDR_MDQS4_N 244 DQS4_P DQ37 102 DDR_DQ38 146 GND38 123
DDR_DQ32 T25 D1_MDQ31 DDR_MDQS5_P 256 DQS4_N DQ38 247 DDR_DQ39 VREFCA GND39 125
DDR_DQ33 U25 D1_MDQ32 DDR_MDQS5_N 255 DQS5_P DQ39 108 DDR_DQ40 C22 3V3_SLP 284 GND40 127
DDR_DQ34 AA26 D1_MDQ33 Y21 DDR_MDQS6_P 267 DQS5_N DQ40 253 DDR_DQ41 VDDSPD GND41 129
DDR_DQ35 AA25 D1_MDQ34 TEST_OUT8 DDR_MDQS6_N 266 DQS6_P DQ41 115 DDR_DQ42 0.1uF 144 GND42 131
D1_MDQ35 (DDR4 ONLY) DQS6_N DQ42 RFU1 GND43
DDR_DQ36 P25 DDR_MDQS7_P 278 260 DDR_DQ43 205 134
DDR_DQ37 R25 D1_MDQ36 DDR_MDQS7_N 277 DQS7_P DQ43 106 DDR_DQ44 C23 227 RFU2 GND44 136
DDR_DQ38 W26 D1_MDQ37 DDR_MDQS8_P 197 DQS7_N DQ44 251 DDR_DQ45 RFU3 GND45 138
DDR_DQ39 Y25 D1_MDQ38 DDR_MBA[0..2] DDR_MDQS8_N 196 DQS8_P DQ45 113 DDR_DQ46 0.1uF 200 GND46 147
DDR_DQ40 V24 D1_MDQ39 Y28 DDR_MBA0 DQS8_N DQ46 258 DDR_DQ47 202 GND71 GND47 149
D1_MDQ40 DDR4 D1_MBA0 DQ47 GND72 GND48
DDR_DQ41 W23 NAMES W28 DDR_MBA1 DDR_MCS0_N 84 119 DDR_DQ48 VTT 239 151
DDR_DQ42 AA22 D1_MDQ41 D1_MBA1 E28 DDR_MBA2 DDR_MCS1_N 89 S0 DQ48 264 DDR_DQ49 241 GND73 GND49 154
D1_MDQ42 BG0 D1_MBA2 CS1/NC7 DQ49 GND74 GND50
DDR_DQ43 AC22 DDR_MA[0..15] DDR_MCS2_N 93 126 DDR_DQ50 C24 47uF 243 156
DDR_DQ44 W22 D1_MDQ43 V28 DDR_MA0 DDR_MCS3_N 237 CS2/NC8 DQ50 271 DDR_DQ51 246 GND75 GND51 158
DDR_DQ45 V23 D1_MDQ44 D1_MA00 N28 DDR_MA1 235 CS3/C1/NC22 DQ51 117 DDR_DQ52 C25 0.1uF 248 GND76 GND52 160
DDR_DQ46 AB24 D1_MDQ45 D1_MA01 N27 DDR_MA2 DDR_MCAS_N 86 C2/NC21 DQ52 262 DDR_DQ53 250 GND77 GND53 162
DDR_DQ47 AB23 D1_MDQ46 D1_MA02 M28 DDR_MA3 DDR_MRAS_N 82 CAS/A15 DQ53 124 DDR_DQ54 C26 0.1uF 252 GND78 GND54 165
C C
DDR_DQ48 AD26 D1_MDQ47 D1_MA03 L27 DDR_MA4 DDR_MWE_N 228 RAS/A16 DQ54 269 DDR_DQ55 254 GND79 GND55 167
DDR_DQ49 AD25 D1_MDQ48 D1_MA04 L28 DDR_MA5 DDR_MDM[0..8] WE/A14 DQ55 130 DDR_DQ56 C27 0.1uF 257 GND80 GND56 169
DDR_DQ50 AD23 D1_MDQ49 D1_MA05 K28 DDR_MA6 DDR_MDM0 7 DQ56 275 DDR_DQ57 259 GND81 GND57 171
DDR_DQ51 AE22 D1_MDQ50 D1_MA06 J28 DDR_MA7 8 DQS9_P/DM0 DQ57 137 DDR_DQ58 C28 0.1uF 261 GND82 GND58 173
DDR_DQ52 AB25 D1_MDQ51 D1_MA07 J27 DDR_MA8 DDR_MDM1 18 DQS9_N/NC2 DQ58 282 DDR_DQ59 263 GND83 GND59 176
DDR_DQ53 AC25 D1_MDQ52 D1_MA08 G27 DDR_MA9 19 DQS10_P/DM1 DQ59 128 DDR_DQ60 265 GND84 GND60 178
DDR_DQ54 AC23 D1_MDQ53 D1_MA09 Y27 DDR_MA10 DDR_MDM2 29 DQS10_N/NC3 DQ60 273 DDR_DQ61 268 GND85 GND61 180
DDR_DQ55 AE23 D1_MDQ54 D1_MA10 H28 DDR_MA11 30 DQS11_P/DM2 DQ61 135 DDR_DQ62 270 GND86 GND62 182
DDR_DQ56 AG25 D1_MDQ55 D1_MA11 G28 DDR_MA12 DDR_MDM3 40 DQS11_N/NC4 DQ62 280 DDR_DQ63 272 GND87 GND63 184
DDR_DQ57 AH25 D1_MDQ56 D1_MA12 AE28 DDR_MA13 41 DQS12_P/DM3 DQ63 DDR_ECC[0..7] 274 GND88 GND64 187
DDR_DQ58 AH22 D1_MDQ57 D1_MA13 E27 DDR_MA14 DDR_MDM4 99 DQS12_N/NC5 49 DDR_ECC0 276 GND89 GND65 189
D1_MDQ58 BG1 D1_MA14 DQS13_P/DM4 CB0 GND90 GND66
DDR_DQ59 AF22 D28 DDR_MA15 100 194 DDR_ECC1 279 191
D1_MDQ59 ACT_B D1_MA15 DQS13_N/NC9 CB1/NC15 GND91 GND67
DDR_DQ60 AF26 DDR_MDM5 110 56 DDR_ECC2 281 193
DDR_DQ61 AH26 D1_MDQ60 AA28 DDR_MRAS_N 111 DQS14_P/DM5 CB2 201 DDR_ECC3 283 GND92 GND68 195
D1_MDQ61 A16 D1_MRAS_B DQS14_N/NC10 CB3/NC17 GND93 GND69
DDR_DQ62 AH23 AC28 DDR_MCAS_N DDR_MDM6 121 47 DDR_ECC4 198
D1_MDQ62 A15 D1_MCAS_B DQS15_P/DM6 CB4 GND70
DDR_DQ63 AF23 AB27 DDR_MWE_N 122 192 DDR_ECC5
D1_MDQ63 A14 D1_MWE_B DQS15_N/NC11 CB5/NC14
DDR_MDM7 132 54 DDR_ECC6 DDR_MAPAR_OUT 222 78
1V2 AB28 DDR_MCS0_N 133 DQS16_P/DM7 CB6 199 DDR_ECC7 230 PARITY EVENT 208
D1_MCS0_B AC27 DDR_MCS1_N DDR_MDM8 51 DQS16_N/NC12 CB7/NC16 NC19/SAVE ALERT
R1 162 1% U28 D1_MCS1_B AG27 DDR_MCS2_N 52 DQS17_P/DM8
D1_MDIC1 M1_C0 D1_MCS2_B DQS17_N/NC6
AF28 DDR_MCS3_N DDR4_DIMM
M1_C1 D1_MCS3_B
R2 162 1% P28 DDR_MCKE0 60 DDR_MAPAR_ERR
D1_MDIC0 DDR_MCKE0 35 DDR_MCKE0 DDR_MCKE1 CKE0
C27 203
D1_MCKE0 35 DDR_MCKE1 CKE1/NC18
D R3 10K C28 DDR_MCKE1 DDR_MODT0 87 D
DDR_MAPAR_ERR F28 ALERT_B D1_MCKE1 H21 DDR_MODT1 91 ODT0
DDR_MAPAR_OUT V27 D1_MAPAR_ERR_B TEST_OUT0 F21 ODT1
D1_MAPAR_OUT TEST_OUT1 58
DDR_MODT0 29 DDR_RST_N RESET
R4 0 F20 AD28 3V3_SLP
D1_MVREF D1_MODT0 AE27 DDR_MODT1 R5 1K 139 141 Title
M1_C2 D1_MODT1 1V2_SLP SA0 SCL I2C1_SCL_SLP 7,14,31,32
UNUSED FOR DDR4 W21 140 285 T104XRDB
TEST_OUT2 SA1 SDA I2C1_SDA_SLP 7,14,31,32
J20 V21 238
D1_TPA TEST_OUT3 SPD ADDR = 0x51 SA2 Size Document Number Design Engineer Rev
B <Doc> MICETEK A
T1040 DDR4_DIMM
Date: Monday, December 22, 2014 Sheet 3 of 38
1 2 3 4 5
1 2 3 4 5

T104X IFC INTERFACE


1V8 1V8 1V8 1V8 1V8 1V8 1V8

R6 20K
R7 20K
R8 20K R14 R9 R10 R11 R15 R12
R13 20K CS0: NOR or NAND
R16 20K U1D 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K CS1: NAND or NOR
CS2: CPLD
A 5,29 IFC_AD[0..15] IFC_AD0 IFC INTERFACE A
A4 C13
IFC_AD1 B5 IFC_AD00 4 of 15 IFC_CS0_B E15
IFC_CS0_N 29
IFC_AD01 IFC_CS1_B IFC_CS1_N 29
IFC_AD2 A5 D16
IFC_AD02 IFC_CS2_B IFC_CS2_N 29
IFC_AD3 B6 C16
IFC_AD4 A6 IFC_AD03 IFC_CS3_B E17
IFC_AD5 A7 IFC_AD04 IFC_CS4_B C17 R17 20K
IFC_AD6 B8 IFC_AD05 IFC_CS5_B D18 R18 20K 1V8
IFC_AD7 A8 IFC_AD06 IFC_CS6_B C19 R19 20K
IFC_AD8 B9 IFC_AD07 IFC_CS7_B R20 20K
IFC_AD9 A9 IFC_AD08 D13
IFC_AD09 IFC_WE0_B IFC_WE_N 5,29
IFC_AD10 A10
IFC_AD11 B11 IFC_AD10
IFC_AD12 A11 IFC_AD11
IFC_AD13 B12 IFC_AD12
IFC_AD14 A12 IFC_AD13 F16
IFC_AD14 (WE1_B) IFC_CLE IFC_CLE 5,29
IFC_AD15 A13
IFC_AD15 D15
IFC_OE_B IFC_OE_N 5,29
B15
4,5,29 IFC_A[5..31] IFC_A16 IFC_RB0_B IFC_RB0_N 29
C5 A15
IFC_A16 IFC_RB1_B IFC_RB1_N 29
IFC_A17 C6 F17
IFC_A17 IFC_WP0_B IFC_WP_N 5,29
IFC_A18 D7
IFC_A19 C7 IFC_A18 D17
IFC_A19 IFC_AVD IFC_AVD 5
IFC_A20 cfg_test_port_dis D8 A14
B IFC_A20 IFC_BCTL B
IFC_A21 C8 B14 IFC_TE
IFC_A22 D9 IFC_A21 IFC_TE
IFC_A23 C9 IFC_A22 A17 R21 22
IFC_A23 IFC_CLK0 IFC_CLK 29
IFC_A24 D10 A19
IFC_A25 C10 IFC_A24 IFC_CLK1
IFC_A26 E11 IFC_A25
IFC_A27 C11 IFC_A26 D14
IFC_A28 IFC_A27 IFC_NDDDR_CLK IFC_NDWE_N 5
D11 A16
IFC_A29 C12 IFC_A28 IFC_NDDQS
IFC_A30 D12 IFC_A29 E14
IFC_A31 E12 IFC_A30 IFC_PERR_B
IFC_A31 C15
IFC_PAR0 C14
R22 IFC_PAR1
DNP
4.7K T1040

U2

IFC_AD5 IFC_A5 IFC_A[5..31] 4,5,29


47 2 R23 33
IFC_AD6 46 1D1 1Q1 3 R24 33 IFC_A6
IFC_AD7 44 1D2 1Q2 5 R25 33 IFC_A7
T104X RESET CONFIGURATION IFC_AD8 43 1D3 1Q3 6 R26 33 IFC_A8
C C
cfg_rcw_src[0:8] IFC_AD9 41 1D4 1Q4 8 R27 33 IFC_A9
0_0010_0111: NOR FLASH BOOT IFC_AD10 40 1D5 1Q5 9 R28 33 IFC_A10
0_0100_0000: SD CARD BOOT IFC_AD11 38 1D6 1Q6 11 R29 33 IFC_A11
0_0100_0101: SPI BOOT IFC_AD12 37 1D7 1Q7 12 R30 33 IFC_A12
1_0001_1001: NAND FLASH BOOT 1D8 1Q8
48
SW1 1 LE1
OE1
IFC_AD8 ON IFC_AD13 IFC_A13
cfg_rcw_src0 1 16 R31 4.7K 36 13 R32 33
IFC_AD9 cfg_rcw_src1 2 1 16 15 R33 4.7K IFC_AD14 35 2D1 2Q1 14 R34 33 IFC_A14
IFC_AD10 cfg_rcw_src2 3 2 15 14 R35 4.7K IFC_AD15 33 2D2 2Q2 16 R36 33 IFC_A15
IFC_AD11 cfg_rcw_src3 4 3 14 13 R37 4.7K 32 2D3 2Q3 17
IFC_AD12 cfg_rcw_src4 5 4 13 12 R38 4.7K 30 2D4 2Q4 19
IFC_AD13 cfg_rcw_src5 6 5 12 11 R39 4.7K 29 2D5 2Q5 20
IFC_AD14 cfg_rcw_src6 7 6 11 10 R40 4.7K 27 2D6 2Q6 22
IFC_AD15 cfg_rcw_src7 8 7 10 9 R41 4.7K 26 2D7 2Q7 23
8 9 2D8 2Q8
25
SWITCH_DIP_8 24 LE2
SW2 OE2
4
IFC_CLE ON GND
cfg_rcw_src8 1 16 R42 4.7K 10
IFC_TE cfg_ifc_te 2 1 16 15 R43 4.7K 1V8 1V8 GND 15
D IFC_A18 cfg_pll_config_sel_b 3 2 15 14 R44 4.7K GND 21 D
IFC_A19 cfg_por_ainit 4 3 14 13 R45 4.7K 7 GND 28
IFC_A16 cfg_svr0 5 4 13 12 R46 4.7K 18 VCC GND 34
IFC_A17 cfg_svr1 6 5 12 11 R48 4.7K C29 C30 C31 C32 31 VCC GND 39
IFC_A21 cfg_dram_type 7 6 11 10 R47 4.7K 42 VCC GND 45
IFC_AVD cfg_rsp_dis 8 7 10 9 R49 4.7K 0.1uF 0.1uF 0.1uF 0.1uF VCC GND Title
8 9 T104XRDB
74LVC16373
SWITCH_DIP_8 Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 4 of 38


1 2 3 4 5
1 2 3 4 5

T104X NOR and NAND FLASH INTERFACE


1V8 1V8 1V8

R50 R51 R52


128MB 16-BIT NOR FLASH

4.7K 4.7K 4.7K U3


A A
4,29 IFC_A[5..31] IFC_A30 IFC_AD15 IFC_AD[0..15] 4,5,29
31 35
IFC_A29 26 A0 DQ0 37 IFC_AD14
IFC_A28 25 A1 DQ1 39 IFC_AD13
IFC_A27 24 A2 DQ2 41 IFC_AD12
IFC_A26 23 A3 DQ3 44 IFC_AD11
IFC_A25 22 A4 DQ4 46 IFC_AD10
IFC_A24 21 A5 DQ5 48 IFC_AD9
IFC_A23 20 A6 DQ6 50 IFC_AD8
IFC_A22 10 A7 DQ7 36 IFC_AD7
IFC_A21 9 A8 DQ8 38 IFC_AD6
IFC_A20 8 A9 DQ9 40 IFC_AD5
IFC_A19 7 A10 DQ10 42 IFC_AD4
IFC_A18 6 A11 DQ11 45 IFC_AD3
IFC_A17 5 A12 DQ12 47 IFC_AD2
IFC_A16 4 A13 DQ13 49 IFC_AD1
IFC_A15 3 A14 DQ14 51 IFC_AD0
IFC_A14 54 A15 DQ15/A-1 1V8
IFC_A13 19 A16
IFC_A12 18 A17
IFC_A11 11 A18 1V8
IFC_A10 12 A19 NOR_RB_N 29
R53
1GB 8-BIT NAND FLASH
IFC_A9 15 A20
IFC_A8 2 A21 4.7K U4A
B A22 B
1 R54
A23 IFC_AD[0..15] 4,5,29
56 C6 H4 IFC_AD7
A24 29 NAND_CS_N CE I/O0
55 1K J4 IFC_AD6
A25 D5 I/O1 K4 IFC_AD5
4,29 IFC_CLE CLE I/O2
32 17 C4 K5 IFC_AD4
29 NOR_CS_N CE RDY/BUSY 4 IFC_AVD ALE I/O3 IFC_AD3
34 K6
4,5,29 IFC_OE_N OE I/O4 IFC_AD2
13 D4 J7
4,29 IFC_WE_N WE 4,5,29 IFC_OE_N RE I/O5 IFC_AD1
C7 K7
4 IFC_NDWE_N WE I/O6
14 J8 IFC_AD0
29 NOR_RST_N RESET I/O7
27 C3
NC1 4,29 IFC_WP_N WP
1V8 53 28 G5 C8
BYTE NC2 LOCK R/B NAND_RB_N 29
16 30
WP/ACC NC3 D3 C5 1V8
1V8 3V3 43 33 1V8 G4 VCC VSS F7
R55 29 VCC GND 52 H8 VCC VSS K3
VIO GND J6 VCC VSS K8
4.7K VCC VSS R56
JS28F00AM29EWHA
MT29F8G08ABBCAH4:C 1K
IFC_VA5
IFC_VA6
IFC_VA7 U4B

C 1V8 H6 H3 C
U5 H7 NC1 NC21 H5
IFC_A7 1 5 J3 NC2 NC22 A1
I0 VCC 4 J5 NC3 NC23 A2
29 CFG_VBANK[0..2] CFG_VBANK2 O NC4 NC24
2 3 D6 B1
I1 GND 1V8 D7 NC5 NC25 A9
74LVC1G86 D8 NC6 NC26 A10
E3 NC7 NC27 B9
1V8 E4 NC8 NC28 B10
U6 C33 C34 C35 C36 E5 NC9 NC29 L1
IFC_A6 1 5 E6 NC10 NC30 L2
I0 VCC 4 1uF 0.1uF 0.1uF 0.1uF E7 NC11 NC31 M1
CFG_VBANK1 2 O 3 E8 NC12 NC32 M2
I1 GND F3 NC13 NC33 L9
74LVC1G86 F4 NC14 NC34 L10
F5 NC15 NC35 M9
1V8 F6 NC16 NC36 M10
U7 F8 NC17 NC37
IFC_A5 1 5 G6 NC18 G3
I0 VCC 4 G7 NC19 DNU1 G8
CFG_VBANK0 2 O 3 NC20 DNU2
I1 GND
74LVC1G86 MT29F8G08ABBCAH4:C

D 1V8 3V3 D
1V8

C38 C39 C40 C41 C42 C43


Title
0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 5 of 38


1 2 3 4 5
1 2 3 4 5

T104X SPI FLASH and SDHC INTERFACE

3V3 3V3 3V3 3V3

A A
R57 R58 R59 R60
3V3 3V3
4.7K 4.7K 4.7K 4.7K 64MB SERIAL FLASH
R61 33
R62 R63

U1C 4.7K 4.7K U8 3V3


SPI / SDHC Interfaces
P2 R64 51 15 8
3 of 15 SPI_MOSI SI SO
P1 16
SPI_MISO N1 R65 10 R66 51 7 SCK C44 C45
SPI_CLK SPI_CS0_N CS
M1 9 3 1uF 0.1uF
(SD_DAT4) SPI_CS0_B WP NC1
M2 1 4
(SD_DAT5) SPI_CS1_B TDMR_SPI_CS0_N 15 SPI_CLK 15 HOLD NC2
M3 5
(SD_DAT6) SPI_CS2_B TDMR_SPI_CS1_N 15 SPI_MISO 15 NC3
N3 3V3 6
(SD_DAT7) SPI_CS3_B SPI_MOSI 15 NC4 11
2 NC5 12
VCC NC6 13
10 NC7 14
L2 SDHC_DAT0 GND NC8
SDHC_DAT0 K4 SDHC_DAT1
B SDHC_DAT1 B
L3 SDHC_DAT2 MT25QL512ABA1ESF-0SIT
SDHC_DAT2 L1 SDHC_DAT3 CO-LAYOUT
SDHC_DAT3 EVDD CAN BE 3.3V or 1.8V EVDD 3V3 U9 DNP
K1 R67 0 SDHC_CLK
SDHC_CLK K3 SDHC_CMD R69 10K 8
SDHC_CMD R68 10K VCC
R70 10K 5 2
L5 SDHC_CD_N R71 10K 6 SI SO
SDHC_CD_B M5 SDHC_WP 1 SCK
SDHC_WP R72 10K 3 CS
R73 10K 7 WP
T1040 3V3 HOLD
4
R74 10K 9 GND VDD_SD
R75 10K EPAD

N25Q512A13GF840F
C46 C47

U10 1uF 0.1uF


SD CARD VDD MANUAL SELECTION 1 8

3V3 VDD_SD EVDD 2 7


C J2 VDD_SD C
1 9 J3
2 9
3 3 6 1 D2/RSV
2 D3/CS
JMP3 4 5 3 CMD/DIN
4 VSS 10
RClamp0524J.TCT 5 VDD INSERT 11
U11 6 CLK/SCLK PROTECT
1 8 7 VSS 12
8 D0/DOUT COM1 13
2 7 D1/RSV COM2
SD_CARD_SKT
9

3 6

4 5

RClamp0524J.TCT

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 6 of 38


1 2 3 4 5
1 2 3 4 5

T104X SYSTEM LOGIC INTERFACE


1V8_SLP 2V5_SLP 3V3 1V8 1V8_SLP
TEMP_DIODE_P 14
TEMP_DIODE_N 14
1V8_SLP 1V8_SLP
EVT_PWR_EN 29
EVT_PWR_OK 29

1K
1K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
EVT0_N 29
EVT1_N 29
R94 R95
A EVT4_N 29 A
TEST_SEL_B U1F 4.7K 4.7K 3V3
FOR T1040/T1042, PULL-DOWN
System Logic

R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
FOR T1020/T1022, PULL-UP F9 E21
G8 SCAN_MODE_B 6 of 15 TD1_ANODE G21
29 TEST_SEL_N TEST_SEL_B TD1_CATHODE

1
Q2 3V3_SLP 3V3_SLP
F7 IRLML6346
29 CPLD_INT1_N IRQ00
D3 2 3
29 CPLD_INT2_N IRQ01
E9 3V3 3V3
14 RTC_INT_N IRQ02
D1 R96 R97
29 SDHC_VS IRQ03
D4 D6
20 EC2_INT_N IRQ04 EVT0_B

1
D5 C4 4.7K 4.7K
20 EC2_PME_N IRQ05 EVT1_B
AB4 C1 R98 R99 Q3
19 EC1_INT_N IRQ06 EVT2_B
AD5 C2 IRLML6346
19 EC1_PME_N IRQ07 EVT3_B I2C1_SCL_SLP 3,14,31,32
AB1 C3 4.7K 4.7K 2 3
21 SG_INT_N IRQ08 EVT4_B I2C1_SDA_SLP 3,14,31,32
AC5
29 GPIO_CKE_ISO IRQ09
L4 W1
IRQ10 IIC1_SCL I2C1_SCL 14,16,17
U3 V1
IRQ11 IIC1_SDA I2C1_SDA 14,16,17
A3 V3
29 EVT_BRD_ISO IRQ_OUT_B IIC2_SCL Y3 U12
F19 IIC2_SDA 3V3
R6 TMP_DETECT_B V2 R100 4.7K R101 4.7K 14 5
B LP_TMP_DETECT_B (T2081 only)
IIC3_SCL SCL SC0 I2C2_MPEX1_SCL 27 B
W3 R102 4.7K R103 4.7K 15 4
IIC3_SDA SDA SD0 I2C2_MPEX1_SDA 27
1V8_SLP R104 4.7K F13 AA3 7
PORESET_B IIC4_SCL DIU_HSYNC 11 SC1 I2C2_MPEX2_SCL 27
R105 4.7K E8 AB3 3V3 6
HRESET_B IIC4_SDA DIU_VSYNC 11 SD1 I2C2_MPEX2_SDA 27
R106 4.7K B3
3V3 RESET_REQ_B R107 4.7K 3 10
RESET SC2 I2C2_HDMI_SCL 16
AA1 9
29 PORESET_N UART1_SIN UART1_RXD 14 SD2 I2C2_HDMI_SDA 16
R108 4.7K P5 AA2 1
29 HRESET_N DMA1_DREQ0_B UART1_SOUT UART1_TXD 14 A0
cfg_test_port_mux_sel U5 Y2 2 12
29 RESET_REQ_N DMA1_DACK0_B UART1_CTS_B UART1_CTS_N 14 A1 SC3 I2C2_PEX_SCL 27
R5 Y1 3V3 13 11
DMA1_DDONE0_B UART1_RTS_B UART1_RTS_N 14 A2 SD3 I2C2_PEX_SDA 27
R109 4.7K V5
AA5 DMA2_DREQ0_B 16 8
Y5 DMA2_DACK0_B W4 VDD VSS
DMA2_DDONE0_B UART2_SIN UART2_RXD 14
AA4 C48
UART2_SOUT UART2_TXD 14
Y4 PCA9546APW
UART2_CTS_B UART2_CTS_N 14
A18 V4 0.1uF
29 JTAG_TDI TDI UART2_RTS_B UART2_RTS_N 14
C18
29 JTAG_TDO TDO
E18 XVDD use 1.35V I2C ADDR = 0x77
29 JTAG_TCK TCK
B18 B2 ASLEEP cfg_xvdd_sel R110 4.7K 1V8_SLP
29 JTAG_TMS TMS ASLEEP
D19 F18 R111 4.7K 1V8
29 JTAG_TRST_N TRST_B CKSTP_OUT_B

G15 E6 TP1 1V8_SLP 3V3_SLP


30 SYS_REFCLK SYSCLK CLK_OUT
C J21 B20 U13 C
30 DDR_REFCLK DDRCLK FA_ANALOG_PIN C20 1 5 LABEL = ASLEEP
G14 FA_ANALOG_G_V 2 VCC1 VCC D1
31 SYS_REFCLK_P DIFF_SYSCLK A
F14 3 4 R112 510 2 1
31 SYS_REFCLK_N DIFF_SYSCLK_B GND O
R113 R114
TP2 B17 1% 1% FXLP34P5X GRN
RTC 698 698
CKSTP_OUT_N 29
R115 T1040
1V8_SLP 3V3_SLP
10K

C49 C50
29 COP_CKSTP_OUT_N
0.1uF 0.1uF
29 COP_HRESET_N
29 COP_SRESET_N
3V3_SLP 3V3_SLP
29 COP_TMS
29 COP_TCK
29 COP_TDI
29 COP_TDO
R116 R117
COP CONNECTOR
3V3_SLP J4 10 10K

D R118 10K 1 2 D
3 4 COP_TRST_N 29
R119 10K
R120 10K 5 6
R121 10K 7 8
R122 10K 9 10
R123 10K 11 12 Title
13 14 T104XRDB
15 16
HTST-108-01-L-DV Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 7 of 38


1 2 3 4 5
1 2 3 4 5

T104X ETHERNET and SERDES INTERFACE

U1E
19 EC1_TXD[0..3] EC1_TXD0 ETHERNET EC2_TXD0 EC2_TXD[0..3] 20
R133 10 AE3 AE7 R124 10
A EC1_TXD1 EC1_TXD0 5 of 15 EC2_TXD0 EC2_TXD1 A
R125 10 AE4 AF7 R126 10
EC1_TXD2 R127 10 AD3 EC1_TXD1 EC2_TXD1 AF6 R128 10 EC2_TXD2
EC1_TXD3 R129 10 AC3 EC1_TXD2 EC2_TXD2 AG5 R130 10 EC2_TXD3
R131 4.7K EC1_TXD3 EC2_TXD3 R134 4.7K
R135 10 AF4 AF8 R136 10
19 EC1_TXCTL EC1_TX_CTL EC2_TX_CTL EC2_TXCTL 20
R132 10 AF3 AE8 R137 10
19 EC1_GTXCLK EC1_GTX_CLK EC2_GTX_CLK EC2_GTXCLK 20
C51 10pF AC4 C52 10pF
DNP EC1_TX_ER DNP
19 EC1_RXD[0..3] EC2_RXD[0..3] 20
EC1_RXD0 AF2 AH8 EC2_RXD0
EC1_RXD1 AF1 EC1_RXD0 EC2_RXD0 AG7 EC2_RXD1
EC1_RXD2 AE1 EC1_RXD1 EC2_RXD1 AH7 EC2_RXD2
EC1_RXD3 AD2 EC1_RXD2 EC2_RXD2 AH6 EC2_RXD3
R710 0 DNP R711 0 DNP EC1_RXD3 EC2_RXD3 R712 0 DNP R713 0 DNP
AG2 AG8
19 EC1_RXCTL EC1_RX_CTL EC2_RX_CTL EC2_RXCTL 20
R714 0 3 inch delay line R715 0 AD1 AH5 R716 0 3 inch delay line R717 0
19 EC1_RXCLK EC1_RX_CLK EC2_RX_CLK EC2_RXCLK 20
AG3 AC6
19 EC1_REFCLK EC1_GTX_CLK125 EC2_GTX_CLK125 EC2_REFCLK 20
AC2
AC1 EC1_RX_ER
EC1_COL
R138 10 AH3 L6
19 EMI1_MDC_SLP EMI1_MDC EMI2_MDC
19 EMI1_MDIO_SLP
AH4
EMI1_MDIO T2081 only { EMI2_MDIO
M6

AC8 AD7 TP3


R139 R140 AB6 TSEC_1588_CLK_IN TSEC_1588_CLK_OUT AF5 TP4
B TSEC_1588_TRIG_IN1 TSEC_1588_ALARM_OUT1 B
AE5 AC7 TP5
2V5_SLP 2V5_SLP 1.5K 4.7K TSEC_1588_TRIG_IN2 TSEC_1588_ALARM_OUT2 AE6 TP6
U80 TP7 TP8 TP9 TSEC_1588_PULSE_OUT1 AD8 TP10
1 5 2V5 TSEC_1588_PULSE_OUT2
A VCC 4
2 C 3 2V5_SLP 2V5_SLP T1040
20,21,22,23,24,25 EMI1_MDC B GND
74LVC1G66 R718 R142 R143 R144
2V5_SLP C1067 C1068
U81 1K 4.7K 4.7K 4.7K
1 5 0.1uF 0.1uF
A VCC 4
2 C 3
20,21,22,23,24,25 EMI1_MDIO B GND
74LVC1G66
U1B
SerDes
AH10 AD10
SD1_RX0_P 2 of 15 SD1_TX0_P
AG10 AE10
C56 0.1uF AH11 SD1_RX0_N SD1_TX0_N AD11
21 SGMII_RX_P SD1_RX1_P SD1_TX1_P SGMII_TX_P 21
C57 0.1uF AG11 AE11
21 SGMII_RX_N SD1_RX1_N SD1_TX1_N SGMII_TX_N 21
C58 0.1uF AH13 AD13
9 SD_RX2_P SD1_RX2_P SD1_TX2_P SD_TX2_P 9
C55 0.1uF AG13 AE13
9 SD_RX2_N SD1_RX2_N SD1_TX2_N SD_TX2_N 9
C C59 0.1uF AH14 AD14 C
9 SD_RX3_P SD1_RX3_P SD1_TX3_P SD_TX3_P 9
C60 0.1uF AG14 AE14
9 SD_RX3_N SD1_RX3_N SD1_TX3_N SD_TX3_N 9
AH16 AD16
9 SD_RX4_P SD1_RX4_P SD1_TX4_P SD_TX4_P 9
AG16 AE16
9 SD_RX4_N SD1_RX4_N SD1_TX4_N SD_TX4_N 9
AH17 AD17
27 MPEX1_RX_P SD1_RX5_P SD1_TX5_P MPEX1_TX_P 27
AG17 AE17
27 MPEX1_RX_N SD1_RX5_N SD1_TX5_N MPEX1_TX_N 27
AH19 AD19
27 MPEX2_RX_P SD1_RX6_P SD1_TX6_P MPEX2_TX_P 27
AG19 AE19
27 MPEX2_RX_N SD1_RX6_N SD1_TX6_N MPEX2_TX_N 27
AH20 AD20
27 SATA_RX_P SD1_RX7_P SD1_TX7_P SATA_TX_P 27
AG20 AE20
27 SATA_RX_N SD1_RX7_N SD1_TX7_N SATA_TX_N 27
AB14 AB18 C1054 0.1uF
31 SD_REFCLK1_P SD1_REF_CLK1_P SD1_REF_CLK2_P SD_REFCLK2_P 30
AA14 AA18 C1055 0.1uF
31 SD_REFCLK1_N SD1_REF_CLK1_N SD1_REF_CLK2_N SD_REFCLK2_N 30
TP11 Y15 Y20
TP12 AB15 SD1_PLL1_TPA SD1_IMP_CAL_TX AA12
SD1_PLL1_TPD SD1_IMP_CAL_RX
TP13 Y19
TP14 AB19 SD1_PLL2_TPA R145 R146
SD1_PLL2_TPD 1% 1%
SVDD 200 XVDD 698
T1040

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 8 of 38


1 2 3 4 5
1 2 3 4 5

SERDES and MDIO MUX/DEMUX SWITCHs

U16

3 19
A 8 SD_RX2_N A0+ B0+ QSGMII1_RX_N 24 A
4 18
8 SD_RX2_P A0- B0- QSGMII1_RX_P 24
15
C0+ SGMII1_RX_N 22
14
C0- SGMII1_RX_P 22
7 17
8 SD_TX2_N A1+ B1+ QSGMII1_TX_N 24
8 16
8 SD_TX2_P A1- B1- QSGMII1_TX_P 24
13
C1+ SGMII1_TX_N 22
R147 4.7K 12
C1- SGMII1_TX_P 22
9 2
29 QSG_SEL_N SEL PD
3V3 1 5
6 VDD GND 11
10 VDD GND 20
VDD GND 21
C61 C62 C63 EPAD

0.01uF 0.01uF 0.01uF PI3PCIE3212

U17
B B

3 19
8 SD_RX3_N A0+ B0+ QSGMII2_RX_N 25
4 18
8 SD_RX3_P A0- B0- QSGMII2_RX_P 25
15
C0+ SGMII2_RX_N 23
14
C0- SGMII2_RX_P 23
7 17
8 SD_TX3_N A1+ B1+ QSGMII2_TX_N 25
8 16
8 SD_TX3_P A1- B1- QSGMII2_TX_P 25
13
C1+ SGMII2_TX_N 23
12
C1- SGMII2_TX_P 23
9 2
SEL PD
3V3 1 5
6 VDD GND 11
10 VDD GND 20
VDD GND 21
C64 C65 C66 EPAD

0.01uF 0.01uF 0.01uF PI3PCIE3212

C C

U18

3 19
8 SD_RX4_N A0+ B0+ AURORA_RX_N 28
4 18
8 SD_RX4_P A0- B0- AURORA_RX_P 28
15
C0+ PEX_RX_N 27
14
C0- PEX_RX_P 27
7 17
8 SD_TX4_N A1+ B1+ AURORA_TX_N 28
8 16
8 SD_TX4_P A1- B1- AURORA_TX_P 28
13
C1+ PEX_TX_N 27
R148 4.7K 12
C1- PEX_TX_P 27
9 2
29 PEX_SEL SEL PD
3V3 1 5
6 VDD GND 11
10 VDD GND 20
VDD GND 21
C67 C68 C69 EPAD

D 0.01uF 0.01uF 0.01uF PI3PCIE3212 D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 9 of 38


1 2 3 4 5
1 2 3 4 5

T104X USB INTERFACE

3V3_SLP 3V3_SLP

R149 R150 3V3_SLP 3V3_SLP


A DNP DNP A
10K 10K
5V0_SLP U19
R151 0 R152 R153
1
INA

3
100K 100K 5
Q4 DNP INB
IRLML6346 USB1_PWREN 2 10 5V0_USB1
1 USB1_FLG_N 9 ONA OUTA
FLTA
USB2_PWREN 4 6 5V0_USB2
2 USB2_FLG_N 7 ONB OUTB
FLTB C73 C74 C75 C70 C71 C72
8 3 R154 D2 R158 D3
R155 0 R156 R157 11 GND ISET 100uF 10uF 1000pF 1% 100uF 10uF 1000pF 1%
EPAD 10V 51.1K CMHD3595 10V 51.1K CMHD3595
3

1K 1K
Q5 DNP MAX1558H
IRLML6346 R159
1 5V0_SLP 5V0_SLP 1%
26.7K R160 R161
1% 1%
2

C76 C77 18.2K 18.2K


B B
10uF 0.1uF

R162 0 USB1_VBUS
DNP J5
4 L1 3 USB1_DP 7 5 FB1
U1L BLM21PG121SN1
1 2 USB1_DM 6 5 6 7 8 8 FB2
USB INTERFACES 90ohm BLM21PG121SN1
F5 12 of 15 F6 R163 0 3 1 FB3
USB1_PWRFAULT USB1_DRVVBUS DNP BLM21PG121SN1
F1 R164 0 2 1 2 3 4 4 FB4
USB1_UDP F2 DNP BLM21PG121SN1
USB1_UDM 4 L2 3 USB2_DP USB_A_2

9
10
11
12
E4 USB1_VBUSCLMP
USB1_VBUSCLMP 1 2 USB2_DM USB2_VBUS
F4 90ohm
USB1_UID R165 0
DNP

C U20 5V0_SLP C
H5 J5
USB2_PWRFAULT USB2_DRVVBUS USB2_DP 1 6 USB1_DM
H1
USB2_UDP H2 2 5
G4 USB2_UDM
USB_IBIAS_REXT J4 USB2_VBUSCLMP USB2_DM 3 4 USB1_DP
USB2_VBUSCLMP
F8 H4
30 USB_REFCLK USBCLK USB2_UID VBUS054B-HSF
C78
DNP R166 T1040 R167 R168
0.1uF 1% 1% 1% USB1&2 FOR HOST MODE
10K 49.9 49.9

R169
1%
49.9
DNP

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 10 of 38


1 2 3 4 5
1 2 3 4 5

T104X QE-TDM/DIU MUX/DEMUX


DVI_D[0..11] 16
DFP_D[0..11] 17
U21 U22

U1N QED_D0 7 6 DVI_D0 QED_D8 7 6 DVI_D8


1A 1B1 5 DFP_D0 1A 1B1 5 DFP_D8
A MISC. QED_D0 1B2 1B2 A
U2 4 4
14 of 15 TDMA_RXD QED_D1 1B3 UC1_RXD 18 1B3 UC3_RTS_N 18
U1 1 3 1 3
TDMA_RSYNC 1OE 1B4 TDMA_RXD 15 1OE 1B4 TDMB_TSYNC 15
T1 QED_D2
TDMA_TXD R1 QED_D3 QED_D1 9 10 DVI_D1 QED_D9 9 10 DVI_D9
TDMA_TSYNC R2 QED_D4 2A 2B1 11 DFP_D1 2A 2B1 11 DFP_D9
TDMA_RQ 2B2 12 2B2 12
2B3 UC1_CTS_N 18 2B3 UC3_CDBRXER 18
U4 QED_D5 15 13 15 13
TDMB_RXD QED_D6 2OE 2B4 TDMA_RSYNC 15 2OE 2B4 TDMB_RQ 15
T3
TDMB_RSYNC T4 QED_D7 14 14
TDMB_TXD R3 QED_D8 2 S0 2 S0
TDMB_TSYNC R4 QED_D9 S1 S1
TDMB_RQ 3V3 16 8 3V3 16 8
P4 QED_D10 VCC GND VCC GND
CLK09 P3 QED_D11
CLK10 N4 QED_D12 74CBTLV3253 74CBTLV3253
CLK11 M4 R170 0 QED_D13
CLK12
U23 U24
T1040
QED_D2 7 6 DVI_D2 QED_D10 7 6 DVI_D10
1A 1B1 5 DFP_D2 1A 1B1 5 DFP_D10
1B2 4 1B2 4
1B3 UC1_TXD 18 1B3
1 3 1 3
1OE 1B4 TDMA_TXD 15 1OE 1B4 TDMA_TCK_CLK9 15
B B
QED_D3 9 10 DVI_D3 QED_D11 9 10 DVI_D11
2A 2B1 11 DFP_D3 2A 2B1 11 DFP_D11
2B2 12 2B2 12
2B3 UC1_RTS_N 18 2B3
15 13 15 13
2OE 2B4 TDMA_TSYNC 15 2OE 2B4 TDMB_RCK_CLK10 15
14 14
29 QE_MUX_CFG0 S0 S0
2 2
29 QE_MUX_CFG1 S1 S1
3V3 16 8 3V3 16 8
VCC GND VCC GND

74CBTLV3253 74CBTLV3253

U25 U26 U27

2 3 QED_D4 7 6 DVI_D4 QED_D12 7 6


7 DIU_HSYNC 1A 1Y DVI_HSYNC 16 1A 1B1 DFP_D4 1A 1B1 DVI_DE 16
1 5 5
1OE 1B2 1B2 DFP_DE 17
5 6 4 4
2A 2Y DFP_HSYNC 17 1B3 UC1_CDBRXER 18 1B3
4 1 3 1 3
2OE 1OE 1B4 TDMA_RQ 15 1OE 1B4 TDMB_TCK_CLK11 15
9 8
7 DIU_VSYNC 3A 3Y DVI_VSYNC 16 QED_D5 DVI_D5 QED_D13
10 9 10 9 10
3OE 2A 2B1 2A 2B1 DVI_DCLK 16
12 11 11 DFP_D5 11
4A 4Y DFP_VSYNC 17 2B2 2B2 DFP_DCLK 17
C 13 12 12 C
4OE 2B3 UC3_RXD 18 2B3
15 13 15 13
2OE 2B4 TDMB_RXD 15 2OE 2B4 TDMA_RCK_CLK8_12 15
3V3 14 7
VCC GND 14 14
2 S0 2 S0
74LVC125A S1 S1
3V3 16 8 3V3 16 8
VCC GND VCC GND
3V3
74CBTLV3253 74CBTLV3253

C79
U28
0.1uF 3V3 3V3 3V3 3V3 3V3 3V3 3V3
QED_D6 7 6 DVI_D6
1A 1B1 5 DFP_D6
1B2 4 C80 C81 C82 C83 C84 C85 C86
1B3 UC3_CTS_N 18
1 3
1OE 1B4 TDMB_RSYNC 15
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
QED_D7 9 10 DVI_D7
2A 2B1 11 DFP_D7
2B2 12
2B3 UC3_TXD 18
15 13
2OE 2B4 TDMB_TXD 15
D 14 D
2 S0
S1
3V3 16 8
VCC GND
Title
74CBTLV3253 T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 11 of 38


1 2 3 4 5
1 2 3 4 5

T104X POWER SUPPLY


USB_SVDD supply must ramp before or after the
1V2 U1G 1V8 1V2 VCORE U1H USB_HVDD and USB_OVDD supplies have ramped. VCORE_SLP
FB5
POWER #1 POWER #2
D27 J14 K15 K9 1V0_USB_SVDD
F27 G1VDD01 7 of 15 OVDD1 J15 K17 VDD01 8 of 15 USB_SVDD1 K10 BLM18PG121SN1
H27 G1VDD02 OVDD2 J16 C87 C88 C89 C90 C91 C92 C93 C94 C1066 C1065 K19 VDD02 USB_SVDD2 C95 C96 C1138 C97 C98
K21 G1VDD03 OVDD3 J17 L12 VDD03 J8
K27 G1VDD04 OVDD4 J18 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF L14 VDD04 USB_HVDD1 K8 0.1uF 0.1uF 3000pF 2.2uF 2.2uF
A L21 G1VDD05 OVDD5 J19 L16 VDD05 USB_HVDD2 A
M21 G1VDD06 OVDD6 L18 VDD06 3V3_SLP
M27 G1VDD07 J11 1V8_SLP L20 VDD07 J9 FB6
N21 G1VDD08 O1VDD1 J12 C99 C100 C101 C102 C103 C116 C117 C104 M9 VDD08 USB_OVDD1 J10 3V3_USB_HVDD
P21 G1VDD09 O1VDD2 J13 M13 VDD09 USB_OVDD2 BLM18PG121SN1
P27 G1VDD10 O1VDD3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF M15 VDD10 C105 C106 C107 C108 C118
R21 G1VDD11 M17 VDD11
T21 G1VDD12 M19 VDD12 0.1uF 0.1uF 3000pF 2.2uF 2.2uF
U21 G1VDD13 N12 VDD13
U27 G1VDD14 C109 C110 C111 C119 C112 C113 C114 C115 N14 VDD14 1V8_SLP
W27 G1VDD15 N16 VDD15 FB7
AA27 G1VDD16 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF N18 VDD16 1V8_USB_OVDD
AD27 G1VDD17 N20 VDD17 BLM18PG121SN1
AF27 G1VDD18 P9 VDD18 AB9 C120 C121 C122 C123 C124
2V5 G1VDD19 P11 VDD19 SENSEVDDC
V8 2V5 2V5_SLP 3V3 P13 VDD20 AB10 0.1uF 0.1uF 3000pF 2.2uF 2.2uF
W8 LVDD1 3V3 EVDD P15 VDD21 SENSEGNDC
LVDD2 P17 VDD22
N8 P19 VDD23 Though hole test points, route as differential signals
DVDD1 P8 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 R12 VDD24 TP15
DVDD2 VDD25 SENSEVDDC 32
R8 R14 G19 SENSEGNDC TP16
DVDD3 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R16 VDD26 SENSEVDD TP17
VDD27 SENSEVDD 32
M8 R18 G20 SENSEGND TP18
2V5_SLP CVDD1 EVDD R20 VDD28 SENSEGND
B VDD29 B
T8 T9 VCORE
U8 L1VDD1 L8 T13 VDD30
L1VDD2 EVDD1 LABEL = PROG_SFP 1V8_SLP 1V8 T15 VDD31
J6 T17 VDD32
F12 1V8_SFP T19 VDD33 C137 C138 C139 C140 C145 C141 C142 C143
PROG_SFP U14 VDD34
F11 C144 R171 JMP2 C146 C147 C148 C149 C150 C151 C152 U16 VDD35 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
PROG_MTR U18 VDD36
G18 0.1uF 330 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF U20 VDD37
FA_VL V9 VDD38
G9 J7 V13 VDD39 C153 C154 C155 C156
TH_VDD 1V8_MTR 1V8_SLP V15 VDD40
P6 V17 VDD41 22uF 22uF 22uF 22uF
(T2080 only)
VDD_LP VDD42
C161 R172 JMP2 V19
LABEL = PROG_MTR W14 VDD43
T1040 0.1uF 330 C162 C163 C164 C170 Y8 VDD44
VCORE Y9 VDD45 C165 C166 C167 C168 C169 C171 C172 C173
J8 10uF 0.1uF 0.1uF 0.1uF Y11 VDD46
SVDD U1I XVDD 1V0_FA_VL VDD47 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

W15 POWER #3: SerDes AC9 C174 R173 JMP2


S1VDD1 9 of 15 X1VDD1
W16 AC12 LABEL = FA_VDD
W17 S1VDD2 X1VDD2 AC15 0.1uF 330 VCORE_SLP C175 C176 C177 C178 C179 C180 C181 C182
W18 S1VDD3 X1VDD3 AC18 1V8
C C
W19 S1VDD4 X1VDD4 AC21 K11 T11 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
W20 S1VDD5 X1VDD5 K13 VDDC01 VDDC07 U10
Y13 S1VDD6 L10 VDDC02 VDDC08 U12
S1VDD7 C183 M11 VDDC03 VDDC09 V11
N10 VDDC04 VDDC10 W10 C184 C185 C186 C187 C188 C189 C190 C191
T1040 0.1uF R10 VDDC05 VDDC11 W12
VDDC06 VDDC12 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1V0S 1V35X
C192 C193 T1040

C194 C195 C196 C197 C198 C199 C200 C201


NFM21PC225B0J3 NFM21PC225B0J3
0.1uF 0.1uF 0.1uF 0.1uF 1500pF 1500pF 1500pF 1500pF

SVDD VCORE_SLP
C202 C203 C204 C205 C206 C207 C208

1500pF 1500pF 1500pF 1500pF 1500pF 1500pF 1500pF


C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221

2.2uF 2.2uF 3000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF 22uF 22uF 22uF

D D
XVDD
C226 C227 C228 C229 C230 C231 C232 C233 C234

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1500pF 1500pF


C237 C238 C239 C240 C241 C242 C243 C244 Title
T104XRDB
2.2uF 2.2uF 3000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 12 of 38


1 2 3 4 5
1 2 3 4 5

T104X PLL FILTERs and GROUND


U1J
DDR4 UDIMM VDD DECOUPLING
GROUNDS #1
A2 N15
GND001 10 of 15 GND086
A20 N17
A27 GND002 GND087 N19 1V2_SLP
B1 GND003 GND088 N22
B4 GND004 GND089 N26
B7 GND005 GND090 P7
A B10 GND006 GND091 P10 C246 C245 A
B13 GND007 GND092 P12
B16 GND008 GND093 P14 470uF 470uF
B19 GND009 GND094 P16 2.5V 2.5V
B23 GND010 GND095 P18
B25 GND011 GND096 P20
U1O B28 GND012 GND097 P24
C22 GND013 GND098 R7 1V2_SLP
NC/SPECIAL GND014 GND099
AG28 AH27 C26 R9
NC_DET15 of 15 DEV_DET D2 GND015 GND100 R11 C247 47uF
G17 (T2081 detect) D20 GND016 GND101 R13 C248 47uF
N6 NC01 D21 GND017 GND102 R15 C249 0.1uF
T6 NC02 D24 GND018 GND103 R17 C250 0.1uF
U6 NC03 E5 GND019 GND104 R19 C251 0.1uF
V6 NC04 G6 E7 GND020 GND105 R22 C252 0.1uF
W6 NC05 SPARE1 H6 E10 GND021 GND106 R26 C253 0.1uF
Y6 NC06 SPARE2 J6 E13 GND022 GND107 T2 C254 0.1uF
AA6 NC07 SPARE3 E16 GND023 GND108 T5 C255 0.1uF
AA7 NC08 E19 GND024 GND109 T7 C256 0.1uF
AA8 NC09 E22 GND025 GND110 T10 C257 0.1uF
AA9 NC10 F10 E26 GND026 GND111 T12 C258 0.1uF
AA10 NC11 TH_TPA F15 GND027 GND112 T14 C259 0.1uF
AB8 NC12 F24 GND028 GND113 T16 C260 0.1uF
AB11 NC13 G7 GND029 GND114 T18
B NC14 GND030 GND115 B
AB12 G13 T20
NC15 G16 GND031 GND116 T22
G22 GND032 GND117 T26
T1040 G26 GND033 GND118 U7
H7 GND034 GND119 U9
H8 GND035 GND120 U11 U1K
H9 GND036 GND121 U13
GND037 GND122 GROUNDS #2
H10 U15 Y14 E1
H11 GND038 GND123 U17 Y16 S1GND0111 of 15USB_AGND01 E2
H12 GND039 GND124 U19 Y17 S1GND02 USB_AGND02 E3
H13 GND040 GND125 U24 Y18 S1GND03 USB_AGND03 F3
H14 GND041 GND126 V7 AA13 S1GND04 USB_AGND04 G1
H15 GND042 GND127 V10 AA15 S1GND05 USB_AGND05 G2
H16 GND043 GND128 V12 AA17 S1GND06 USB_AGND06 G3
H17 GND044 GND129 V14 AA19 S1GND07 USB_AGND07 G5
H18 GND045 GND130 V16 AA21 S1GND08 USB_AGND08 H3
H19 GND046 GND131 V18 AB13 S1GND09 USB_AGND09 J1
H20 GND047 GND132 V20 AB17 S1GND10 USB_AGND10 J2
H24 GND048 GND133 V22 AB21 S1GND11 USB_AGND11 J3
J7 GND049 GND134 V26 AF10 S1GND12 USB_AGND12
J22 GND050 GND135 W2 AF11 S1GND13
J26 GND051 GND136 W5 AF12 S1GND14
K2 GND052 GND137 W7 AF13 S1GND15 AC10
U1M K5 GND053 GND138 W9 AF14 S1GND16 X1GND01 AC11
C C
1V8 1V35X K6 GND054 GND139 W11 AF15 S1GND17 X1GND02 AC13
PLL FILTERS GND055 GND140 S1GND18 X1GND03
K7 W13 AF16 AC14
AVDD_CGA1 13 of 15 AVDD_SD1_PLL1 GND056 GND141 S1GND19 X1GND04
R174 5.1 G11 AB16 R175 0.33 K12 W24 AF17 AC16
AVDD_CGA1 AVDD_SD1_PLL1 1% K14 GND057 GND142 Y7 AF18 S1GND20 X1GND05 AC17
C261 C262 C263 C264 C265 K16 GND058 GND143 Y10 AF19 S1GND21 X1GND06 AC19
K18 GND059 GND144 Y12 AF20 S1GND22 X1GND07 AC20
10uF 1uF 3000pF 4.7uF 47uF K20 GND060 GND145 Y22 AG9 S1GND23 X1GND08 AD9
AA16 AGND_SD1_PLL1 R176 0 K24 GND061 GND146 Y26 AG12 S1GND24 X1GND09 AD12
AGND_SD1_PLL1 L7 GND062 GND147 AA11 AG15 S1GND25 X1GND10 AD15
R177 5.1 AVDD_CGA2 G12 AB20 AVDD_SD1_PLL2 R178 0.33 L9 GND063 GND148 AA24 AG18 S1GND26 X1GND11 AD18
AVDD_CGA2 AVDD_SD1_PLL2 1% L11 GND064 GND149 AB2 AG21 S1GND27 X1GND12 AD21
C266 C267 C268 C269 C270 L13 GND065 GND150 AB5 AH9 S1GND28 X1GND13 AE9
L15 GND066 GND151 AB7 AH12 S1GND29 X1GND14 AE12
10uF 1uF 3000pF 4.7uF 47uF L17 GND067 GND152 AB22 AH15 S1GND30 X1GND15 AE15
1V8_SLP AA20 AGND_SD1_PLL2 R179 0 L19 GND068 GND153 AB26 AH18 S1GND31 X1GND16 AE18
AGND_SD1_PLL2 L22 GND069 GND154 AC24 AH21 S1GND32 X1GND17 AE21
R180 5.1 AVDD_PLAT G10 L26 GND070 GND155 AC26 S1GND33 X1GND18
AVDD_PLAT M7 GND071 GND156 AD4
C271 C272 M10 GND072 GND157 AD6 T1040
M12 GND073 GND158 AD22
10uF 1uF M14 GND074 GND159 AE2
M16 GND075 GND160 AE24
M18 GND076 GND161 AE26
D R181 5.1 AVDD_DDR1 E20 M20 GND077 GND162 AF9 D
AVDD_D1 M24 GND078 GND163 AF21
C273 C274 N2 GND079 GND164 AG1
T1040 N5 GND080 GND165 AG4
10uF 1uF N7 GND081 GND166 AG6
N9 GND082 GND167 AG22 Title
N11 GND083 GND168 AG23 T104XRDB
N13 GND084 GND169 AG26
GND085 GND170 AH2 Size Document Number Design Engineer Rev
GND171 B <Doc> MICETEK A

T1040 Date: Monday, December 22, 2014 Sheet 13 of 38


1 2 3 4 5
1 2 3 4 5

T104X DUART and I2C DEVICE INTERFACE


U29 3V3

C275 0.1uF 1 16 C276 0.1uF


C1+ VCC
3 2 C277 0.1uF
C1- V+
A
RS-232 XCVR A
C278 0.1uF 4 6 C279 0.1uF
C2+ V-

10
5 15
C2- GND 5
9
11 14 R182 100 FB8 RS232_TXD1 4
7 UART1_TXD T1-IN T1-OUT BLM18BD601SN1 8 J9A
12 13 R183 100 FB9 RS232_RXD1 3 2XDB9
7 UART1_RXD R1-OUT R1-IN BLM18BD601SN1 7 TOP
2
10 7 R184 100 FB10 RS232_RTS1 6
7 UART1_RTS_N T2-IN T2-OUT BLM18BD601SN1 1
9 8 R185 100 FB11 RS232_CTS1
7 UART1_CTS_N R2-OUT R2-IN BLM18BD601SN1

22
C280 C281 C282 C283
MAX3232
100pF 100pF 100pF 100pF

U30 3V3

C284 0.1uF 1 16 C285 0.1uF


B C1+ VCC B

3 2 C287 0.1uF
C1- V+
RS-232 XCVR
C286 0.1uF 4 6 C288 0.1uF
C2+ V-

20
5 15
C2- GND 15
19
11 14 R186 100 FB12 RS232_TXD2 14
7 UART2_TXD T1-IN T1-OUT BLM18BD601SN1 18 J9B
12 13 R187 100 FB13 RS232_RXD2 13 2XDB9
7 UART2_RXD R1-OUT R1-IN BOTTOM
BLM18BD601SN1 17
12
10 7 R188 100 FB14 RS232_RTS2 16
7 UART2_RTS_N T2-IN T2-OUT BLM18BD601SN1 11
9 8 R189 100 FB15 RS232_CTS2
7 UART2_CTS_N R2-OUT R2-IN BLM18BD601SN1

21
C289 C290 C291 C292
MAX3232
RTC I2C EEPROM 100pF 100pF 100pF 100pF

C I2C ADR = 0x68 3V3_SLP I2C ADDR = 0x50 C


For RS232 ESD protection, place close to connector

U31 3V3_SLP 3V3 U32 U33 DNP


R190 RS232_CTS2 1 16
6 8 6 7 3V3
3,7,14,31,32 I2C1_SCL_SLP SCL VCC 7,16,17 I2C1_SCL SCL WP
5 3 4.7K 5 RS232_CTS1 2 15
3,7,14,31,32 I2C1_SDA_SLP SDA VBACKUP 7,16,17 I2C1_SDA SDA 1
7 8 A0 2 C293 RS232_TXD1 3 14
SQWINT RTC_INT_N 7 VCC A1
1 4 3
2 X1 4 GND A2 0.1uF RS232_RTS1 4 13
Y1 X2 GND R191
AT24C256 RS232_RXD1 5 12
1 4 DS1339U-33+ 1K J10
RS232_TXD2 6 11
3V3_SLP 1 2 I2C THERMAL MONITOR
32.768KHz RS232_RTS2 7 10
2

C294
C295 3V3_SLP 3V3_SLP RS232_RXD2 8 9
10uF BAT_SOCKET I2C ADDR = 0x4C
0.1uF LCDA15C-8
C296
U34 3V3_SLP R192 R195
1000pF
D R193 100 2 1 4.7K 4.7K D
7 TEMP_DIODE_P D+ VDD
R194 100 3
7 TEMP_DIODE_N D- 4
THERM THERM_FAULT_N 29
6
ALERT/THERM2 THERM_ALERT_N 29
8
3,7,14,31,32 I2C1_SCL_SLP SCLK
7 5 C297 Title
3,7,14,31,32 I2C1_SDA_SLP SDATA GND T104XRDB
0.1uF
ADT7461 Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 14 of 38


1 2 3 4 5
1 2 3 4 5

TDM RISER INTERFACE

A A

3V3

R196 4.7K
R197 4.7K TDM RISER CARD CONNECTOR
R198 4.7K
R199 4.7K
12V
J11
11 TDMB_RXD 1 2
11 TDMA_RQ 3 4 3V3
5 6
11 TDMA_TXD 7 8
11 TDMA_TSYNC 9 10
11 TDMA_RSYNC 11 12
11 TDMA_RXD 13 14 T104X DVDD: 3.3V
15 16
11 TDMA_TCK_CLK9 17 18 TDMB_RSYNC 11
19 20 TDMB_TXD 11
B 11 TDMA_RCK_CLK8_12 21 22 TDMB_TSYNC 11 B
23 24 TDMB_RQ 11
29 TDMR_SLP_N 25 26 R200 51
29 TDMR_PRS_N 27 28 SPI_CLK 6
11 TDMB_RCK_CLK10 29 30
29 TDMR1_INT_N 31 32 TDMR_SPI_CS0_N 6
29 TDMR2_INT_N 33 34 TDMR_SPI_CS1_N 6
R201 33
18,29 TDMR_RST_N 35 36 SPI_MISO 6
R202 51
37 38 SPI_MOSI 6
11 TDMB_TCK_CLK11 39 40
CONN_2X20

12V

C298 C299

10uF 0.1uF

C C

3V3

C300 C301 C302 C303

10uF 0.1uF 0.1uF 0.1uF

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 15 of 38


1 2 3 4 5
1 2 3 4 5

HDMI DISPLAY INTERFACE

A A
FB46
I2C ADDR = 0x75
BLM18PG121SN1
R203 4.7K
U35 3V3 3V3 5V0 U36 R204 4.7K
11 DVI_D[0..11] DVI_D0 DVI_TDC0_P 5V0_HDMI
63 22 1 38
DVI_D1 62 D0 TDC0+ 21 DVI_TDC0_N 2 5V_SUPPLY 5V_OUT 37 C304 0.1uF J12
D1 TDC0- LV_SUPPLY ESD_BYP

49.9K
49.9K
49.9K
49.9K
DVI_D2 61 3 36
DVI_D3 60 D2 25 DVI_TDC1_P DVI_TDC2_P 4 GND GND 35 D2_P 1
DVI_D4 59 D3 TDC1+ 24 DVI_TDC1_N 5 TMDS_D2+ TMDSO_D2+ 34 2 D2+
DVI_D5 58 D4 TDC1- DVI_TDC2_N 6 TMDS_GND TMDS_GND 33 D2_N 3 D2 Shield
DVI_D6 55 D5 28 DVI_TDC2_P DVI_TDC1_P 7 TMDS_D2- TMDSO_D2- 32 D1_P 4 D2-
DVI_D7 54 D6 TDC2+ 27 DVI_TDC2_N 8 TMDS_D1+ TMDSO_D1+ 31 5 D1+
D7 TDC2- TMDS_GND TMDS_GND D1 Shield

R206
R207
R205
R208
DVI_D8 53 DVI_TDC1_N 9 30 D1_N 6
DVI_D9 52 D8 30 DVI_TLC_P DVI_TDC0_P 10 TMDS_D1- TMDSO_D1- 29 D0_P 7 D1-
DVI_D10 51 D9 TLC+ 31 DVI_TLC_N 11 TMDS_D0+ TMDSO_D0+ 28 8 D0+
DVI_D11 50 D10 TLC- DVI_TDC0_N 12 TMDS_GND TMDS_GND 27 D0_N 9 D0 Shield
R209 49.9K D11 8 R210 0 DVI_TLC_P 13 TMDS_D0- TMDSO_D0- 26 CK_P 10 D0-
2 GPIO0 9 DNP 14 TMDS_CK+ TMDSO_CK+ 25 11 CK+
11 DVI_DE DE HPDET TMDS_GND TMDS_GND CK Shield
4 DVI_TLC_N 15 24 CK_N 12
11 DVI_HSYNC H TMDS_CK- TMDSO_CK- CK-
5 38 16 23 13
11 DVI_VSYNC V R CE_REMOTE_IN CE_REMOTE_OUT CE Remote
R211 49.9K 37 17 22 14
B G DDC_CLK_IN DDC_CLK_OUT NC B
15 39 18 21 15
7,14,17 I2C1_SCL SPC B DDC_DAT_IN DDC_DAT_OUT DDC CLK
14 19 20 16
7,14,17 I2C1_SDA SPD HOTPLUG_DET_IN HOTPLUG_DET_OUT DDC DATA
48 17
13 HSYNC 47 18 GND
29 DVI_RST_N RESET VSYNC +5V
7 CM2020 19
29 DVI_INT_N GPIO1/HPINT HP DET
35 R212 140 1%
57 ISET 19 R213 2.37K 1% 20 22
11 DVI_DCLK XCLK+ VSWING MH1 MH3
56 3V3 5V0 R215 C305 21 23
3V3 XCLK- I2C2_HDMI_SDA 7 MH2 MH4
R214 1K 16
NC1 I2C2_HDMI_SCL 7
R216 R217 R218 1K 3 41 15K 0.1uF
C306 0.1uF VREF NC2 42 C307 C308 HDMI_A
3V3 4.7K 4.7K R219 0 10 NC3 43 LABEL = DVI SEL
DNP AS NC4 44 D4 0.1uF 0.1uF
36 NC5 46 R220 330 2 1
TEST NC6
3V3 1 6 GRN
12 DVDD DGND 11
49 DVDD DGND 64 R768 0
45 DVDD DGND DNP
C309 C310 C311 DVDDV DVI_TDC2_P 4 L19 3 D2_P
23 20
0.1uF 0.1uF 0.1uF 29 TVDD TGND 26 DVI_TDC2_N 1 2 D2_N
TVDD TGND 32 90ohm
3V3 TGND R769 0
C C
33 34 DNP
VDD GND 40 R770 0
GND DNP
C312 C313 C314 18 17 DVI_TDC1_P 4 L20 3 D1_P
AVDD AGND
0.1uF 0.1uF 0.1uF DVI_TDC1_N 1 2 D1_N
CH7301C 90ohm
3V3 R771 0
FB16 DNP
3V3_DVI_VDD R772 0
BLM18PG121SN1 DNP
C315 DVI_TDC0_P 4 L21 3 D0_P

0.1uF DVI_TDC0_N 1 2 D0_N


90ohm
3V3 R773 0
FB17 DNP
3V3_DVI_AVDD R774 0
BLM18PG121SN1 DNP
C316 DVI_TLC_P 4 L22 3 CK_P

0.1uF DVI_TLC_N 1 2 CK_N


90ohm
D R775 0 D
DNP

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 16 of 38


1 2 3 4 5
1 2 3 4 5

LVDS PANEL INTERFACE


I2C ADDR = 0x38

U37
11 DFP_D[0..11] DFP_D0 LVDS0_P
94 49
DFP_D1 93 D0 A0P 50 LVDS0_N 3V3
A DFP_D2 92 D1 A0M A
DFP_D3 91 D2 46 LVDS1_P
DFP_D4 90 D3 A1P 47 LVDS1_N
DFP_D5 89 D4 A1M C317 C318 C319
DFP_D6 86 D5 44 LVDS2_P J13
DFP_D7 85 D6 A2P 45 LVDS2_N 10uF 0.1uF 0.1uF 1
DFP_D8 84 D7 A2M 100 ohms 2
DFP_D9 83 D8 38 LVDS3_P DIFF PAIRs 3
DFP_D10 82 D9 A3P 39 LVDS3_N 4
DFP_D11 81 D10 A3M 5 M1
D11 6
8 36 7
7 D12 A4P 37 8
6 D13 A4M 9
5 D14 33 10
4 D15 A5P 34 11
3V3 3V3 3 D16 A5M 12
2 D17 31 13
1 D18 A6P 32 14
100 D19 A6M 15
R221 R222 99 D20 28 16 LQ150X1LW71N
98 D21 A7P 29 17
4.7K 4.7K 97 D22 A7M 18
R223 49.9K D23 19
B B
76 41 LVDS_CLK_P 3V3 20
11 DFP_DE DE CLK1P
75 42 LVDS_CLK_N
11 DFP_HSYNC HSYNC CLK1M
74 LABEL = FLIP R224 4.7K DF14-20P-1.25H
11 DFP_VSYNC

21
22
R225 49.9K VSYNC J14
87 26 1
11 DFP_DCLK CLKIN_P CLK2P
3V3 R226 0 DNP 88 27 2
CLKIN_N CLK2M
22 20 HDR_1X2
29 DFP_RST_N PD RSVD1 54 LABEL = PNLFMT 3V3
21 RSVD2 55 J15
29 DFP_INT_N MSEN RSVD3 56 1 R227 4.7K
59 RSVD4 57 2
7,14,16 I2C1_SCL I2CCLK/DDREN RSVD5
60 58
7,14,16 I2C1_SDA I2CDAT/DSEL RSVD6
3V3 61 62 HDR_1X2
I2CSEL RSVD7

3
66
63 RSVD8 67 3V3
64 A0 RSVD9 Q6
3V3 65 A1 72 1 IRLML6346
A2 TST1 29 DFP_MODE
73
No pre-emphasis R228 49.9K DNP 12 TST2

2
13 PRE
DCLK Falling-Edge R229 4.7K 18 PLLSEL
DE Active-High R230 4.7K 19 R_FB
Since 12b input R231 4.7K DNP 23 R_FDE
C C
Unbalanced LVDS Outputs R232 4.7K DNP 24 DUAL
BAL
78 LABEL = BACKLIGHT
3V3 VREF 12V R233 0 J16
FB18 10 14 1
3V3_DFP_PLLVCC 16 PLLVCC PLLGND 15 F1 1A 2
BLM18PG121SN1 PLLVCC PLLGND 17 DNP 3
C320 C321 PLLGND C322 C323 C324
30 25 CON_3PIN
0.1uF 0.1uF 40 LVDSVCC LVDSGND 35 10uF 0.1uF 0.1uF
3V3 48 LVDSVCC LVDSGND 43
LVDSVCC LVDSGND 51 LABEL = BACKCTL
LVDSGND J17
70 71 1
VCC3V GND3V 29 DFP_BACKLIGHT
C325 C326 C327 C328 79 80 2
95 VCC3V GND3V 96 3
VCC3V GND3V 29 DFP_BL_PWM
0.1uF 0.1uF 0.1uF 0.1uF
53 9 CON_3PIN
VCC GND 11 R234 R235
68 GND 52
I2CVCC GND 77 4.7K 4.7K
C329 C330 C331 GND 69
SGND
D 0.1uF 0.1uF 0.1uF D
DS90C387R

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 17 of 38


1 2 3 4 5
1 2 3 4 5

PROFIBUS INTERFACE

5V0
A A
R236 0
VCC_PROFI
U38 L3
2 4 PROFI_PWR_OUT
C332 +VIN +VOUT 10uH
1 3 LOW ESR
10uF -VIN -VOUT Place Close to C333 R237
NKE0505SC MEV1S0505DC
11 UC1_CDBRXER
10uF 270K
11 UC3_CDBRXER
R238 0

R239 R240
GND_PROFI
4.7K 4.7K GND_PROFI

3V3

VCC_PROFI
B B

R241 J18
JMP2 VCC_PROFI
U39 4.7K 3V3 U40 VCC_PROFI R242
DNP
2 4 1 16 0
11 UC1_RXD

1
2
3 1B1 1A VCC1 VCC2 J42
11 UC3_RXD 1B2 3 R243 100 1
5 7 R 2
11 UC1_TXD 2B1 2A ISO_RXD_TXD_N
6 4 13 3
11 UC3_TXD 2B2 RE B 4
11 9 12 ISO_RXD_TXD_P 5
11 UC1_CTS_N 3B1 3A A
10 6
11 UC3_CTS_N 3B2 D ISO_DE
10 HDR_1X5
14 12 7 ISODE
11 UC1_RTS_N 4B1 4A PV
13 11 C334
11 UC3_RTS_N 4B2 NC1
5 14
15 1 DE NC2 0.1uF R244
OE S 2 9 DNP GND_PROFI
8 16 3V3 R245 8 GND1_1 GND2_1 15 0
GND VCC GND1_2 GND2_2
4.7K
74CBTLV3257 ISO1176DW
C GND_PROFI GND_PROFI C
29 PROFI_MUX_CFG
15,29 TDMR_RST_N

3V3 3V3 3V3

C336 C337
R246
0.1uF 3V3 DNP 0.1uF
U41 4.7K
1 5
NC VCC 4
2 O 3
I GND
74LVC1G14

3V3

C338

0.1uF
D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 18 of 38


1 2 3 4 5
1 2 3 4 5

RGMII ETHERNET PORT 1

T1

EC1_MDI0_P 12 13 EC1_MDX0_P
A A
C339 0.01uF 10 15 R247 75

EC1_MDI0_N 11 14 EC1_MDX0_N

EC1_MDI1_P 9 16 EC1_MDX1_P
100 ohms
U42 DIFF PAIRs C341 0.01uF 7 18 R248 75 J19B
B1 B9
22 EC1_MDI1_N 8 17 EC1_MDX1_N B2
8 EC1_GTXCLK TXC B3 B10
8 EC1_TXD[0..3] EC1_TXD0 EC1_MDI2_P EC1_MDX2_P
23 1 6 19 B4
EC1_TXD1 24 TXD0 MDI+[0] 2 B5
EC1_TXD2 25 TXD1 MDI-[0] C342 0.01uF 4 21 R249 75 B6 B11
EC1_TXD3 26 TXD2 4 B7
27 TXD3 MDI+[1] 5 EC1_MDI2_N 5 20 EC1_MDX2_N B8 B12
8 EC1_TXCTL TXCTL MDI-[1]
R250 33 19 7 EC1_MDI3_P 3 22 EC1_MDX3_P RJ45_LED_2X1
8 EC1_RXCLK

27
28
C343 10pF DNP RXC MDI+[2] 8
8 EC1_RXD[0..3] EC1_RXD0 MDI-[2]
R251 33 14 C344 0.01uF 1 24 R252 75
EC1_RXD1 R253 33 16 RXD0/SELRGV 10
EC1_RXD2 R254 33 17 RXD1/TXDLY MDI+[3] 11 EC1_MDI3_N 2 23 EC1_MDX3_N
EC1_RXD3 R255 33 18 RXD2/AN0 MDI-[3]
R256 33 13 RXD3/AN1 C345
B 8 EC1_RXCTL RXCTL/PHY_AD2 B
H5008 1000pF
30 34 EC1_LED0 2KV
8 EMI1_MDC_SLP MDC LED0/PHY_AD0
31 35 EC1_LED1
8 EMI1_MDIO_SLP MDIO LED1/PHY_AD1 32 EC1_RXDLY
LED2/RXDLY
29 EC1_RST_N
42 46 R258 33
CKXTAL1 CLK125 EC1_REFCLK 8
43 C346 10pF R259 510
Y2 CKXTAL2 DNP R260 510
29 20 R262 0
PHYRST INT EC1_INT_N 7
1 3 C348 C349
R263 0 38 33 R264 0 C347 1000pF
ENSWREG PME EC1_PME_N 7
C350 C351 R265 2KV 470pF 470pF
25MHz 39 12 R266 15 C352 1000pF C353 1000pF
2

4.7pF 4.7pF 4.7K RSET NC DNP DNP 2KV


44 48 L4
45 VDDREG REG_OUT 2.2uH
2V5_SLP VDDREG C354 C355
15 28 R267
21 DVDD33 DVDD10 36 4.7uF 0.1uF
37 DVDD33 DVDD10 0
C356 C357 DVDD33 3
6 AVDD10 9 1V05_EC1_DVDD
0.1uF 0.1uF 41 AVDD33 AVDD10 40
3V3_SLP AVDD33 AVDD10 C358 C359
C C
47 49
GND EPAD 0.1uF 0.1uF

C360 C361 RTL8211E-VB


R268 1V05_EC1_AVDD
0.1uF 0.1uF 1%
2.49K C362 C363 C364

0.1uF 0.1uF 0.1uF

3V3_SLP

C365 C366 C367

4.7uF 0.1uF 0.1uF

RGMII PHY POWER-ON STRAPPINGs

2V5_SLP 3V3_SLP

EC1_RXD0 R269 4.7K SELRGV 2.5V


D EC1_RXD1 R270 4.7K TXDLY D
EC1_RXD2 R271 4.7K AN0 NWay, advertize all capability
EC1_RXD3 R272 4.7K AN1
EC1_RXCTL R273 4.7K PHY_AD2
EC1_LED0 R274 4.7K PHY_AD0 PHY ADDR = 0x04
EC1_LED1 R275 4.7K PHY_AD1 Title
EC1_RXDLY R276 4.7K RXDLY T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 19 of 38


1 2 3 4 5
1 2 3 4 5

RGMII ETHERNET PORT 2

T2 3V3
FB20
EC2_MDI0_P 12 13 EC2_MDX0_P
A BLM18BD601SN1 A
C368 0.01uF 10 15 R277 75 C369

EC2_MDI0_N 11 14 EC2_MDX0_N 0.1uF

EC2_MDI1_P 9 16 EC2_MDX1_P
100 ohms

25
26
U45 DIFF PAIRs C370 0.01uF 7 18 R278 75 J19A
A1 A9
22 EC2_MDI1_N 8 17 EC2_MDX1_N A2
8 EC2_GTXCLK TXC A3 A10
8 EC2_TXD[0..3] EC2_TXD0 EC2_MDI2_P EC2_MDX2_P
23 1 6 19 A4
EC2_TXD1 24 TXD0 MDI+[0] 2 A5
EC2_TXD2 25 TXD1 MDI-[0] C371 0.01uF 4 21 R279 75 A6 A11
EC2_TXD3 26 TXD2 4 A7
27 TXD3 MDI+[1] 5 EC2_MDI2_N 5 20 EC2_MDX2_N A8 A12
8 EC2_TXCTL TXCTL MDI-[1]
R281 33 19 7 EC2_MDI3_P 3 22 EC2_MDX3_P RJ45_LED_2X1
8 EC2_RXCLK RXC MDI+[2]
C372 10pF DNP 8
8 EC2_RXD[0..3] EC2_RXD0 MDI-[2]
R280 33 14 C373 0.01uF 1 24 R282 75
EC2_RXD1 R283 33 16 RXD0/SELRGV 10
EC2_RXD2 R284 33 17 RXD1/TXDLY MDI+[3] 11 EC2_MDI3_N 2 23 EC2_MDX3_N
EC2_RXD3 R285 33 18 RXD2/AN0 MDI-[3]
R286 33 13 RXD3/AN1 C374
B 8 EC2_RXCTL RXCTL/PHY_AD2 B
H5008 1000pF
30 34 EC2_LED0 2KV
8,21,22,23,24,25 EMI1_MDC MDC LED0/PHY_AD0
31 35 EC2_LED1
8,21,22,23,24,25 EMI1_MDIO MDIO LED1/PHY_AD1 32 EC2_RXDLY
LED2/RXDLY
29 EC2_RST_N
42 46 R288 33
CKXTAL1 CLK125 EC2_REFCLK 8
43 C375 10pF R289 510
Y3 CKXTAL2 DNP R290 510
29 20 R292 0
PHYRST INT EC2_INT_N 7
1 3 C377 C378
R293 0 38 33 R294 0 C376 1000pF
ENSWREG PME EC2_PME_N 7
C379 C380 R295 2KV 470pF 470pF
25MHz 39 12 R296 15 C381 1000pF C382 1000pF
2

4.7pF 4.7pF 4.7K RSET NC DNP DNP 2KV


44 48 L5
45 VDDREG REG_OUT 2.2uH
2V5 VDDREG C383 C384
15 28 R297
21 DVDD33 DVDD10 36 4.7uF 0.1uF
37 DVDD33 DVDD10 0
C385 C386 DVDD33 3
6 AVDD10 9 1V05_EC2_DVDD
0.1uF 0.1uF 41 AVDD33 AVDD10 40
3V3 AVDD33 AVDD10 C388 C387
C C
47 49
GND EPAD 0.1uF 0.1uF

C389 C390 RTL8211E-VL


R298 1V05_EC2_AVDD
0.1uF 0.1uF 1%
2.49K C391 C392 C393

0.1uF 0.1uF 0.1uF

3V3

C394 C395 C396

4.7uF 0.1uF 0.1uF

RGMII PHY POWER-ON STRAPPINGs

2V5 3V3

EC2_RXD0 R299 4.7K SELRGV 2.5V


D EC2_RXD1 R300 4.7K TXDLY D
EC2_RXD2 R301 4.7K AN0 NWay, advertize all capability
EC2_RXD3 R302 4.7K AN1
EC2_RXCTL R303 4.7K PHY_AD2
EC2_LED0 R304 4.7K PHY_AD0 PHY ADDR = 0x05
EC2_LED1 R305 4.7K PHY_AD1 Title
EC2_RXDLY R306 4.7K RXDLY T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 20 of 38


1 2 3 4 5
1 2 3 4 5

SGMII ETHERNET PORT


U48

48
GTX_CLK 17
HSOP SGMII_RX_P 8
50 18 100 ohms DIFF PAIR
TXD0 HSON SGMII_RX_N 8
53
A 54 TXD1 22 T3 3V3 A
55 TXD2 HSOP_CK 21 100 ohms FB21
57 TXD3 HSON_CK DIFF PAIRs SG_MDI0_P 12 13 SG_MDX0_P
58 TXD4 BLM18BD601SN1
59 TXD5 C397 0.01uF 10 15 R307 75 C398
60 TXD6 1
49 TXD7 MDIP0 2 SG_MDI0_N 11 14 SG_MDX0_N 0.1uF
61 TXEN/TXCTL MDIN0
TXER 4 SG_MDI1_P 9 16 SG_MDX1_P
56 MDIP1 5

13
TXCLK MDIN1 C399 0.01uF 7 18 R308 75 J20
38 7 1 9
RXC MDIP2 8 SG_MDI1_N 8 17 SG_MDX1_N 2
33 MDIN2 3 10
35 RXD0 10 SG_MDI2_P 6 19 SG_MDX2_P 4
36 RXD1 MDIP3 11 5
2V5 37 RXD2 MDIN3 C400 0.01uF 4 21 R309 75 6 11
2.5V GMII/RGMII R310 4.7K 39 RXD3 7
41 RXD4/SELRGV SG_MDI2_N 5 20 SG_MDX2_N 8 12
42 RXD5/TXDLY 13
R311 4.7K 43 RXD6/RXDLY HSIP 14 SG_MDI3_P 3 22 SG_MDX3_P RJ45_LED

14
NWay, advertize all capability 32 RXD7/AN0 HSIN
R312 4.7K 44 RXDV/RXCTL C401 0.01uF 1 24 R313 75
RXER/AN1
B B
SGMII to Coper R314 4.7K 46 SG_MDI3_N 2 23 SG_MDX3_N
R315 4.7K 45 CRS/MII1
COL/MII0 C402
72 68 H5008 1000pF
8,20,22,23,24,25 EMI1_MDC MDC LED0/PHY_AD0
73 69 C403 0.1uF 2KV
8,20,22,23,24,25 EMI1_MDIO MDIO LED1/PHY_AD1 SGMII_TX_P 8
70 C404 0.1uF 100 ohms DIFF PAIR
LED2/MDI0 SGMII_TX_N 8
71
LED3/MDI1 3V3
65 64
62 TDI TDO SG_LED0 R316 510
63 TMS SG_LED1 R317 510
TCK R318 4.7K R321 4.7K
29 SG_RST_N
81 86 R320 4.7K R319 4.7K C406 C407
82 CKXTAL1 CLK125 PHY ADDR = 0x01 C405 1000pF
CKXTAL2 SGMII to Coper 2KV 470pF 470pF
Y4 52 75 R323 0 C408 1000pF
PHYRST INT SG_INT_N 7
2KV
1 3 R324 0 77 74
R325 ENSWREG PME
C409 C410 78 28
25MHz 4.7K RSET NC1 29
2

4.7pF 4.7pF 26 NC2 30


REXT NC3 31
NC4 76 R326 15 C411 1000pF
C C
NC5 DNP DNP
84 88 L6
R327 R328 85 VDDREG REG_OUT 4.7uH
1% 1% 2V5 VDDREG 47 C412 C413
2.49K 12.1K DVDD10 66 R329
34 DVDD10 22uF 0.1uF
40 DVDD33 24 0
51 DVDD33 REGV15
3V3 67 DVDD33 3 1V05_SG_DVDD
DVDD33 AVDD10 9
6 AVDD10 12 C414 C415
25 AVDD33 AVDD10 16
C416 C417 C418 80 AVDD33 AVDD10 23 0.1uF 0.1uF
AVDD33 AVDD10 79
0.1uF 0.1uF 0.1uF 15 AVDD10
19 AGND 83 1V05_SG_AVDD
20 AGND GND 87
27 AGND GND 89 C419 C420 C421 C422 C423 C424
AGND EPAD
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RTL8211DN

D 3V3 2V5 D

C425 C426 C427 C428 C429 C430


Title
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 21 of 38


1 2 3 4 5
1 2 3 4 5

SGMII ETHERNET PORT 1


U82

48
GTX_CLK 17
HSOP SGMII1_RX_P 9
50 18 100 ohms DIFF PAIR
TXD0 HSON SGMII1_RX_N 9
53
A 54 TXD1 22 T12 3V3 A
55 TXD2 HSOP_CK 21 100 ohms FB44
57 TXD3 HSON_CK DIFF PAIRs SG1_MDI0_P 12 13 SG1_MDX0_P
58 TXD4 BLM18BD601SN1
59 TXD5 C1070 0.01uF 10 15 R724 75 C1071
60 TXD6 1
49 TXD7 MDIP0 2 SG1_MDI0_N 11 14 SG1_MDX0_N 0.1uF
61 TXEN/TXCTL MDIN0
TXER 4 SG1_MDI1_P 9 16 SG1_MDX1_P
56 MDIP1 5

13
TXCLK MDIN1 C1072 0.01uF 7 18 R725 75 J40
38 7 1 9
RXC MDIP2 8 SG1_MDI1_N 8 17 SG1_MDX1_N 2
33 MDIN2 3 10
35 RXD0 10 SG1_MDI2_P 6 19 SG1_MDX2_P 4
36 RXD1 MDIP3 11 5
2V5 37 RXD2 MDIN3 C1073 0.01uF 4 21 R726 75 6 11
2.5V GMII/RGMII R727 4.7K 39 RXD3 7
41 RXD4/SELRGV SG1_MDI2_N 5 20 SG1_MDX2_N 8 12
42 RXD5/TXDLY 13
R728 4.7K 43 RXD6/RXDLY HSIP 14 SG1_MDI3_P 3 22 SG1_MDX3_P RJ45_LED

14
NWay, advertize all capability 32 RXD7/AN0 HSIN
R729 4.7K 44 RXDV/RXCTL C1074 0.01uF 1 24 R730 75
RXER/AN1
B B
SGMII to Coper R731 4.7K 46 SG1_MDI3_N 2 23 SG1_MDX3_N
R732 4.7K 45 CRS/MII1
COL/MII0 C1075
72 68 H5008 1000pF
8,20,21,23,24,25 EMI1_MDC MDC LED0/PHY_AD0
73 69 C1076 0.1uF 2KV
8,20,21,23,24,25 EMI1_MDIO MDIO LED1/PHY_AD1 SGMII1_TX_P 9
70 C1077 0.1uF 100 ohms DIFF PAIR
LED2/MDI0 SGMII1_TX_N 9
71
LED3/MDI1 3V3
65 64
62 TDI TDO SG1_LED0 R733 510
63 TMS SG1_LED1 R734 510
TCK R735 4.7K R736 4.7K
29 SG1_RST_N
81 86 R737 4.7K R738 4.7K C1079 C1080
82 CKXTAL1 CLK125 PHY ADDR = 0x02 C1078 1000pF
CKXTAL2 SGMII to Coper 2KV 470pF 470pF
Y9 52 75 R739 0 C1081 1000pF
PHYRST INT SG1_INT_N 29
2KV
1 3 R741 0 77 74
R740 ENSWREG PME
C1082 C1083 78 28
25MHz 4.7K RSET NC1 29
2

4.7pF 4.7pF 26 NC2 30


REXT NC3 31
NC4 76 R742 15 C1084 1000pF
C C
NC5 DNP DNP
84 88 L17
R743 R744 85 VDDREG REG_OUT 4.7uH
1% 1% 2V5 VDDREG 47 C1085 C1086
2.49K 12.1K DVDD10 66 R745
34 DVDD10 22uF 0.1uF
40 DVDD33 24 0
51 DVDD33 REGV15
3V3 67 DVDD33 3 1V05_SG1_DVDD
DVDD33 AVDD10 9
6 AVDD10 12 C1087 C1088
25 AVDD33 AVDD10 16
C1089 C1090 C1091 80 AVDD33 AVDD10 23 0.1uF 0.1uF
AVDD33 AVDD10 79
0.1uF 0.1uF 0.1uF 15 AVDD10
19 AGND 83 1V05_SG1_AVDD
20 AGND GND 87
27 AGND GND 89 C1092 C1093 C1094 C1095 C1096 C1097
AGND EPAD
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RTL8211DN

D 3V3 2V5 D

C1098 C1099 C1100 C1101 C1102 C1103


Title
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 22 of 38


1 2 3 4 5
1 2 3 4 5

SGMII ETHERNET PORT 2


U83

48
GTX_CLK 17
HSOP SGMII2_RX_P 9
50 18 100 ohms DIFF PAIR
TXD0 HSON SGMII2_RX_N 9
53
A 54 TXD1 22 T13 3V3 A
55 TXD2 HSOP_CK 21 100 ohms FB45
57 TXD3 HSON_CK DIFF PAIRs SG2_MDI0_P 12 13 SG2_MDX0_P
58 TXD4 BLM18BD601SN1
59 TXD5 C1104 0.01uF 10 15 R746 75 C1105
60 TXD6 1
49 TXD7 MDIP0 2 SG2_MDI0_N 11 14 SG2_MDX0_N 0.1uF
61 TXEN/TXCTL MDIN0
TXER 4 SG2_MDI1_P 9 16 SG2_MDX1_P
56 MDIP1 5

13
TXCLK MDIN1 C1106 0.01uF 7 18 R747 75 J41
38 7 1 9
RXC MDIP2 8 SG2_MDI1_N 8 17 SG2_MDX1_N 2
33 MDIN2 3 10
35 RXD0 10 SG2_MDI2_P 6 19 SG2_MDX2_P 4
36 RXD1 MDIP3 11 5
2V5 37 RXD2 MDIN3 C1107 0.01uF 4 21 R748 75 6 11
2.5V GMII/RGMII R749 4.7K 39 RXD3 7
41 RXD4/SELRGV SG2_MDI2_N 5 20 SG2_MDX2_N 8 12
42 RXD5/TXDLY 13
R750 4.7K 43 RXD6/RXDLY HSIP 14 SG2_MDI3_P 3 22 SG2_MDX3_P RJ45_LED

14
NWay, advertize all capability 32 RXD7/AN0 HSIN
R751 4.7K 44 RXDV/RXCTL C1108 0.01uF 1 24 R752 75
RXER/AN1
B B
SGMII to Coper R753 4.7K 46 SG2_MDI3_N 2 23 SG2_MDX3_N
R754 4.7K 45 CRS/MII1
COL/MII0 C1109
72 68 H5008 1000pF
8,20,21,22,24,25 EMI1_MDC MDC LED0/PHY_AD0
73 69 C1110 0.1uF 2KV
8,20,21,22,24,25 EMI1_MDIO MDIO LED1/PHY_AD1 SGMII2_TX_P 9
70 C1111 0.1uF 100 ohms DIFF PAIR
LED2/MDI0 SGMII2_TX_N 9
71
LED3/MDI1 3V3
65 64
62 TDI TDO SG2_LED0 R755 510
63 TMS SG2_LED1 R756 510
TCK R757 4.7K R758 4.7K
29 SG2_RST_N
81 86 R759 4.7K R760 4.7K C1113 C1114
82 CKXTAL1 CLK125 PHY ADDR = 0x03 C1112 1000pF
CKXTAL2 SGMII to Coper 2KV 470pF 470pF
Y10 52 75 R761 0 C1115 1000pF
PHYRST INT SG2_INT_N 29
2KV
1 3 R762 0 77 74
R763 ENSWREG PME
C1116 C1117 78 28
25MHz 4.7K RSET NC1 29
2

4.7pF 4.7pF 26 NC2 30


REXT NC3 31
NC4 76 R764 15 C1118 1000pF
C C
NC5 DNP DNP
84 88 L18
R765 R766 85 VDDREG REG_OUT 4.7uH
1% 1% 2V5 VDDREG 47 C1119 C1120
2.49K 12.1K DVDD10 66 R767
34 DVDD10 22uF 0.1uF
40 DVDD33 24 0
51 DVDD33 REGV15
3V3 67 DVDD33 3 1V05_SG2_DVDD
DVDD33 AVDD10 9
6 AVDD10 12 C1121 C1122
25 AVDD33 AVDD10 16
C1123 C1124 C1125 80 AVDD33 AVDD10 23 0.1uF 0.1uF
AVDD33 AVDD10 79
0.1uF 0.1uF 0.1uF 15 AVDD10
19 AGND 83 1V05_SG2_AVDD
20 AGND GND 87
27 AGND GND 89 C1126 C1127 C1128 C1129 C1130 C1131
AGND EPAD
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RTL8211DN

D 3V3 2V5 D

C1132 C1133 C1134 C1135 C1136 C1137


Title
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 23 of 38


1 2 3 4 5
1 2 3 4 5

QSGMII PHY 1

U51A

D31 B18
A 26 QSG2_MDI0_P P0_D0P P1_D0P QSG1_MDI0_P 26 A
D30 B17
26 QSG2_MDI0_N P0_D0N P1_D0N QSG1_MDI0_N 26
C25 C29 1V0 U51B 2V5
26 QSG2_MDI1_P P0_D1P P1_D1P QSG1_MDI1_P 26
C24 C28
26 QSG2_MDI1_N P0_D1N P1_D1N QSG1_MDI1_N 26
E5 E3
D29 B16 E7 VDD1 VDD25 E4
26 QSG2_MDI2_P P0_D2P P1_D2P QSG1_MDI2_P 26 VDD1 VDD25
C23 B15 E10 E6
26 QSG2_MDI2_N P0_D2N P1_D2N QSG1_MDI2_N 26 VDD1 VDD25
E13 E8
C22 C27 E15 VDD1 VDD25 E12
26 QSG2_MDI3_P P0_D3P P1_D3P QSG1_MDI3_P 26 VDD1 VDD25
C21 C26 E17 E18
26 QSG2_MDI3_N P0_D3N P1_D3N QSG1_MDI3_N 26 VDD1 VDD25
E19 E20
E2 C3 E21 VDD1 VDD25 E22
26 QSG2_LED0 LED0_PHY0 LED0_PHY1 QSG1_LED0 26 VDD1 VDD25
D1 B2 E23 E24
26 QSG2_LED1 LED1_PHY0 LED1_PHY1 QSG1_LED1 26 VDD1 VDD25
D2 C4 1V0 E25 E26 2V5
C2 LED2_PHY0 LED2_PHY1 D4 FB22 VDD1 VDD25 FB23
LED3_PHY0 LED3_PHY1 E1 E27
C33 C1 BLM18PG121SN1 E11 VDD1A VDD25A E29 BLM18PG121SN1
26 QSG4_MDI0_P P2_D0P P3_D0P QSG3_MDI0_P 26 VDD1A VDD25A
C32 C36 E14 E31
26 QSG4_MDI0_N P2_D0N P3_D0N QSG3_MDI0_N 26 VDD1A VDD25A
E16 E33
B20 D35 E28 VDD1A VDD25A E35
26 QSG4_MDI1_P P2_D1P P3_D1P QSG3_MDI1_P 26 VDD1A VDD25A
B19 D34 E30 E37 2V5A_QSG1
26 QSG4_MDI1_N P2_D1N P3_D1N QSG3_MDI1_N 26 VDD1A VDD25A
E32 2V5
A10 C35 E34 VDD1A
26 QSG4_MDI2_P P2_D2P P3_D2P QSG3_MDI2_P 26 VDD1A
A9 C34 E36 E9
B 26 QSG4_MDI2_N P2_D2N P3_D2N QSG3_MDI2_N 26 VDD1A VDDMDIO B

C31 D33 B1 D9
26 QSG4_MDI3_P P2_D3P P3_D3P QSG3_MDI3_P 26 THERMDA VSS/EFUSE
C30 D32 D3 139
26 QSG4_MDI3_N P2_D3N P3_D3N QSG3_MDI3_N 26 THERMDC_VSS VSS_CASE
C5 B4
26 QSG4_LED0 LED0_PHY2 LED0_PHY3 QSG3_LED0 26
D5 C6 F104S8A
26 QSG4_LED1 LED1_PHY2 LED1_PHY3 QSG3_LED1 26
B3 A2
D6 LED2_PHY2 LED2_PHY3 D7
LED3_PHY2 LED3_PHY3 1V0A_QSG1
C431 0.1uF D16 D14
9 QSGMII1_TX_P QSGMII0_TXP QSGMII0_RXP QSGMII1_RX_P 9
C434 0.1uF D15 D13 C432 C433 C435 C436 C437 C438 C439 C440 C441
9 QSGMII1_TX_N QSGMII0_TXN QSGMII0_RXN QSGMII1_RX_N 9
C442 0.1uF D11 B13 2V5 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
30 QSG1_REFCLK_P REFCLK_P RCVRD_CLK0
C443 0.1uF D12 C20
30 QSG1_REFCLK_N REFCLK_N RCVRD_CLK1
D27
CLK_SQUELCH_IN R330
B8 2V5A_QSG1
REFCLK_SEL[1:0] = 00 for 125MHz clock B7 REFCLK_SEL0 2V5 4.7K
REFCLK_SEL1 C444 C445 C446 C447 C448
C11 C10 R331 0
,22,23,25 EMI1_MDC MDC MDINT QSG1_INT_N 29
D10 10uF 1uF 0.1uF 0.1uF 0.1uF
,22,23,25 EMI1_MDIO MDIO
C B5 C19 R333 4.7K DNP C
29 QSG1_RST_N RESET PHYADD2 B12 R334 4.7K PHY ADDR = 0x08~0B 1V0
D8 PHYADD3 D26 R335 4.7K DNP
COMA_MODE PHYADD4
D19 C17
R336 R337 C14 GPIO0 GPIO8 D22 C449 C450 C451 C452 C453 C454 C455
D20 GPIO1 GPIO9 D24
2V5 4.7K 4.7K C15 GPIO2 GPIO10 D23 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
B9 GPIO3 GPIO11 C18
C16 GPIO4 GPIO12 B11
D21 GPIO5 GPIO13 D25 2V5
B10 GPIO6 GPIO14
GPIO7
C9 C8
A3 JTAG_DI JTAG_DO C456 C457 C458 C459 C460 C461 C462
B6 JTAG_TMS
C7 JTAG_CLK 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
JTAG_TRST
A8 D17 R338 619
A7 REF_REXT SEDES_REXT_0 D18 1%
REF_FILT SEDES_REXT_1
A1 C12
R339 R340 C463 A4 NC1 HSTST_P/NC C13
1% A5 NC2 HSTST_N/NC D28
D 1K 2K 1uF A6 NC3 TANA_0/NC B14 D
NC4 TANA_1/NC

F104S8A

Title
Join as single point then to analog ground plane T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 24 of 38


1 2 3 4 5
1 2 3 4 5

QSGMII PHY 2

U52A

D31 B18
A 26 QSG6_MDI0_P P0_D0P P1_D0P QSG5_MDI0_P 26 A
D30 B17
26 QSG6_MDI0_N P0_D0N P1_D0N QSG5_MDI0_N 26
C25 C29 1V0 U52B 2V5
26 QSG6_MDI1_P P0_D1P P1_D1P QSG5_MDI1_P 26
C24 C28
26 QSG6_MDI1_N P0_D1N P1_D1N QSG5_MDI1_N 26
E5 E3
D29 B16 E7 VDD1 VDD25 E4
26 QSG6_MDI2_P P0_D2P P1_D2P QSG5_MDI2_P 26 VDD1 VDD25
C23 B15 E10 E6
26 QSG6_MDI2_N P0_D2N P1_D2N QSG5_MDI2_N 26 VDD1 VDD25
E13 E8
C22 C27 E15 VDD1 VDD25 E12
26 QSG6_MDI3_P P0_D3P P1_D3P QSG5_MDI3_P 26 VDD1 VDD25
C21 C26 E17 E18
26 QSG6_MDI3_N P0_D3N P1_D3N QSG5_MDI3_N 26 VDD1 VDD25
E19 E20
E2 C3 E21 VDD1 VDD25 E22
26 QSG6_LED0 LED0_PHY0 LED0_PHY1 QSG5_LED0 26 VDD1 VDD25
D1 B2 E23 E24
26 QSG6_LED1 LED1_PHY0 LED1_PHY1 QSG5_LED1 26 VDD1 VDD25
D2 C4 1V0 E25 E26 2V5
C2 LED2_PHY0 LED2_PHY1 D4 FB24 VDD1 VDD25 FB25
LED3_PHY0 LED3_PHY1 E1 E27
C33 C1 BLM18PG121SN1 E11 VDD1A VDD25A E29 BLM18PG121SN1
26 QSG8_MDI0_P P2_D0P P3_D0P QSG7_MDI0_P 26 VDD1A VDD25A
C32 C36 E14 E31
26 QSG8_MDI0_N P2_D0N P3_D0N QSG7_MDI0_N 26 VDD1A VDD25A
E16 E33
B20 D35 E28 VDD1A VDD25A E35
26 QSG8_MDI1_P P2_D1P P3_D1P QSG7_MDI1_P 26 VDD1A VDD25A
B19 D34 E30 E37 2V5A_QSG2
26 QSG8_MDI1_N P2_D1N P3_D1N QSG7_MDI1_N 26 VDD1A VDD25A
E32 2V5
A10 C35 E34 VDD1A
26 QSG8_MDI2_P P2_D2P P3_D2P QSG7_MDI2_P 26 VDD1A
A9 C34 E36 E9
B 26 QSG8_MDI2_N P2_D2N P3_D2N QSG7_MDI2_N 26 VDD1A VDDMDIO B

C31 D33 B1 D9
26 QSG8_MDI3_P P2_D3P P3_D3P QSG7_MDI3_P 26 THERMDA VSS/EFUSE
C30 D32 D3 139
26 QSG8_MDI3_N P2_D3N P3_D3N QSG7_MDI3_N 26 THERMDC_VSS VSS_CASE
C5 B4
26 QSG8_LED0 LED0_PHY2 LED0_PHY3 QSG7_LED0 26
D5 C6 F104S8A
26 QSG8_LED1 LED1_PHY2 LED1_PHY3 QSG7_LED1 26
B3 A2
D6 LED2_PHY2 LED2_PHY3 D7
LED3_PHY2 LED3_PHY3 1V0A_QSG2
C464 0.1uF D16 D14
9 QSGMII2_TX_P QSGMII0_TXP QSGMII0_RXP QSGMII2_RX_P 9
C470 0.1uF D15 D13 C465 C466 C467 C468 C469 C471 C472 C473 C474
9 QSGMII2_TX_N QSGMII0_TXN QSGMII0_RXN QSGMII2_RX_N 9
C475 0.1uF D11 B13 2V5 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
30 QSG2_REFCLK_P REFCLK_P RCVRD_CLK0
C476 0.1uF D12 C20
30 QSG2_REFCLK_N REFCLK_N RCVRD_CLK1
D27
CLK_SQUELCH_IN R341
B8 2V5A_QSG2
REFCLK_SEL[1:0] = 00 for 125MHz clock B7 REFCLK_SEL0 2V5 4.7K
REFCLK_SEL1 C477 C478 C479 C480 C481
C11 C10 R342 0
,22,23,24 EMI1_MDC MDC MDINT QSG2_INT_N 29
D10 10uF 1uF 0.1uF 0.1uF 0.1uF
,22,23,24 EMI1_MDIO MDIO
C B5 C19 R344 4.7K C
29 QSG2_RST_N RESET PHYADD2 B12 R345 4.7K PHY ADDR = 0x0C~0F 1V0
D8 PHYADD3 D26 R346 4.7K DNP
COMA_MODE PHYADD4
D19 C17
R347 R348 C14 GPIO0 GPIO8 D22 C482 C483 C484 C485 C486 C487 C488
D20 GPIO1 GPIO9 D24
2V5 4.7K 4.7K C15 GPIO2 GPIO10 D23 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
B9 GPIO3 GPIO11 C18
C16 GPIO4 GPIO12 B11
D21 GPIO5 GPIO13 D25 2V5
B10 GPIO6 GPIO14
GPIO7
C9 C8
A3 JTAG_DI JTAG_DO C489 C490 C491 C492 C493 C494 C495
B6 JTAG_TMS
C7 JTAG_CLK 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF
JTAG_TRST
A8 D17 R349 619
A7 REF_REXT SEDES_REXT_0 D18 1%
REF_FILT SEDES_REXT_1
A1 C12
R350 R351 C496 A4 NC1 HSTST_P/NC C13
1% A5 NC2 HSTST_N/NC D28
D 1K 2K 1uF A6 NC3 TANA_0/NC B14 D
NC4 TANA_1/NC

F104S8A

Title
Join as single point then to analog ground plane T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 25 of 38


1 2 3 4 5
1 2 3 4 5

QSGMII ETHERNET PORTs


T4 2V5_LED T5 2V5_LED

97
98
2 23 QSG5_MDX0_P J21E 2 23 QSG1_MDX0_P J21A
25 QSG5_MDI0_P 24 QSG1_MDI0_P
C497 0.1uF 1 24 R352 75 E1 E9 C498 0.1uF 1 24 R353 75 A1 A9
3 22 QSG5_MDX0_N E2 3 22 QSG1_MDX0_N A2
25 QSG5_MDI0_N QSG5_MDX1_P 24 QSG1_MDI0_N QSG1_MDX1_P
5 20 E3 E10 5 20 A3 A10
25 QSG5_MDI1_P 24 QSG1_MDI1_P
C499 0.1uF 4 21 R354 75 E4 C500 0.1uF 4 21 R355 75 A4
A 6 19 QSG5_MDX1_N E5 6 19 QSG1_MDX1_N A5 A
25 QSG5_MDI1_N QSG5_MDX2_P 24 QSG1_MDI1_N QSG1_MDX2_P
8 17 E6 E11 8 17 A6 A11
25 QSG5_MDI2_P 24 QSG1_MDI2_P
C501 0.1uF 7 18 R356 75 E7 C502 0.1uF 7 18 R357 75 A7
9 16 QSG5_MDX2_N E8 E12 9 16 QSG1_MDX2_N A8 A12
25 QSG5_MDI2_N QSG5_MDX3_P 24 QSG1_MDI2_N QSG1_MDX3_P
11 14 11 14
25 QSG5_MDI3_P 24 QSG1_MDI3_P
C503 0.1uF 10 15 R358 75 RJ45_LED_8 C504 0.1uF 10 15 R359 75 RJ45_LED_8
12 13 QSG5_MDX3_N 12 13 QSG1_MDX3_N
25 QSG5_MDI3_N 24 QSG1_MDI3_N
R360 510 R361 510
25 QSG5_LED0 24 QSG1_LED0
H5008 C505 1000pF R362 510 H5008 C506 1000pF R363 510
25 QSG5_LED1 24 QSG1_LED1
2KV 2KV
C507 470pF C508 470pF
C509 470pF C510 470pF

T7 2V5_LED T6 2V5_LED
2 23 QSG6_MDX0_P J21F 2 23 QSG2_MDX0_P J21B
25 QSG6_MDI0_P 24 QSG2_MDI0_P
C511 0.1uF 1 24 R364 75 F1 F9 C512 0.1uF 1 24 R365 75 B1 B9
3 22 QSG6_MDX0_N F2 3 22 QSG2_MDX0_N B2
25 QSG6_MDI0_N 24 QSG2_MDI0_N
5 20 QSG6_MDX1_P F3 F10 5 20 QSG2_MDX1_P B3 B10
25 QSG6_MDI1_P 24 QSG2_MDI1_P
C513 0.1uF 4 21 R366 75 F4 C514 0.1uF 4 21 R367 75 B4
6 19 QSG6_MDX1_N F5 6 19 QSG2_MDX1_N B5
25 QSG6_MDI1_N 24 QSG2_MDI1_N
8 17 QSG6_MDX2_P F6 F11 8 17 QSG2_MDX2_P B6 B11
25 QSG6_MDI2_P 24 QSG2_MDI2_P
C515 0.1uF 7 18 R368 75 F7 C516 0.1uF 7 18 R369 75 B7
9 16 QSG6_MDX2_N F8 F12 9 16 QSG2_MDX2_N B8 B12
B 25 QSG6_MDI2_N QSG6_MDX3_P 24 QSG2_MDI2_N QSG2_MDX3_P
B
11 14 11 14
25 QSG6_MDI3_P 24 QSG2_MDI3_P
C517 0.1uF 10 15 R370 75 RJ45_LED_8 C518 0.1uF 10 15 R371 75 RJ45_LED_8
12 13 QSG6_MDX3_N 12 13 QSG2_MDX3_N
25 QSG6_MDI3_N 24 QSG2_MDI3_N
R372 510 R373 510
25 QSG6_LED0 24 QSG2_LED0
H5008 C519 1000pF R374 510 H5008 C520 1000pF R375 510
25 QSG6_LED1 24 QSG2_LED1
2KV 2KV
C521 470pF C522 470pF
C523 470pF C524 470pF

T9 2V5_LED T8 2V5_LED
2 23 QSG7_MDX0_P J21G 2 23 QSG3_MDX0_P J21C
25 QSG7_MDI0_P 24 QSG3_MDI0_P
C525 0.1uF 1 24 R376 75 G1 G9 C526 0.1uF 1 24 R377 75 C1 C9
3 22 QSG7_MDX0_N G2 3 22 QSG3_MDX0_N C2
25 QSG7_MDI0_N QSG7_MDX1_P 24 QSG3_MDI0_N QSG3_MDX1_P
5 20 G3 G10 5 20 C3 C10
25 QSG7_MDI1_P 24 QSG3_MDI1_P
C527 0.1uF 4 21 R378 75 G4 C528 0.1uF 4 21 R379 75 C4
6 19 QSG7_MDX1_N G5 6 19 QSG3_MDX1_N C5
25 QSG7_MDI1_N QSG7_MDX2_P 24 QSG3_MDI1_N QSG3_MDX2_P
8 17 G6 G11 8 17 C6 C11
25 QSG7_MDI2_P 24 QSG3_MDI2_P
C529 0.1uF 7 18 R380 75 G7 C530 0.1uF 7 18 R381 75 C7
9 16 QSG7_MDX2_N G8 G12 9 16 QSG3_MDX2_N C8 C12
25 QSG7_MDI2_N QSG7_MDX3_P 24 QSG3_MDI2_N QSG3_MDX3_P
11 14 11 14
25 QSG7_MDI3_P 24 QSG3_MDI3_P
C531 0.1uF 10 15 R382 75 RJ45_LED_8 C532 0.1uF 10 15 R383 75 RJ45_LED_8
12 13 QSG7_MDX3_N 12 13 QSG3_MDX3_N
25 QSG7_MDI3_N 24 QSG3_MDI3_N
C R384 510 R385 510 C
25 QSG7_LED0 24 QSG3_LED0
H5008 C533 1000pF R386 510 H5008 C534 1000pF R387 510
25 QSG7_LED1 24 QSG3_LED1
2KV 2KV
C535 470pF C536 470pF
C537 470pF C538 470pF

T11 2V5_LED T10 2V5_LED


2 23 QSG8_MDX0_P J21H 2 23 QSG4_MDX0_P J21D
25 QSG8_MDI0_P 24 QSG4_MDI0_P
C539 0.1uF 1 24 R388 75 H1 H9 C541 0.1uF 1 24 R390 75 D1 D9
3 22 QSG8_MDX0_N H2 3 22 QSG4_MDX0_N D2
25 QSG8_MDI0_N QSG8_MDX1_P 24 QSG4_MDI0_N QSG4_MDX1_P
5 20 H3 H10 5 20 D3 D10
25 QSG8_MDI1_P 24 QSG4_MDI1_P
C540 0.1uF 4 21 R389 75 H4 C542 0.1uF 4 21 R391 75 D4
6 19 QSG8_MDX1_N H5 6 19 QSG4_MDX1_N D5
25 QSG8_MDI1_N 24 QSG4_MDI1_N
8 17 QSG8_MDX2_P H6 H11 8 17 QSG4_MDX2_P D6 D11
25 QSG8_MDI2_P 24 QSG4_MDI2_P
C543 0.1uF 7 18 R392 75 H7 C544 0.1uF 7 18 R393 75 D7
9 16 QSG8_MDX2_N H8 H12 9 16 QSG4_MDX2_N D8 D12
25 QSG8_MDI2_N QSG8_MDX3_P 24 QSG4_MDI2_N QSG4_MDX3_P
11 14 11 14
25 QSG8_MDI3_P 24 QSG4_MDI3_P
C545 0.1uF 10 15 R394 75 RJ45_LED_8 C546 0.1uF 10 15 R395 75 RJ45_LED_8
99
100

12 13 QSG8_MDX3_N 12 13 QSG4_MDX3_N C547 470pF


25 QSG8_MDI3_N 24 QSG4_MDI3_N
R396 510
24 QSG4_LED0
H5008 C548 1000pF H5008 C549 1000pF R397 510
24 QSG4_LED1
2KV 2KV C550 470pF
R398 510 C551 1000pF
25 QSG8_LED0
D R399 510 2KV D
25 QSG8_LED1
2V5 2V5_LED C552 1000pF
FB26 C553 470pF 2KV
C554 470pF C555 1000pF
BLM18BD601SN1 2KV
C556 C557 C558 C559 1000pF Title
2KV T104XRDB
0.1uF 4.7uF 0.01uF C560 1000pF
2KV Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 26 of 38


1 2 3 4 5
1 2 3 4 5

PCIe X1 SLOT, MINI PCIe and SATA CONNECTORs

MINI PCIe CONNECTOR 3V3

3V3 J27 R442 4.7K


R443 4.7K
PCIe x1 SLOT 2 30
3.3V SMB_CLK I2C2_MPEX1_SCL 7
52 32
A 3.3V SMB_DATA I2C2_MPEX1_SDA 7 A
12V J26 3V3
1V5 24 1 R446 4.7K
B1 B9 R444 4.7K 3.3VAUX WAKE
B2 +12V JTAG1_TRST A5 R447 4.7K 6 22
+12V JTAG2_TCK 1.5V PERST MPEX1_RST_N 29
A2 A6 R448 4.7K 28
A3 +12V JTAG3_TDI A7 48 1.5V 7
3V3 3V3 B3 +12V JTAG4_TDO A8 R445 4.7K 1.5V CLKREQ
+12V JTAG5_TMS 13
REFCLK+ MPEX1_REFCLK_N 31
B8 11
+3V3 REFCLK- MPEX1_REFCLK_P 31
A9
R449 A10 +3V3 3V3 4 25 C737 0.1uF
+3V3 GND PERP0 MPEX1_RX_P 8
9 23 C738 0.1uF
GND PERN0 MPEX1_RX_N 8
4.7K B10 R450 4.7K 15
+3V3AUX R451 4.7K 18 GND 33 C739 0.1uF
GND PETP0 MPEX1_TX_P 8
A1 B5 21 31 C740 0.1uF
PRSNT1 SMCLK I2C2_PEX_SCL 7 GND PETN0 MPEX1_TX_N 8
B17 B6 26
29 PEX_PRS_N PRSNT2_X1 SMDAT I2C2_PEX_SDA 7 GND
27 38 100 ohms
B12 B11 R452 4.7K 29 GND USB_D+ 36 DIFF PAIRs
RSVD1 WAKE 34 GND USB_D-
B4 A11 35 GND 42 3V3
GND PERST PEX_RST_N 29 GND LED_WWAN
A4 40 44
B7 GND A13 50 GND LED_WLAN 46
GND REFCLK+ PEX_REFCLK_P 31 GND LED_WPAN
A12 A14
GND REFCLK- PEX_REFCLK_N 31
B13 3 20 C742 C743 C744 C745 C746 C747
B GND RSVD1 RSVD10 B
A15 A16 C741 0.1uF 5 37
GND PERP0 PEX_RX_P 9 RSVD2 RSVD11
B16 A17 C748 0.1uF 8 39 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF
GND PERN0 PEX_RX_N 9 RSVD3 RSVD12
B18 10 41
A18 GND B14 C749 0.1uF 12 RSVD4 RSVD13 43
GND PETP0 PEX_TX_P 9 RSVD5 RSVD14
B15 C750 0.1uF 14 45 1V5
PETN0 PEX_TX_N 9 RSVD6 RSVD15
END OF X1 16 47
100 ohms 17 RSVD7 RSVD16 49
PCIE_X1 DIFF PAIRs 19 RSVD8 RSVD17 51
Z17 M2 M3 RSVD9 RSVD18 C751 C752 C753 C754 C755 C756
53 54
MS1 MS2 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF

MINIPCIE_CONN

MINI PCIe CONNECTOR 3V3

3V3 J28 R453 4.7K


R454 4.7K
2 30
3.3V SMB_CLK I2C2_MPEX2_SCL 7
52 32
3.3V SMB_DATA I2C2_MPEX2_SDA 7
1V5 24 1 R455 4.7K
3.3VAUX WAKE
C 6 22 C
1.5V PERST MPEX2_RST_N 29
28
48 1.5V 7
1.5V CLKREQ
12V 3V3 13
REFCLK+ MPEX2_REFCLK_N 31
11
REFCLK- MPEX2_REFCLK_P 31
4 25 C757 0.1uF
GND PERP0 MPEX2_RX_P 8
C758 C759 C760 C761 C762 C763 C764 C765 C766 C767 9 23 C768 0.1uF
GND PERN0 MPEX2_RX_N 8
15
100uF 10uF 10uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 18 GND 33 C769 0.1uF
GND PETP0 MPEX2_TX_P 8
25V 21 31 C770 0.1uF
GND PETN0 MPEX2_TX_N 8
26
27 GND 38 100 ohms
29 GND USB_D+ 36 DIFF PAIRs
34 GND USB_D-
35 GND 42
ON-BOARD SATA CONNECTOR 40 GND LED_WWAN 44
J29 50 GND LED_WLAN 46
T1040 ONLY! GND LED_WPAN
3 20
1 5 RSVD1 RSVD10 37
C771 0.01uF 2 GND 8 RSVD2 RSVD11 39
8 SATA_TX_P TX_P RSVD3 RSVD12
C772 0.01uF 3 10 41
8 SATA_TX_N TX_N RSVD4 RSVD13
D 4 12 43 D
C773 0.01uF 5 GND 14 RSVD5 RSVD14 45
8 SATA_RX_N RX_N RSVD6 RSVD15
C774 0.01uF 6 16 47
8 SATA_RX_P RX_P RSVD7 RSVD16
7 17 49
100 ohms GND 19 RSVD8 RSVD17 51
DIFF PAIRs 8 Z18 M4 M5 RSVD9 RSVD18 Title
9 MH1 53 54 T104XRDB
MH2 MS1 MS2
Size Document Number Design Engineer Rev
SATA_CONN MINIPCIE_CONN B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 27 of 38


1 2 3 4 5
1 2 3 4 5

AURORA PORT

A A

3V3_SLP

1K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
100 ohms
J30 DIFF PAIRs

R456
R457
R458
R459
R460
R461
R462
R463
R464
R465

R466
1
TX0_P AURORA_TX_P 9
2 3
VIO TX0_N AURORA_TX_N 9
4 13 C775 0.01uF
29 AURORA_TCK TCK RX0_P AURORA_RX_P 9
6 15 C776 0.01uF
29 AURORA_TMS TMS RX0_N AURORA_RX_N 9
8
29 AURORA_TDI TDI
10 7 Aurora expects DC‐blocking caps at RX
29 AURORA_TDO TDO TX1_P
12 9
29 AURORA_TRST_N TRST TX1_N
19
RX1_P 21
RX1_N
B B
R467 10 14 25
29 AURORA_HALT_N I/O_0 TX2_P
R468 10 16 27
29 AURORA_EVTI_N I/O_1 TX2_N
R469 10 18
29 AURORA_EVTO_N I/O_2
AURORA_CLKOUT 20 37
TP19 AURORA_RDY_N 32 I/O_3 RX2_P 39
34 I/O_4 RX2_N
29 AURORA_HRST_N I/O_5
(OPEN-DRAIN) 31
TX3_P 33
AURORA NET DUT PIN FUNCTION TX3_N
38 43
IO0 AURORA_HALT_N EVT0_N POWER‐ON DEBUG INPUT FROM DCU TO DUT 40 RSV1 RX3_P 45
IO1 AURORA_EVTI_N EVT1_N SYNC PACKET REQUEST FROM DCU TO DUT 44 RSV2 RX3_N
IO2 AURORA_EVTO_N EVT4_N WATCHPOINT TRIG OUT FROM DUT TO DCU 46 RSV3 49
IO3 AURORA_CLKOUT CLKOUT CLKOUT DEBUG CLKOUT FROM DUT TO DCU 50 RSV4 TX4_P 51
IO4 AURORA_RDY_N NA R/W ACCESS TRANSFER COMPLETE W/O ERROR 52 RSV5 TX4_N
IO5 DUT_HRESET_N HRESET_N OPEN‐DRAIN WARM RESET TO/FROM DUT 56 RSV6 55
58 RSV7 TX5_P 57
62 RSV8 TX5_N
64 RSV9 61
68 RSV10 TX6_P 63
70 RSV11 TX6_N
RSV12 67
TX7_P 69 100 ohms
TX7_N DIFF PAIR
C C
22 26
28,29 AURORA_PORST_N RESET CLK_P AURORA_REFCLK_P 31
(OPEN-DRAIN) 28

GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
CLK_N AURORA_REFCLK_N 31
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
CONN SKT 70
5
11
17
23
24
29
30
35
36
41
42
47
48
53
54
59
60
65
66
G1
G2

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 28 of 38


1 2 3 4 5
1 2 3 4 5

CPLD
3.3V BANK1 IO 1.8V BANK2 IO
CPLD_TDO IO_F1 IO_B9 IFC_AD15 IFC_AD[0..15] 4,5
cfg
IO_G2 COP_SRESET_N 7 IO_A9 IFC_AD14
cfg
IO_D1 COP_HRESET_N 7 IO_C8 IFC_AD13
U57A U57B cfg
COP_TRST_N 7
IO_P7 IO_A8 cfg IFC_AD12
IO_C2 IO_A2 IO_R14 GPIO_CKE_ISO 7 IO_B8 IFC_AD11
C2 A2 H5 M8 cfg
IO_C3 IO_B1_C2 IO_B2_A2 IO_A4 30 CPLD_REFCLK GCLK0p DEV_OE IO_P12 TDMR_SLP_N 15 IO_A7 IFC_AD10
C3 A4 J5 M9 cfg
IO_D1 IO_B1_C3 IO_B2_A4 IO_A5 GCLK1p DEV_CLRn IO_H3 TDMR_PRS_N 15 IO_B7 IFC_AD9
D1 A5 J12 cfg
A IO_D2 IO_B1_D1 IO_B2_A5 IO_A6 4 IFC_CLK GCLK2p IO_M2 SENSEVDD_EN_N 32 IO_A6 IFC_AD8 A
D2 A6 H12 cfg
IO_D3 IO_B1_D2 IO_B2_A6 IO_A7 GCLK3p IO_N1 EC1_RST_N 19 IO_A10 IFC_AD7
D3 A7
IO_B1_D3 IO_B2_A7 EC2_RST_N 20
IO_E1 E1 A8 IO_A8 CPLD_TDI L6 M5 IO_N2 IO_B10 IFC_AD6
IO_B1_E1 IO_B2_A8 TDI TDO SG_RST_N 21
IO_E2 E2 A9 IO_A9 CPLD_TMS N4 IO_R3 IO_B11 IFC_AD5
IO_E3 IO_B1_E2 IO_B2_A9 IO_A10 CPLD_TCK TMS IO_P4 SG1_RST_N 22 IO_A11 IFC_AD4
E3 A10 P3
IO_B1_E3 IO_B2_A10 TCK SG2_RST_N 23
IO_E4 E4 A11 IO_A11 IO_R1 OD OUTPUT IO_A12 IFC_AD3
IO_B1_E4 IO_B2_A11 QSG1_RST_N 24
IO_F1 F1 A12 IO_A12 H8 H7 IO_M3 OD OUTPUT IO_B12 IFC_AD2
IO_F2 IO_B1_F1 IO_B2_A12 IO_A13 VCCINT GNDINT IO_M4 QSG2_RST_N 25 IO_B13 IFC_AD1
F2 A13 1V8_SLP H10 H9
IO_B1_F2 IO_B2_A13 VCCINT GNDINT PEX_RST_N 27
IO_F3 F3 A15 IO_A15 J7 J8 IO_E4 IO_A13 IFC_AD0
IO_G1 IO_B1_F3 IO_B2_A15 IO_B1 VCCINT GNDINT IO_E3 MPEX1_RST_N 27 IO_A5 IFC_A31 IFC_A[27..31] 4,5
G1 B1 J9 J10
IO_B1_G1 IO_B2_B1 VCCINT GNDINT MPEX2_RST_N 27
IO_G2 G2 B3 IO_B3 IO_J2 IO_D12 IFC_A30
IO_G3 IO_B1_G2 IO_B2_B3 IO_B4 IO_E2 PWR_RST_N 36 IO_C11 IFC_A29
G3 B4 C1 A1
IO_B1_G3 IO_B2_B4 VCCIO1 GNDIO COP_TDI 7
IO_H1 H1 B5 IO_B5 H6 A16 IO_F2 IO_C12 IFC_A28
IO_H2 IO_B1_H1 IO_B2_B5 IO_B6 VCCIO1 GNDIO IO_E1 COP_TMS 7 IO_C13 IFC_A27
H2 B6 J6 B2
IO_H3 IO_B1_H2 IO_B2_B6 IO_B7 VCCIO1 GNDIO IO_F3 COP_TCK 7 IO_D16
H3 B7 L8 B15 cfg
IO_J1 IO_B1_H3 IO_B2_B7 IO_B8 VCCIO1 GNDIO IO_C3 THERM_FAULT_N 14 IO_E15 IFC_A16 4,5
J1 B8 L9 G7 cfg
IO_B1_J1 IO_B2_B8 VCCIO1 GNDIO THERM_ALERT_N 14 IFC_A17 4,5
IO_J2 J2 B9 IO_B9 3V3_SLP P1 G8 IO_R16 IO_B6
IO_B1_J2 IO_B2_B9 VCCIO1 GNDIO FAN_PWM 36 IFC_CS0_N 4
IO_J3 J3 B10 IO_B10 T3 G9 IO_P5 IO_B5
IO_B1_J3 IO_B2_B10 VCCIO1 GNDIO PEX_PRS_N 27 IFC_CS1_N 4
IO_K1 K1 B11 IO_B11 T14 G10 IO_D2 IO_A4
IO_K2 IO_B1_K1 IO_B2_B11 IO_B12 VCCIO1 GNDIO IO_G1 COP_TDO 7 IO_H15 IFC_CS2_N 4
K2 B12 A3 K7 cfg
IO_B1_K2 IO_B2_B12 VCCIO2 GNDIO COP_CKSTP_OUT_N 7 IFC_WE_N 4,5
IO_K3 K3 B13 IO_B13 A14 K8 IO_P2 IO_G15 cfg
IO_B1_K3 IO_B2_B13 VCCIO2 GNDIO SG1_INT_N 22 IFC_OE_N 4,5
IO_L1 L1 B14 IO_B14 C16 K9 IO_G3 IO_A15
IO_B1_L1 IO_B2_B14 VCCIO2 GNDIO CKE_ISO_EN 35 IFC_RB0_N 4
IO_L2 L2 B16 IO_B16 F8 K10 IO_C2 IO_B16
IO_B1_L2 IO_B2_B16 VCCIO2 GNDIO EVDD_SEL 35 IFC_RB1_N 4
IO_L3 L3 C4 IO_C4 F9 R2 IO_L4 IO_D13
B
IO_L4 IO_B1_L3 IO_B2_C4 IO_C5 VCCIO2 GNDIO IO_T4 QSG_SEL_N 9 IO_C14 NOR_CS_N 5 B
L4 C5 1V8_SLP H11 R15
IO_B1_L4 IO_B2_C5 VCCIO2 GNDIO PEX_SEL 9 NOR_RST_N 5
IO_M1 M1 C6 IO_C6 J11 T1 IO_M1 IO_E14
IO_B1_M1 IO_B2_C6 VCCIO2 GNDIO DVI_RST_N 16 NOR_RB_N 5
IO_M2 M2 C7 IO_C7 P16 T16 IO_H2 IO_D15 cfg
IO_B1_M2 IO_B2_C7 VCCIO2 GNDIO LED_STATUS 36 IFC_CLE 4,5
IO_M3 M3 C8 IO_C8 IO_T13 IO_F16 cfg
IO_B1_M3 IO_B2_C8 QE_MUX_CFG0 11 IFC_WP_N 4,5
IO_M4 M4 C9 IO_C9 D6 H4 IO_R12
IO_N1 IO_B1_M4 IO_B2_C9 IO_C10 NC_D6 NC_H4 IO_L2 QE_MUX_CFG1 11 IO_J16 CFG_VBANK0 CFG_VBANK[0..2] 5
N1 C10 D7 H13
IO_N2 IO_B1_N1 IO_B2_C10 IO_C11 NC_D7 NC_H13 IO_N5 DVI_INT_N 16 IO_H16 CFG_VBANK1
N2 C11 D8 J4
IO_N3 IO_B1_N2 IO_B2_C11 IO_C12 NC_D8 NC_J4 IO_P6 DFP_RST_N 17 IO_J15 CFG_VBANK2
N3 C12 D9 J13
IO_B1_N3 IO_B2_C12 NC_D9 NC_J13 DFP_INT_N 17
IO_N5 N5 C13 IO_C13 D10 K4 IO_R4 IO_G16
IO_N12 IO_B1_N5 IO_B2_C13 IO_C14 NC_D10 NC_K4 IO_J1 DFP_MODE 17 IO_D11 NAND_CS_N 5
N12 C14 E5 K5
IO_P2 IO_B1_N12 IO_B2_C14 IO_C15 NC_E5 NC_K5 IO_K1 DFP_BACKLIGHT 17 IO_C4 NAND_RB_N 5
P2 C15 E6 K6
IO_B1_P2 IO_B2_C15 NC_E6 NC_K6 DFP_BL_PWM 17 JTAG_TDI 7
IO_P4 P4 D4 IO_D4 E7 K11 IO_P8 IO_C5
IO_B1_P4 IO_B2_D4 NC_E7 NC_K11 TDMR_RST_N 15,18 JTAG_TMS 7
IO_P5 P5 D5 IO_D5 E8 K12 IO_K3 IO_B4
IO_P6 IO_B1_P5 IO_B2_D5 IO_D11 NC_E8 NC_K12 IO_L3 QSG1_INT_N 24 IO_C6 JTAG_TCK 7
P6 D11 E9 K13
IO_P7 IO_B1_P6 IO_B2_D11 IO_D12 NC_E9 NC_K13 IO_R13 QSG2_INT_N 25 IO_C7 JTAG_TDO 7
P7 D12 E10 L5
IO_P8 IO_B1_P7 IO_B2_D12 IO_D13 NC_E10 NC_L5 IO_N3 PROFI_MUX_CFG 18 IO_C9 JTAG_TRST_N 7
P8 D13 E11 L7
IO_B1_P8 IO_B2_D13 NC_E11 NC_L7 SG2_INT_N 23 CKSTP_OUT_N 7
IO_P9 P9 D14 IO_D14 E12 L10 IO_P11 IO_E13
IO_P10 IO_B1_P9 IO_B2_D14 IO_D15 NC_E12 NC_L10 IO_P10 TDMR1_INT_N 15 IO_F13 EVT0_N 7
P10 D15 F4 L11
IO_P11 IO_B1_P10 IO_B2_D15 IO_D16 NC_F4 NC_L11 IO_T15 TDMR2_INT_N 15 IO_B14 EVT1_N 7
P11 D16 F5 L12
IO_P12 IO_B1_P11 IO_B2_D16 IO_E13 NC_F5 NC_L12 IO_R5 FAN_TACH 36 IO_A2 EVT4_N 7
P12 E13 F6 M6 OD OUTPUT
IO_P13 IO_B1_P12 IO_B2_E13 IO_E14 NC_F6 NC_M6 IO_T6 AURORA_TCK 28 IO_C10 DDR_RST_N 3
P13 E14 F7 M7
IO_R1 IO_B1_P13 IO_B2_E14 IO_E15 NC_F7 NC_M7 IO_T5 AURORA_TMS 28 IO_F14 PORESET_N 7
R1 E15 F10 M10 OD OUTPUT
IO_B1_R1 IO_B2_E15 NC_F10 NC_M10 AURORA_TDI 28 HRESET_N 7
IO_R3 R3 E16 IO_E16 F11 M11 IO_R7 IO_K15
IO_R4 IO_B1_R3 IO_B2_E16 IO_F13 NC_F11 NC_M11 IO_R6 AURORA_TDO 28 RESET_REQ_N 7
C R4 F13 F12 M12 C
IO_R5 IO_B1_R4 IO_B2_F13 IO_F14 NC_F12 NC_M12 IO_T7 AURORA_TRST_N 28 IO_C15
R5 F14 G4 N6
IO_R6 IO_B1_R5 IO_B2_F14 IO_F15 NC_G4 NC_N6 IO_R8 AURORA_HALT_N 28 IO_D14 CPLD_INT1_N 7
R6 F15 G5 N7
IO_R7 IO_B1_R6 IO_B2_F15 IO_F16 NC_G5 NC_N7 IO_T8 AURORA_EVTI_N 28 IO_M16 CPLD_INT2_N 7
R7 F16 G6 N8
IO_R8 IO_B1_R7 IO_B2_F16 IO_G14 NC_G6 NC_N8 IO_P9 AURORA_EVTO_N 28 IO_L15 SDHC_VS 7
R8 G14 G11 N9
IO_B1_R8 IO_B2_G14 NC_G11 NC_N9 AURORA_HRST_N 28 EVT_PWR_EN 7
IO_R9 R9 G15 IO_G15 G12 N10 IO_T9 IO_L16
IO_B1_R9 IO_B2_G15 NC_G12 NC_N10 AURORA_PORST_N 28 EVT_PWR_OK 7
IO_R10 R10 G16 IO_G16 1V8_SLP G13 N11 IO_H1 IO_K16
IO_R11 IO_B1_R10 IO_B2_G16 IO_H14 NC_G13 NC_N11 IO_L1 PWR_GOOD 36 IO_P15 EVT_BRD_ISO 7
R11 H14
IO_R12 IO_B1_R11 IO_B2_H14 IO_H15 IO_K2 3V3_PGOOD 33 IO_P14 SD_REFCLK_EN_N 31
R12 H15
IO_R13 IO_B1_R12 IO_B2_H15 IO_H16 IO_T2 IOPWR_EN 33,35 IO_E16 SINGLE_CLK_EN_N 30,31
R13 H16 EPM570GF256 cfg
IO_B1_R13 IO_B2_H16 IOPWR_EN_N 35 TEST_SEL_N 7
IO_R14 R14 J14 IO_J14 C777 C778 C779 C780 IO_P13 IO_F15 BOOT_FLASH_SEL
IO_R16 IO_B1_R14 IO_B2_J14 IO_J15 IO_J3 VCORE_EN 32
R16 J15
IO_T2 IO_B1_R16 IO_B2_J15 IO_J16 IO_N12 VCORE_PGOOD 32
T2 J16 1uF 0.1uF 0.1uF 0.1uF
IO_T4 IO_B1_T2 IO_B2_J16 IO_K14 IO_R9 VDD_EN_N 32
T4 K14 CPLD JTAG CONNECTOR
IO_B1_T4 IO_B2_K14 DDRPWR_EN 33
IO_T5 T5 K15 IO_K15 IO_T10 3V3_SLP J31 3V3_SLP
IO_T6 IO_B1_T5 IO_B2_K15 IO_K16 IO_T11 DDR_PGOOD 33 CPLD_TCK
T6 K16 3V3_SLP R470 4.7K
IO_B1_T6 IO_B2_K16 GVDD_EN_N 35 1 2
IO_T7 T7 L13 IO_L13 IO_R10 CPLD_TDO
IO_T8 IO_B1_T7 IO_B2_L13 IO_L14 IO_D3 VPP_EN 34 CPLD_TMS 3 4
T8 L14 R471 10K
IO_B1_T8 IO_B2_L14 VTT_EN 34 5 6
IO_T9 T9 L15 IO_L15 IO_T12
IO_T10 IO_B1_T9 IO_B2_L15 IO_L16 IO_R11 SVDD_EN 34 CPLD_TDI 7 8
T10 L16 C781 C782 C783 C784 C785 C786 C787 C788 R472 10K
IO_T11 IO_B1_T10 IO_B2_L16 IO_M13 XVDD_EN 34 9 10
T11 M13
IO_T12 T12 IO_B1_T11 IO_B2_M13 M14 IO_M14 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF SW3 HDR_2X5
IO_T13 T13 IO_B1_T12 IO_B2_M14 M15 IO_M15
IO_T15 IO_B1_T13 IO_B2_M15 IO_M16 IFC_WE_N ON
T15 M16 cfg_eng_use0 1 16 R473 4.7K
D
IO_B1_T15 IO_B2_M16 N13 IO_N13 1V8_SLP 1V8 cfg_eng_use1 IFC_OE_N 2 1 16 15 R474 4.7K D
IO_B2_N13 N14 IO_N14 cfg_eng_use2 IFC_WP_N 3 2 15 14 R475 4.7K
IO_B2_N14 N15 IO_N15 R476 10K BOOT_FLASH_SEL 4 3 14 13 R477 1K
IO_B2_N15 N16 IO_N16 R478 10K CFG_VBANK0 5 4 13 12 R479 1K
IO_B2_N16 P14 IO_P14 C789 C790 C791 C792 C793 C794 C795 C796 R480 10K CFG_VBANK1 6 5 12 11 R481 1K
IO_B2_P14 P15 IO_P15 R482 10K CFG_VBANK2 7 6 11 10 R483 1K Title
IO_B2_P15 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF TEST_SEL_N 8 7 10 9 T104XRDB
8 9
EPM570GF256 Size Document Number Design Engineer Rev
SWITCH_DIP_8 B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 29 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM CLOCK GENERATORs

X1

1 3 R484 33
A 29,31 SINGLE_CLK_EN_N OE OUT SYS_REFCLK 7 A
1V8_SLP
FB37 C797
1V8_OSC_SYS 4 2 DNP R486
R485 BLM18BD601SN1 VDD GND 10pF DNP
C798 C799 C800 C801 1K
4.7K 100MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF

X2

1 3 R487 33
OE OUT DDR_REFCLK 7
1V8
FB38 C802
1V8_OSC_DDR 4 2 DNP R488
BLM18BD601SN1 VDD GND 10pF DNP
C803 C804 C805 C806 1K
66.66MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF

X3

1 3 R489 33
B OE OUT USB_REFCLK 10 B
1V8_SLP
FB39 C807
1V8_OSC_USB 4 2 DNP R490
BLM18BD601SN1 VDD GND 10pF DNP
C808 C809 C810 C811 1K
24MHz,+/-50ppm
0.1uF 0.01uF 1uF 0.1uF

X4

R491 1K 1 3 R492 33
OE OUT CPLD_REFCLK 29
3V3_SLP
FB40
3V3_OSC_CPLD 4 2
BLM18BD601SN1 VDD GND
C812 C813 C814 C815
32.768KHz
0.1uF 0.01uF 1uF 0.1uF

C U58 C

14 4
XTAL_IN Q0 QSG1_REFCLK_N 24
13 5
XTAL_OUT Q0 QSG1_REFCLK_P 24
Y7
16 2
TEST_CLK Q1 SD_REFCLK2_P 8
1 3 1
Q1 SD_REFCLK2_N 8
R493 1K 10
C816 C817 3V3 12 F_SEL0 23
25MHz 125MHz F_SEL1 Q2 24
2

4.7pF 4.7pF 17 Q2
7 XTAL_SEL 21
PLL_SEL Q3 QSG2_REFCLK_N 25
C818 C819 20
Q3 QSG2_REFCLK_P 25
6
0.1uF 0.1uF MR
11 R708 R709 R494 R495 R496 R497
3V3 18 VCC
FB41 VCC 150 150 150 150 150 150
3V3O_843004 3 8
BLM18BD601SN1 22 VCCO NC
C820 C821 VCCO 15
9 GND 19
0.1uF 0.1uF VCCA GND

D 3V3 ICS843004-01 D

R498 10 3V3A_843004

C822 C823
Title
10uF 0.01uF T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 30 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM CLOCK GENERATORs (cont.)

A A

I2C ADDR = 0x6A

1V8_SLP

U79 Integrated output terminations providing Zo=100


29 SD_REFCLK_EN_N
R499 49.9
29,30 SINGLE_CLK_EN_N
2 14 R500 0 DNP 1%
X1_25 DIF0 PEX_REFCLK_P 27
3 15 R501 0
X2 DIF0 PEX_REFCLK_N 27
Y8 R502 49.9 R503 49.9
13 18 R511 0 DNP 1% DNP 1%
OE0 DIF1 AURORA_REFCLK_P 28
1 3 21 19 R504 0
B OE1 DIF1 AURORA_REFCLK_N 28 B
24 R505 49.9 R512 49.9
C824 C825 30 OE2 22 R506 0 DNP 1% DNP 1%
OE3 DIF2 MPEX1_REFCLK_P 27
25MHz R508 1K 35 23 R507 0
MPEX1_REFCLK_N 27
2

2pF 2pF 38 OE4 DIF2 R513 49.9 R509 49.9


DEFAULT NO SPREAD OE5 28 R514 0 DNP 1% DNP 1%
DIF3 MPEX2_REFCLK_P 27
R523 1K DNP 1 29 R515 0
SS_EN_TRI DIF3 MPEX2_REFCLK_N 27
R525 1K 6 R516 49.9 R517 49.9
R528 1K SADR/REF1.8 33 R518 0 DNP 1% DNP 1%
DIF4 SD_REFCLK1_P 8
40 34 R519 0
CKPWRGD_PD DIF4 SD_REFCLK1_N 8
R520 49.9 R521 49.9
9 36 R522 0 DNP 1% DNP 1%
3,7,14,32 I2C1_SCL_SLP SCLK_3.3 DIF5 SYS_REFCLK_P 7
10 37 R524 0
3,7,14,32 I2C1_SDA_SLP SDATA_3.3 DIF5 SYS_REFCLK_N 7
R527 49.9
7 12 DNP 1%
20 NC1 VDDIO 17
25 NC2 VDDIO 27
NC3 VDDIO 32
R532 10 1V8_0641_VDDXTAL 4 VDDIO 39 1V8_SLP
VDDXTAL1.8 VDDIO FB42
C826 C827 26 5 1V8_0641_VDDIO
VDDA1.8 VDDREF1.8 BLM18PG221SN1
10uF 0.01uF 16 C828 C829 C830 C831 C832 C833
1V8_SLP 31 VDD1.8 8
VDD1.8 GNDDIG 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C C
11 41
R533 10 1V8_0641_VDDA VDDDIG1.8 EPAD

C834 C835 IDT9FGV0641

10uF 0.01uF

1V8_SLP 1V8_SLP
FB43
1V8_0641_VDD
BLM18PG221SN1 C839
C836 C837 C838
0.1uF
10uF 0.1uF 0.1uF

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 31 of 38


1 2 3 4 5
1 2 3 4 5

T104X CORE POWER CONVERTOR

A A

COPPER ISLAND
Caution: separate analog and power ground and make connection at GND plane
COPPER PLANE
5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U60 1.0uH(IHLP2525CZER1R0M01): Irms = 11A, Isat = 22A, DCR = 9mohm COPPER PLANE
Fsw = 400KHz VCORE_SLP Q7
13 14 C840 0.33uF IRFH6200 VCORE
10 VIN BOOT L7 Vout = 0.5x(Rtop/Rbot+1) R534 0.001 1
C841 C842 C843 C844 C845 VCC 12 1 4 5 2
R535 124K 1% 15 PHASE 1.0uH 2 3 3
22uF 22uF 22uF 1uF 1uF C846 1uF DNP FF 2 R536 10K R537 1.65K C847 0.1uF C848 C849 C850 C851
R538 10K 16 ISET 1% 1% R540
R539 10K 3 EN Rset = 13(mohm)xIoc/19(uA) C852 470uF 470uF 47uF 47uF DISCHARGE LOAD
3V3_SLP

4
29 VCORE_PGOOD PGOOD R541 R542 1K
29 VCORE_EN 8 510pF
Enable DCM Mode R543 10K DNP 3VCBP 5 10 10 R544
R545 0 1 FB
6 FCCM 7 0
SS NC1 9 R546 R547 R548 C853 0.1uF 12V_SLP
B NC2 B
C854 C855 4 1% 1%
17 GND 11 10K 10K 200 INA_VCORE_P
1uF 0.1uF GND PGND INA_VCORE_N
R549
IR3475
10K
Css(nF) = 22xTss(mS) R550 60.4
12 SENSEVDDC
1%
R551 0
12 SENSEVDD

3
3V3_SLP
3V3_SLP
U61 Q8 C857
5 2 C856 R552 1K 1 IRLML6346
VCC A 29 VDD_EN_N
1 0.1uF
29 SENSEVDD_EN_N OE
3 4 0.1uF

2
GND B R553
I2C ADDR = 0x40 74CBTLV1G125
U62 5~7 ohm on-state switch resistance 10K

5 10 INA_VCORE_P 3V3_SLP
3,7,14,31 I2C1_SCL_SLP SCL VIN+
4
3,7,14,31 I2C1_SDA_SLP SDA
R554 0 2 9 INA_VCORE_N C858
R555 0 1 A0 VIN-
C C
A1 0.1uF
3 8 R556 0
NC VBUS
7 6 3V3_SLP
GND VS

INA220A

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 32 of 38


1 2 3 4 5
1 2 3 4 5

2.2uH(IHLP2525CZER2R2M01): Irms = 8A, Isat = 14A, DCR = 18mohm


3.3uH(IHLP2525CZER3R3M01): Irms = 6A, Isat = 13.5A, DCR = 28mohm
SYSTEM POWER CONVERTORs
4.7uH(IHLP2525CZER4R7M01): Irms = 5.5A, Isat = 10A, DCR = 37mohm
COPPER ISLAND COPPER ISLAND

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U69 COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw)


MAX 10A
U64 COPPER PLANE
SWITCHABLE ALWAYS ON
Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz Rset = 13(mohm)xIoc/19(uA)
13 14 C953 0.33uF 1V0 13 14 C867 0.47uF 1V2_SLP
C954 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C859 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C960 C961 C952 1uF VCC 12 L15 C864 C870 C862 1uF VCC 12 L9
A R611 124K 1% 15 PHASE 2.2uH R558 150K 1% 15 PHASE 2.2uH A
22uF 22uF C957 0.01uF DNP FF 2 R613 10K 1% C964 C967 C968 22uF 22uF C865 4.7uF DNP FF 2 R564 10K 1% C875 C876 C871
R615 10K DNP 16 ISET R616 1.65K 1% R619 R565 10K 16 ISET R566 2.05K 1% R567
EN 3V3_SLP EN
R618 10K 3 C966 0.1uF 1% 47uF 47uF 0.1uF R568 10K 3 C878 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 10K 29 DDR_PGOOD PGOOD 14K
29,33,35 IOPWR_EN
8 C972 510pF 29 DDRPWR_EN 8 C880 560pF
Enable DCM Mode R623 10K DNP 3VCBP 5 Enable DCM Mode R570 10K DNP 3VCBP 5
R625 0 1 FB 1V0 1V0 R572 0 1 FB 1V2_SLP 1V2_SLP
6 FCCM 7 6 FCCM 7
SS NC1 9 R627 SS NC1 9 R574
C974 C975 4 NC2 1% C976 C977 C885 C886 4 NC2 1% C887 C888
17 GND 11 10K 17 GND 11 10K
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.1uF GND PGND 47uF 47uF

IR3473 IR3475

Css(nF) = 22xTss(mS) 1V2 POWER ON LAST Css(nF) = 22xTss(mS)

COPPER ISLAND COPPER ISLAND

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U66 SWITCHABLE COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U65 ALWAYS ON COPPER PLANE
Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz Rset = 24(mohm)xIoc/19(uA)
B B
13 14 C896 0.47uF 1V5 13 14 C890 0.47uF 1V8_SLP
C891 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C892 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C894 C895 C893 1uF VCC 12 L10 C898 C889 C897 1uF VCC 12 L11
R575 187K 1% 15 PHASE 3.3uH R576 226K 1% 15 PHASE 3.3uH
22uF 22uF C899 0.01uF DNP FF 2 R577 10K 1% C903 C904 C905 22uF 22uF C900 0.01uF DNP FF 2 R578 10K 1% C901 C906 C907
R579 10K DNP 16 ISET R580 2.21K 1% R582 R583 10K 16 ISET R584 2.43K 1% R586
R581 10K 3 EN C902 0.1uF 1% 47uF 47uF 0.1uF R585 10K 3 EN C908 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 10K PGOOD 10K
29,33,35 IOPWR_EN
8 C909 560pF 8 C910 620pF
Enable DCM Mode R587 10K DNP 3VCBP 5 Enable DCM Mode R588 10K DNP 3VCBP 5
R589 0 1 FB 1V5 1V5 R590 0 1 FB 1V8_SLP 1V8_SLP
6 FCCM 7 6 FCCM 7
SS NC1 9 R591 SS NC1 9 R592
C911 C912 4 NC2 1% C913 C914 C915 C916 4 NC2 1% C917 C918
17 GND 11 4.99K 17 GND 11 3.83K
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.01uF GND PGND 47uF 47uF

IR3473 IR3473

Css(nF) = 22xTss(mS) Css(nF) = 22xTss(mS)

C COPPER ISLAND COPPER ISLAND C

5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw) U67 COPPER PLANE 5V0_SLP Rff(kohm) = Vout/(1Vx20pFxFsw)


MAX 10A
U68 COPPER PLANE
Fsw = 400KHz
SWITCHABLE
Rset = 24(mohm)xIoc/19(uA) Fsw = 400KHz
ALWAYS ON
Rset = 13(mohm)xIoc/19(uA)
13 14 C919 1uF 2V5_SLP 13 14 C930 1uF 3V3_SLP
C920 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1) C921 1uF 10 VIN BOOT Vout = 0.5x(Rtop/Rbot+1)
C922 C923 C925 1uF VCC 12 L12 C924 C927 C926 1uF VCC 12 L13
R593 309K 1% 15 PHASE 4.7uH R594 412K 1% 15 PHASE 2.2uH
22uF 22uF C928 0.01uF DNP FF 2 R595 10K 1% C931 C932 C934 22uF 22uF C929 0.01uF DNP FF 2 R603 10K 1% C933 C935 C936
R596 10K DNP 16 ISET R597 2.55K 1% R602 R598 10K 16 ISET R599 2.32K 1% R600
R601 10K 3 EN C937 0.1uF 1% 47uF 47uF 0.1uF R604 10K 3 EN C938 0.1uF 1% 47uF 47uF 0.1uF
PGOOD 3V3_SLP PGOOD
10K 10K
29 3V3_PGOOD
8 C939 680pF 8 C940 680pF
Enable DCM Mode R605 10K DNP 3VCBP 5 Enable DCM Mode R606 10K DNP 3VCBP 5
R607 0 1 FB 2V5_SLP 2V5_SLP R608 0 1 FB 3V3_SLP 3V3_SLP 3V3_SLP
6 FCCM 7 5V0_SLP 5V0_SLP 6 FCCM 7
SS NC1 9 R609 SS NC1 9 R610
C941 C942 4 NC2 1% C943 C944 C945 C946 4 NC2 1% C947 C950 C951
17 GND 11 2.49K C948 C949 17 GND 11 1.78K
1uF 0.01uF GND PGND 47uF 47uF 1uF 0.01uF GND PGND 47uF 47uF 47uF
22uF 22uF
IR3473 IR3475

Css(nF) = 22xTss(mS) Css(nF) = 22xTss(mS)


D D

Caution: separate analog and power ground and make connection at GND plane
Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 33 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM POWER CONVERTORs (cont.)

COPPER ISLAND
A A
1V2_SLP 3V3_SLP U72 MVREF COPPER ISLAND

2 3 VTT
VLDOIN VO
C991 C992 10 5 R631 10
R636 1 VIN VOSNS 6
10uF 10uF 1% REFIN REFOUT
1K C995 7 9 C996 C997 C998 C999
EN PGOOD
4.7uF 4 0.1uF 1uF 22uF 22uF
8 PGND 11
GND PAD 3V3_SLP
R640 C1004
1% TPS51200 R641 100K
1K 1000pF

3V3_SLP

R642 10K
29 VTT_EN

B B

1V8_SLP 3V3_SLP U73 1V0S


Vout = 0.7x(Rtop/Rbot+1) 3V3_SLP U74 2V5_VPP
1 7
3V3_SLP 2 IN OUT 8 1 2
IN OUT IN OUT
4 6 R643 4.32K C1005 C1006 5 4 R644 39.2K 1% C1007 C1008
BIAS FB/ADJ 1% EN NR/FB
R645 C1009 C1010 5 3 R646 C1012 C1013 10uF 0.1uF 3 6 C1011 1500pF 10uF 0.1uF
EN GND 9 GND GND(TAB)
10K 1uF 1uF EPAD 10K 10uF 0.1uF
1% TPS73701_SOT223 R647
MIC47100YMME 1%
3V3_SLP 36.5K
29 SVDD_EN
SVDD power on with VDD R648 10K
29 VPP_EN

1V8_SLP 3V3_SLP U75 1V35X


C Vout = 0.7x(Rtop/Rbot+1) C
1 7 2V5_VPP VPP
3V3_SLP 2 IN OUT 8 C1014
IN OUT
4 6 R649 9.31K
BIAS FB/ADJ 1% NFM21PC225B0J3 C1019 C1020 C1021 C1022 C1023 C1024
R650 C1015 C1016 5 3 R651 C1017 C1018
EN GND 9 47uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10K 1uF 1uF EPAD 10K 10uF 0.1uF
1%
MIC47100YMME
29 XVDD_EN
XVDD power on with GVDD

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 34 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM POWER SWITCHs

Q9 Q10 Q11
5V0_SLP IRFHM4226 5V0 1V2_SLP IRFH6200 1V2 1V8_SLP IRFHM4226 1V8
1 1 1
A 5 2 5 2 5 2 A
3 3 3

DISCHARGE LOAD R652 DISCHARGE LOAD R653 DISCHARGE LOAD R654


12V_SLP 4 12V_SLP 12V_SLP

4
R655 100 1K R656 100 1K R657 100 1K
R658 10K R659 10K R660 10K
C1025 0.1uF C1026 0.1uF C1027 0.1uF Q30
2V5_SLP IRFHM4226 2V5

3
1
5 2
Q12 Q13 Q14 3
R661 1K 1 IRLML6346 R662 1K 1 IRLML6346 R663 1K 1 IRLML6346
29,35 IOPWR_EN_N 29 GVDD_EN_N 29,35 IOPWR_EN_N
R664 10K R665 10K R666 10K DISCHARGE LOAD R719
12V_SLP
2

4
R720 100 1K
R721 10K
C1069 0.1uF

3
Q15
3V3_SLP IRFH6200 3V3 Q31
1 R722 1K 1 IRLML6346
29,35 IOPWR_EN_N
5 2 R723 10K
B B
3

2
DISCHARGE LOAD R667
12V_SLP
4

R668 100 1K
R669 10K Q16 Q17 Q19 Q20
C1028 0.1uF 1V8 IRLML2030 IRLML2030 EVDD IRLML2030 IRLML2030 3V3
3

2 3 3 2 2 3 3 2

Q18
R670 1K 1 IRLML6346 DISCHARGE LOAD R672
29,35 IOPWR_EN_N
R671 10K

1
1K
2

12V_SLP 12V_SLP
R673 100 R674 100
R675 10K R676 10K
C1029 0.1uF C1030 0.1uF

3
12V_SLP Q23 12V Q21 Q22 EVDD
IRF9321 R677 1K 1 IRLML6346 1 IRLML6346
29 EVDD_SEL
C 1 5 DISCHARGE LOAD R678 10K C
2 6

2
3 7 C1031 C1032 C1033
8 R679
4.7uF 0.1uF 0.1uF
4.7K
4

R680 100
R681 10K
C1034 0.1uF
DDR_MCKE0 3
3

3V3_SLP

3
R682 10K Q24
R683 1K 1 IRLML6346 Q25
29,33 IOPWR_EN
R684 1K 1 IRLML6346
29 CKE_ISO_EN
DDR_MCKE1 3
2

3
Q26
R685 10K 1 IRLML6346

2
D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 35 of 38


1 2 3 4 5
1 2 3 4 5

SYSTEM POWER INPUT

12V 12V
CHASSIS FAN HEADER
LED LABEL = SYS_FAN
R686 0 J32
A 3V3_SLP 3V3_SLP C1035 1 A
F2 500mA 2
10uF DNP 3

2
D5 D6 CON_3PIN
GRN GRN
12V 12V
LABEL = SYS_FAN
R687 0 J33

1
R688 510 C1036 1
29 LED_STATUS
F3 500mA 2
R689 10uF DNP 3

510 CON_3PIN

12V 12V
LABEL = SYS_FAN
R690 0 J34
12V_SLP C1037 1
F4 500mA 2
10uF DNP 3

R691 12V_SLP CON_3PIN


B B
10K 12V 12V

2
CPU FAN HEADER LABEL = SYS_FAN
R692 1K 1 R693 0 J35
Q27 C1038 1
3

TP0610K LABEL = CPU_FAN F5 500mA 2


J36 10uF DNP 3
Q28 3

3
R694 1K 1 IRLML6346 3V3_SLP 2 CON_3PIN
29 FAN_PWM
1
C1039 C1040
2

CON_3PIN
R695 10uF 0.1uF

10K 12V_SLP 5V0_SLP

R696 10K
ATX POWER INPUT CONNECTOR
29 FAN_TACH
C1041 C1042 C1043 C1044 C1045 5V0_SLP J37 5V0_SLP

100uF 10uF 330uF 330uF 10uF 5V MAX: 10A 1 11


25V 16V 16V 12V MAX: 5A +3.3VDC +3.3VDC
2 12
+3.3VDC -12VDC
C 3V3_SLP 3 13 C
COM COM
5V0_SLP 4 14 PWR_EN_N
+5VDC PS_ON
LOCAL RESET 5 15
R697 3V3_SLP U76
LABEL = RESET COM COM
SW4 4.7K 4 R698 6 16
VCC +5VDC COM
1 2 R699 100 3 2 4.7K 12V_SLP 5V0_SB 7 17
MR RESET PWR_RST_N 29 COM COM
3 4
C1046 1 8 18
SWITCH GND R700 5V0_SB PWR_OK -5VDC
0.1uF REMOTE POWER 9 19
J38 MIC811 4.7K R701 +5VSB +5VDC
1 LABEL = POWER 10 20
LABEL = RESET 2 3V3_SLP J39 R702 3.74K +12VDC +5VDC
1 1%
HDR_1X2 2 4.7K ATX_PWR_CONN_20PIN
29 PWR_GOOD
C1047
REMOTE RESET 5V0_SB HDR_1X2 PWR_EN_N
0.1uF U77 R704 C1048
3
R703 100
PWR SWITCH 5V0_SB 2 5 R705 1K 1 Q29 4.7K 0.1uF
D7 D Q MMBT4401
D LABEL = POWER U78 1 3 5V0_SB D
2

SW5 1 5 CLK Q
RB521 NC VCC 4 7 8 5V0_SB 5V0_SB 5V0_SB
1 2 R706 100K 2 O 3 R707 100K 6 PRE VCC 4
3 4 I GND CLR GND
C1049 74AHC1G14 C1050 C1051 C1052 C1053 Title
SWITCH 10mS Debounce Default Power Off 74LVC2G74 T104XRDB
0.1uF 0.1uF 0.1uF 0.1uF 10uF
Size Document Number Design Engineer Rev
B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 36 of 38


1 2 3 4 5
1 2 3 4 5

MECHANICALs

A A

Fiducial Marks Layer Detail


Top 1.5OZ
Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8
L2GND 1OZ

L3SIG 1OZ

L4PWR 1OZ 2.0mm


+/- 10%
Mouting Holes L5PWR 1OZ

L6SIG 1OZ
Z9 Z10 Z11 Z12 Z13 Z14
L7GND 1OZ

Bottom 1.5OZ

B B

Z15 Z16

C C

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 37 of 38


1 2 3 4 5
1 2 3 4 5

CHANGE LIST
2014/10/28
1. Change SD_REFCLK2 to 125MHz for 2.5G SGMII
2. Add RGMII RXCLK 500ps PCB delay line for new T1040 chip requirement
3. Add MDIO mux/demux and voltage level translator
A A
2014/11/12
1. Delete AQR105 and change to RTL8211DN
2. Change profibus DB9 to 1X5 header
3. Remove miniPCIe mounting stubs

2014/12/23
1. Add 2 mounting holes for miniPCIe connectors

B B

C C

D D

Title
T104XRDB

Size Document Number Design Engineer Rev


B <Doc> MICETEK A

Date: Monday, December 22, 2014 Sheet 38 of 38


1 2 3 4 5

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