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DRAM Refresh PDF
DRAM Refresh PDF
DRAM Refresh PDF
(4K) Burst
Refresh
TN-04-30
DT30.p65 – Rev. 2/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
RAS#-ONLY REFRESH
To perform a RAS#-ONLY REFRESH, a row address is counter. The user does not have to supply or keep track
put on the address lines and then RAS# is dropped. of row addresses. A drawing of one CBR REFRESH cycle
When RAS# falls, that row will be refreshed and as long is shown in Figure 3. CAS# must be held LOW before
as CAS# is held HIGH, the DQs will remain open. (See and after RAS# falls to meet tCSR and tCHR. Figure 4
Figure 2.) shows three CBR REFRESH cycles. In this drawing, CAS#
It is the DRAM controller’s function to provide the stays LOW and only RAS# toggles. Every time RAS# falls
addresses to be refreshed and make sure that all rows are a refresh cycle is performed. CAS# may be toggled each
being refreshed in the appropriate amount of time. The time, but it’s not necessary.
row order of refreshing does not matter; what is impor-
tant is that each row be refreshed in the specified CBR POWER SAVINGS
amount of time. Since CBR REFRESH uses the internal counter and
not an external address, the address buffers are pow-
CAS#-BEFORE-RAS# REFRESH ered-down. For power-sensitive applications, this can
CAS#-BEFORE-RAS# REFRESH, also known as CBR be a benefit because there is no additional current used
REFRESH, is a frequently used method of refresh be- in switching address lines on a bus, nor will the DRAMs
cause it is easy to use and offers the advantage of a pull extra power if the address voltage is at an interme-
power savings. A CBR REFRESH cycle is performed by diate state.
dropping CAS# and then dropping RAS#. One refresh
cycle will be performed each time RAS# falls. WE# must CBR REFRESH IS EASY TO USE
be held HIGH while RAS# falls. The DQs will remain Since CBR REFRESH uses its own internal counter,
open during the cycle. there is not a concern about the controller having to
Here’s how CBR REFRESH works. The die contains supply the refresh addresses. Virtually all DRAMs sup-
an internal counter which is initialized to a random port CBR REFRESH and the 15.6µs refresh rate, so you
count when the device is powered up. Each time a CBR can design for CBR REFRESH at the distributed rate of
REFRESH is performed, the device refreshes a row based 15.6µs and plug in many different DRAMs without
on the counter, and then the counter is incremented. having to worry about refresh. For example, the 4 Meg
When CBR REFRESH is performed again, the next row x 4 comes in two versions:
is refreshed and the counter is incremented. The counter • 2,048 cycles in 32ms
will automatically wrap and continue when it reaches • 4,096 cycles in 64ms
the end of its count. There is no way to reset the
tRC
tRAS tRP
V IH
RAS# V IL
tCRP tRPC
V IH
CASL# V IL
and CASH#
tASR tRAH
V IH
ADDR V IL ROW
V
Q V OH OPEN
OL
DON’T CARE
UNDEFINED
Figure 2
RAS#-Only Refresh
TN-04-30
DT30.p65 – Rev. 2/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
If CBR REFRESH is used, simply maintain the stan- was LOW before RAS# went LOW, the part will execute
dard 15.6µs refresh rate. If RAS#-ONLY REFRESH is a CBR REFRESH. In a READ cycle the output data will
used, addresses must be supplied as follows: remain valid during the CBR REFRESH. The refresh is
• A0-A10 for the 2,048 cycle refresh not “hidden” in the sense that you can hide the time it
• A0-A11 for the 4,096 cycle refresh takes to refresh; instead, it is hidden in the sense that
data-out will stay on the lines while performing the
HIDDEN REFRESH function. READ and HIDDEN REFRESH cycles will take
In HIDDEN REFRESH, the user does a READ or the same amount of time: tRC. The two cycles together
WRITE cycle and then, leaving CAS# LOW, brings RAS# take 2 x tRC. If we were to do a READ and then follow
HIGH (for minimum of tRP) and then LOW. Since CAS# it with a standard CBR REFRESH (instead of a HIDDEN
tRP tRAS
V IH
RAS# V IL
tRPC
V IH
CAS# V IL
DQ OPEN
tWRP tWRH
V IH
WE# V IL
Figure 3
One CAS#-Before-RAS# Refresh Cycle
V IH
RAS# V IL
tRPC
tCPN tCSR
V IH
CAS# V IL
DQ OPEN
V IH
WE# V IL
DON’T CARE
UNDEFINED
Figure 4
Three CAS#-Before-RAS# Refresh Cycles
TN-04-30
DT30.p65 – Rev. 2/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
REFRESH), this would take the same amount of time: 2 SUMMARY
x tRC. Three different cycles exist to perform refresh on a
Figure 5 shows a READ followed by a HIDDEN standard DRAM: RAS#-ONLY REFRESH, CBR REFRESH,
REFRESH. Figure 6 shows a READ followed by a stan- and HIDDEN REFRESH. Each cycle can be used in a
dard CBR REFRESH. The only difference between the burst or distributed method, whichever best fits the
two is that data-out is valid during the HIDDEN RE- designer’s needs. It is strongly urged that CBR REFRESH
FRESH. be used to refresh the DRAM. Future DRAMs will most
likely require CBR REFRESH only.
(READ) (REFRESH)
tRAS tRP tRAS tRP
V IH
RAS# V IL
tCRP tRCD tRSH
V IH
CAS# V IL
V IH
ADDR V IL ROW COLUMN
tAA
tRAC
tCAC
tOFF
tCLZ
V IH
WE# V IL
V
DQx V IOH OPEN VALID DATA OPEN
IOL
tOE tOD
V IH tORD
OE# V IL
Figure 5
READ Cycle Followed by Hidden Refresh
(READ) (REFRESH)
tRAS tRP tRAS tRP
V IH
RAS# V IL
tCRP t RCD tRSH
tCSR tCHR
V IH
CAS# V IL
V IH
ADDR V IL ROW COLUMN
tAA
tRAC
tCAC
tCLZ
V IH
WE# V IL tOFF
V IOH
DQx V IOL OPEN OPEN
V IH tORD
OE# V IL
DON’T CARE
UNDEFINED
Figure 6
READ Cycle Followed by CBR REFRESH
Micron is a registered trademark of Micron Technology, Inc.
TN-04-30
DT30.p65 – Rev. 2/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.