VLSI Architecture- MEL G642

Lab Assignment 4
Lavish Patidar
2019H1230528G

Design and implementation of 16*9 Sequential multiplier with

RTL 2 architecture.
1. Architecture of Multiplier
2. Synthesized design of Multiplier:

Fig. 1: Synthesized Top module

Fig. 2: Synthesized Datapath

 Fig. 3: Synthesized Control Path

3. Verilog Code for Multiplier RTL-2 Architecture:

3.1 Verilog Code for Multiplier:
//Top Module for multiplier
`timescale 1ns / 1ps

module Mul_Top(
input [15:0] in1,
input [8:0] in2,
output [24:0] out,
input clock,
input reset
);

wire clr,load_accum,load_Mx,load_My,shift_My;//shift_in;

datapath
DP1(.reset(reset),.clock(clock),.data_in1(in1),.data_in2(in2),.clr(clr),.load_accum(load_accum),.loa
d_Mx(load_Mx),.load_My(load_My),.shift_My(shift_My),.Result_MSB(out[24:9]),.Result_LSB(out[8:
0]));
 controlpath
CP1(.reset(reset),.clock(clock),.clr(clr),.load_accum(load_accum),.load_Mx(load_Mx),.load_My(loa
d_My),.shift_My(shift_My));

endmodule

///////////////////////////////////////////Datapath Module///////////////////////////////////////////////////////////////////////////////

module datapath(
input clock,
input [15:0] data_in1,
input [8:0] data_in2,
input clr,
input load_accum,
input load_Mx,
input load_My,
input shift_My,
input reset,
output [15:0] Result_MSB,
output [8:0] Result_LSB
);

wire [15:0] Mx,PP_out;

wire [16:0] sum;
wire My;

PIPO Mx_Reg(.reset(reset),.clock(clock),.load_Mx(load_Mx),.data_in(data_in1),.data_out(Mx));
PISO My_Reg
(.reset(reset),.data_in(data_in2),.data_serial_in(sum[0]),.data_serial_out(My),.data_parallel_out(R
esult_LSB),.clock(clock),.load_My(load_My),.shift_My(shift_My));
PP_Gen PP (.in1(Mx),.in2(My),.PP_out(PP_out));
Adder Add1(.in1(PP_out),.in2(Result_MSB),.sum(sum));
Accumulator
Acc1(.clock(clock),.clr(clr),.load_accum(load_accum),.data_in(sum),.data_out(Result_MSB));

endmodule

///////////////////////////////////////////////PIPO Module///////////////////////////////////////////////////////////////////////////////
module PIPO(input reset, input clock,input load_Mx,input [15:0] data_in,output reg [15:0]
data_out);
reg [15:0] temp;

always @ (posedge clock)

if (reset)
begin
data_out=0;
temp=0;
end
else

if (load_Mx)
temp=data_in;
else
data_out=temp;

endmodule

/////////////////////////////////////////////////PISO Module///////////////////////////////////////////////////////////////////////////////

module PISO(input reset,input [8:0] data_in,input data_serial_in,output reg

data_serial_out=0,output reg [8:0] data_parallel_out=0,input clock,input load_My,input shift_My);
reg temp;
reg [8:0] temp1;
always @ (posedge clock)
if (reset)
begin
temp=0;
temp1=0;
data_serial_out=0;
data_parallel_out=0;
end
else
if (load_My)
temp1=data_in;
else if (shift_My)
begin
temp=temp1[0];
temp1={data_serial_in,temp1[8:1]};
end
else
begin
data_serial_out=temp;
data_parallel_out=temp1;
end
endmodule

////////////////////////////////////////////////PP Generator
Module///////////////////////////////////////////////////////////////////////////////

module PP_Gen(
input [15:0] in1,
input in2,
output reg [15:0] PP_out=0
);

always @*
PP_out=in1 & {16{in2}};
endmodule

/////////////////////////////////////////////////Adder Module///////////////////////////////////////////////////////////////////////////////

module Adder(
input [15:0] in1,
input [15:0] in2,
output reg [16:0] sum=0
//output reg carry=0
//output reg carry=0
 );

always @*
sum<=in1+in2;
endmodule

////////////////////////////////////////////////Accumulator
Module///////////////////////////////////////////////////////////////////////////////

module Accumulator(input clock,input clr,input load_accum,input [16:0] data_in,output reg [15:0]

data_out=0);
reg [15:0] temp;
always @(posedge clock)
begin
if (clr)
begin
temp=0;
data_out=0;
end
else if (load_accum)
begin
temp=data_in>>1;
//data_out={serial_in,data_in[15:1]};
end
else
data_out=temp;
end
endmodule

//////////////////////////////////////////////Controlpath Module///////////////////////////////////////////////////////////////////////////////

module controlpath(input reset,input clock,output reg clr,output reg load_accum,output reg

load_Mx,output reg load_My,output reg shift_My);

parameter
S0=4'd0,S1=4'd1,S2=4'd2,S3=4'd3,S4=4'd4,S5=4'd5,S6=4'd6,S7=4'd7,S8=4'd8,S9=4'd9,S10=4'd1
0,S11=4'd11;
reg [3:0] PS,NS;
always @(posedge clock)
begin
if (reset)
begin clr=1; load_Mx=0;load_My=0; load_accum=0; shift_My=0; PS=S0; end
else
PS=NS;
end

always @(PS)
begin
case(PS)
S0: begin clr=1; load_Mx=1;load_My=1; load_accum=0; shift_My=0; NS=S1; end
S1: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S2; end
S2: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S3; end
S3: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S4; end
S4: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S5; end
S5: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S6; end
 S6: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S7; end
S7: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S8; end
S8: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S9; end
S9: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S10; end
S10: begin clr=0; load_Mx=0;load_My=0; load_accum=1; shift_My=1; NS=S0; end
default: begin clr=1; load_Mx=0;load_My=0; load_accum=0; shift_My=0; NS=S0; end
endcase
end

endmodule

3.2 Simulation Result:

Results:
The multiplier has been tested by providing the following inputs:
In1 [15:0] = 16’b1010101010101010 (decimal eq. =43690 )
In2 [8:0] = 9’b 101011010 (decimal eq. = 346)
The simulation result of multiplier is out [24:0] = 25’b 0111001101010100_111000100 (16 and 9
bit combination) (decimal eq. = 15116740)