5 4 3 2 1

DEVKIT-MPC5744P
D Table Of Contents: Revision Information D

Rev Date Designer Comments

Block Diagram Sheet 2 X1 6 July 2016 Jun Qiao Initial
X2 12 July 2016 Jun Qiao Update MCU decoupling, add boot section
Board Power Sheet 3 X3 19 July 2016 Jun Qiao Update MCU decoupling, update notes, rename nets
A 22 July 2016 Jun Qiao Update J13 setting, update power to RV1, update notes
MCU Power Sheet 4 A1 26 Aug 2016 Jun Qiao Update FRDM+ connection compatible to DEVKIT-MOTORGF
A2 5 Sept 2016 Jun Qiao Add test points
MCU Pins Sheet 5 A3 7 Sept 2016 Jun Qiao Change U15 to NX5P2190UKZ, change R57 to 100K
A4 9 Sept 2016 Jun Qiao Remove D8, add J39
Boot, Reset & JTAG Sheet 6 A5 13 Sept 2016 Jun Qiao Set power net 12V_IN at U1 pin 1, add R88
A6 20 Sept 2016 Jun Qiao Change R56 from 10K to 20K, and connected to P3V3_SDA
Flexray, CAN, LIN Sheet 7 A7 23 Sept 2016 Jun Qiao Change U15 to MIC2005-0.8YM6, remove R57, change R56 to 10K, add C87.
B 28 Sept 2016 Jun Qiao Release
OpenSDA Sheet 8
User Peripherals Sheet 9
C
FRDM+ Connectors Sheet 10 C

Notes:
- All components and board processes are to be ROHS compliant
- All capacitors are 10% tolerance unless otherwise stated
- All resistors are 5% tolerance unless otherwise stated
- All zero ohm links are 0603
- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2
2 Pin jumpers generally have the "source" on pin 1
- All switches are denoted SWx
- All test points (SMT wire loop style) are denoted TPx
- Test point Vias (just through hole pads) are denoted TPVx
B B
3 Different test points used in design:
TPVx - Through Hole Pad small

TPHx - Through Hile Pad Large (for standard 0.1" header).

Also used on IO Matrix (IOMx)
TPX - Surface Mount Wire Loop

User notes are given throughtout the schematics.

Specific PCB LAYOUT notes are detailed in ITALICS

Caution:
These schematics are provided for reference purposes only. As such, NXP
A
does not make any warranty, implied or otherwise, as to the suitability of A

circuit design or component selection (type or value) used in these Automotive Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
schematics for hardware design using the NXP Calypso family of This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

Microprocessors. Customers using any part of these schematics as a basis Designer: Drawing Title:
ICAP Classification: CP: IUO: X PUBI:

for hardware design, do so at their own risk and Freescale does not Jun Qiao DEVKIT-MPC5744P
Drawn by: Page Title:
assume any liability for such a hardware design. Jun Qiao Index, Rev, Notes
Approved: Size Document Number Rev
Pesses Philip C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 1 of 10
5 4 3 2 1
 5 4 3 2 1

Block Diagram

D D

C C

B B

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
DEVKIT-MPC5744P
Page Title:
Block Diagram
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 2 of 10
5 4 3 2 1
 5 4 3 2 1

Board Power

D D

C C

5V Switching Regulator 3.3V Switching Regulator

Layout note: Input Voltage 12V, Output 5V at 1800mA Input Voltage 5V, Output 3.3V at 1600mA
ADD Graphical silk
5V0_SW 5V0_SR TP1 3V3_SR 3V3_SR TP2
+ - R1 R2 SILK = 5V0_SR R6 R7 SILK = 3V3_SR
1.0K 3.09K 1 1.0K 1.69K 1
1% 1% 5V0_SR 1% 1%
12V_IN
P1 GND U1 D3 GND U2
CON PWR 3 R3 R8
D1
1 A C 1 3 A C 1 3 270
560
3 VIN FB VIN FB L2
2 PMEG4030ER L1 47uH 4.7uH
A

A
C1 4 2 1 2 C3 PMEG4030ER 4 2 1 2
SD OUT SD OUT
GND1
GND2
GND3
GND4

GND1
GND2
GND3
GND4
22uF DS1 22uF DS2
C
SH1
SH2

B B
GND 25V GREEN 10V C4 GREEN

C
D2 C2 SILK = 5V_OK 20% 22uF SILK = 3V3_OK
GND AP1509-SG-13 SBR3U30P1 22uF AP1509-SG-13 D4 10V
5
6
7
8

5
6
7
8
10V SBR3U30P1 20%
C

C
GND 20%
A

A
GND GND GND GND
GND GND GND GND
GND

Layout note: follow IC datasheet recommandations for Layout note: follow IC datasheet recommandations for
PCB layout and thermal dissipation PCB layout and thermal dissipation

Board supply selection 3.3V & 5V Power Decoupling Test and reference points
TP3 TP4
SILK = GND SILK = GND
Select between USB and external 12V
3V3_SR 5V0_SR

1
5V0_SW 5V0_SR 5V_TGT_OUT

C60 C61 C62 C63 C64 C65 GND

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1
2
3

Layout note:
A GND Test Points, Top Side A
GND GND
J13
HDR_1X3
Layout note:
1-2 -> external 12V Decoupling distributed uniformly
2-3 -> USB/UART connector
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
DEVKIT-MPC5744P
Page Title:
Board Power
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 3 of 10
5 4 3 2 1
 5 4 3 2 1

MCU Power
MCU Power Decoupling Default Configuration:
- MCU supply voltages (VDD_HV_IO, VDD_HV_PMU, VDD_HV_OSC, VDD_HV_ADV, VDD_HV_FLA) are set to 3.3V
- MCU core voltage (VDD_LV_CORE, VDD_LV_PLL) are set to 1.25V
- MCU analog reference voltage (VDD_HV_AREx) are set 3.3V default. Could be 5V, or from external J2 pin15 (3.15V~5.5V).

D VDD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages and need to be supplied by the same voltage source. D

J14 J15
HDR 1X2 HDR 1X2
3V3_SR
VDD_HV_PMU Q1 VDD_LV VDD_LV_CORE
NJD2873T4

1
2

1
2
4 3

short in bottom layer short in bottom layer

C86 C5 C6 C7 C66 C67 C8 C9 C10 C11 C12 C13

1
10uF 10uF 0.1UF R9 0 4.7UF 4.7UF 4.7UF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF
[5] BCTRL
20% 20%

C14

GND 0.047uF
DNP GND
Layout notes: VDD_LV_CORE (1.25V) Decoupling.
Layout notes: VDD_HV_PMU (3.3V) Decoupling. GND Place one of the 0.047uF caps close to each VDD_LV_CORx pin.
Place 0.01uF caps close to VDD_HV_PMU pin. Place the 4.7uF caps close to the jumper.
Place the 10uF caps close to the jumper.
L6 VDD_LV_PLL

J16 1 2
HDR 1X2
330 OHM C15
VDD_HV_IO Layout notes: VDD_LV_PLL (1.25V) Decoupling.
0.047uF Place the 0.047uF caps close to VDD_LV_PLL pin.
1
2

short in bottom layer GND

C C73 C16 C17 C18 C19 C20 C74 C75 C76 C77 C

10uF 10uF 0.047uF 0.047uF 0.047uF 0.047uF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20%

GND

Layout notes: VDD_HV_IO (3.3V) Decoupling.

Place one of the 0.047uF and 0.01uF caps close to each VDD_HV_IO pin. J17
Place the 10uF caps close to the jumper. HDR 1X2

VDD_HV_ADV

1
2
J18 short in bottom layer
C21 C22 C72
HDR 1X2
1uF 0.047uF 0.01UF
VDD_HV_FLA
1
2

short in bottom layer GND

C23 C24
Layout notes: VDD_HV_ADV (3.3V) Decoupling.
Layout notes: VDD_HV_FLA (3.3V) Decoupling. Place the 0.047uF and 0.01uF caps close to VDD_HV_ADV pin.
0.1UF 0.01UF Place the 0.01uF caps close to VDD_HV_FLA pin. J7
HDR 1X2 Place the 1uF caps close to the jumper.
Place the 0.1uF caps close to the jumper.
VDD_AREF VDD_HV_ADRE1

1
2
GND
1-2 -> 3.3V
B
2-3 -> 5V short in bottom layer B
C25 C26 C70
3V3_SR
1uF 0.047uF 0.01UF
J19
1 C59
2
3 0.1UF
5V0_SR GND
Layout notes: VDD_HV_ARE1 (3.3V) Decoupling.
VDD_AREF: ADC high reference voltage Place the 0.047uF and 0.01uF caps close to VDD_HV_ARE1 pin.
J8 HDR_1X3 J9
HDR 1X2
3.3V set jumper as 1-2 GND
HDR 1X2 Place the 1uF caps close to the jumper.
5V set jumper as 2-3
VDD_HV_OSC from other boards set no jumper (and populate R81) VDD_HV_ADRE0
1
2

1
2
short in bottom layer short in bottom layer
C27 C28 C29 C30 C71
Layout notes: VDD_HV_OSC (3.3V) Decoupling.
0.1UF 0.01UF Place the 0.01uF caps close to VDD_HV_OSC pin. 1uF 0.047uF 0.01UF
Place the 0.1uF caps close to the jumper.

GND
GND
Layout notes: VDD_HV_ARE0 (3.3V) Decoupling.
Place the 0.047uF and 0.01uF caps close to VDD_HV_ARE0 pin.
Place the 1uF caps close to the jumper.

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
DEVKIT-MPC5744P
Page Title:
MCU Power
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 4 of 10
5 4 3 2 1
 5 4 3 2 1

MCU Pins
MCU I/O MATRIX VDD_HV_PMU VDD_HV_OSC

TPV1 TPV2

SILK = HV_PMU SILK = HV_OSC

VDD_HV_IO VDD_HV_FLA

TPV3 TPV4
D D

SILK = HV_IO SILK = HV_FLA

VDD_LV_CORE VDD_LV_PLL VDD_HV_ADV VDD_HV_ADRE0 VDD_HV_ADRE1

TPV5 TPV6 TPV7 TPV8 TPV9

SILK = LV_CORE SILK = LV_PLL SILK = HV_ADV SILK = HV_ADRE0 SILK = HV_ADRE1

131
135

126
18
39
70
93

36

21
91

72

27
97

58

50
56
U16

VDD_HV_OSC
VDD_HV_FLA

VDD_HV_ADV
VDD_LV_COR1
VDD_LV_COR2
VDD_LV_COR3
VDD_LV_COR4
VDD_LV_COR5
VDD_LV_COR6

VDD_LV_PLL

VDD_HV_IO_1
VDD_HV_IO_2
VDD_HV_IO_3
VDD_HV_IO_4

VDD_HV_PMU/VDD_HV_PMU_AUX/VDD_HV_IO_5

VDD_HV_ADRE0
VDD_HV_ADRE1
(GPIO) 73
[10] PA0 A0/GPIO0/ETIMER_0_ETC0/DSPI2_SCK/SIUL2_REQ0
(GPIO) 74
[10] PA1 A1/GPIO1/ETIMER_0_ETC1/DSPI2_SOUT/SIUL2_REQ1
(GPIO) 84
[6,10] PA2 A2/GPIO2/ETIMER_0_ETC2/FLEXPWM_0_A3/MC_RGM_ABS0/DSPI2_SIN/SIUL2_REQ2
(GPIO) 92 68 (GPIO)
[6,10] PA3 A3/GPIO3/ETIMER_0_ETC3/DSPI2_CS0/FLEXPWM_0_B3/MC_RGM_ABS2/SIUL2_REQ3 E0/GPI64/ADC1_AN5/ADC3_AN4 PE0 [10]
(GPIO) 108 49 (GPIO)
[6,10] PA4 A4/GPIO4/ETIMER_1_ETC0/DSPI2_CS1/ETIMER_0_ETC4/FLEXPWM_1_A2/SIUL2_REQ4/MC_RGM_FAB E2/GPI66/ADC0_AN5 PE2 [10]
(GPIO) 14 42 (GPIO)
[10] PA5 A5/GPIO5/DSPI1_CS0/ETIMER_1_ETC5/DSPI0_CS7/SIUL2_REQ5 E4/GPI68/ADC0_AN7 PE4 [10]
(GPIO) 2 44 (GPIO)
[10] PA6 A6/GPIO6/DSPI1_SCK/ETIMER_2_ETC2/SIUL2_REQ6 E5/GPI69/ADC0_AN8 PE5 [10]
(GPIO) 10 46 (GPIO)
[10] PA7 A7/GPIO7/DSPI1_SOUT/ETIMER_2_ETC3/SIUL2_REQ7 E6/GPI70/ADC0_ADC2_AN4 PE6 [10]
(GPIO) 12 48 (GPIO)
[10] PA8 A8/GPIO8/ETIMER_2_ETC4/DSPI1_SIN/SIUL2_REQ8 E7/GPI71/ADC0_AN6 PE7 [10]
(GPIO) 134 61 (GPIO)
[9] PA9 A9/GPIO9/DSPI2_CS1/ETIMER_2_ETC5/FLEXPWM_0_B3/FLEXPWM_0_FAULT0/SENT_0_SENT_RX1 E9/GPI73/ADC1_AN7/ADC3_AN6 PE9 [9]
(GPIO) 118 63 (GPIO)
[9] PA10 A10/GPIO10/DSPI2_CS0/FLEXPWM_0_B0/FLEXPWM_0_X2/SIUL2_REQ9/SENT_1_SENT_RX1 E10/GPI74/ADC1_AN8/ADC3_AN7 PE10 [9]
(GPIO) 120 65 (GPIO)
[9] PA11 A11/GPIO11/DSPI2_SCK/FLEXPWM_0_A0/FLEXPWM_0_A2/SIUL2_REQ10 E11/GPI75/ADC1_AN4/ADC3_AN3 PE11 [10]
(GPIO) 122 67 (ADC_POT)
[9] PA12 A12/GPIO12/DSPI2_SOUT/FLEXPWM_0_A2/FLEXPWM_0_B2/SIUL2_REQ11 E12/GPI76/ADC1_AN6/ADC3_AN5 PE12 [9]
(GPIO) 136 117 (GPIO)
[9] PA13 A13/GPIO13/FLEXPWM_0_B2/FLEXPWM_0_FAULT0/DSPI2_SIN/SIUL2_REQ12 E13/GPIO77/ETIMER_0_ETC5/DSPI2_CS3/DSPI1_CS4/DSPI3_SCK/SIUL2_REQ25 PE13 [10]
(GPIO) 143 119 (GPIO)
[10] PA14 A14/GPIO14/CAN1_TXD/ETIMER_1_ETC4/SIUL2_REQ13 E14/GPIO78/ETIMER_1_ETC5/DSPI3_SOUT/DSPI1_CS5/FLEXPWM_1_B2/SIUL2_REQ26 PE14 [10]
(GPIO) 144 121 (GPIO)
[9,10] PA15 A15/GPIO15/ETIMER_1_ETC5/CAN0_RXD/CAN1_RXD/SIUL2_REQ14 E15/GPIO79/DSPI0_CS1/ENET_0_TIMER1/DSPI3_SIN/SIUL2_REQ27 PE15 [10]
(CAN0_TX) 109
[7] PB0 B0/GPIO16/CAN0_TXD/ETIMER_1_ETC2/SSCM_DEBUG0/SIUL2_REQ15
(CAN0_RX) 110 133 (GPIO)
[7] PB1 B1/GPIO17/ETIMER_1_ETC3/SSCM_DEBUG1/CAN0_RXD/CAN1_RXD/SIUL2_REQ16 F0/GPIO80/FLEXPWM_0_A1/DSPI3_CS3/ENET_0_MDC/ETIMER_0_ETC2/SIUL2_REQ28 PF0 [9]
C (LIN0_TX) 114 139 (GPIO) C
[7,10] PB2 B2/GPIO18/LIN0_TXD/DSPI0_CS4/SSCM_DEBUG2/SIUL2_REQ17 F3/GPIO83/DSPI0_CS6/DSPI3_CS2/ENET_0_TIMER2 PF3 [10]
(LIN0_RX) 116 4 (GPIO)
[7,10] PB3 B3/GPIO19/DSPI0_CS5/SSCM_DEBUG3/LIN0_RXD F4/GPIO84/NPC_WRAPPER_MDO3/DSPI3_CS1 PF4 [10]
(TDO) 89 5 (GPIO)
[6,8] MCU_TDO B4/GPIO20/NPC_HNDSHK_TDO F5/GPIO85/NPC_WRAPPER_MDO2/DSPI3_CS0 PF5 [10]
(TDI) 86 8 (GPIO)
[8] MCU_TDI B5/GPIO21/DSPI0_CS7/TDI F6/GPIO86/NPC_WRAPPER_MDO1 PF6 [10]
(GPIO) 138 19 (GPIO)
[10] PB6 B6/GPIO22/MC_CGM_CLK_OUT/DSPI2_CS2/SIUL2_REQ18 F7/GPIO87/NPC_WRAPPER_MCKO PF7 [10]
(GPIO) 43 20 (GPIO)
[10] PB7 B7/GPI23/ADC0_AN0/LIN0_RXD F8/GPIO88/NPC_WRAPPER_MSEO1 PF8 [10]
(GPIO) 47 23 (GPIO)
[10] PB8 B8/GPI24/ADC0_AN1/ETIMER_0_ETC5 F9/GPIO89/NPC_WRAPPER_MSEO0 PF9 [10]
(GPIO) 52 24 (GPIO)
[10] PB9 B9/GPI25/ADC0_ADC1_AN11 F10/GPIO90/NPC_WRAPPER_EVTO PF10 [10]
(GPIO) 53 25 (GPIO)
[10] PB10 B10/GPI26/ADC0_ADC1_AN12 F11/GPIO91/NPC_WRAPPER_EVTI_IN PF11 [10]
(GPIO) 54 106 (SW1)
[10] PB11 B11/GPI27/ADC0_ADC1_AN13 F12/GPIO92/ETIMER_1_ETC3/FLEXPWM_1_A1/SIUL2_REQ30 PF12 [9]
(GPIO) 55 112 (SW2)
[10] PB12 B12/GPI28/ADC0_ADC1_AN14 F13/GPIO93/ETIMER_1_ETC4/FLEXPWM_1_B1/SIUL2_REQ31 PF13 [9]
(GPIO) 60 115 (GPIO)
[10] PB13 B13/GPI29/ADC1_AN0/LIN1_RXD F14/GPIO94/LIN1_TXD/CAN2_TXD PF14 [10]
(GPIO) 64 113 (GPIO)
[10] PB14 B14/GPI30/ADC1_AN1/ETIMER_0_ETC4/SIUL2_REQ19 F15/GPIO95/LIN1_RXD/CAN2_RXD PF15 [10]
(GPIO) 62
[9] PB15 B15/GPI31/ADC1_AN2/SIUL2_REQ20
(GPIO) 66
[9] PC0 C0/GPI32/ADC1_AN3
(GPIO) 41
[10] PC1 C1/GPI33/ADC0_AN2
(GPIO) 45 102 (GPIO)
[10] PC2 C2/GPI34/ADC0_AN3 G2/GPIO98/FLEXPWM_0_X2/DSPI1_CS1 PG2 [10]
(GPIO) 11 104 (GPIO)
[9] PC4 C4/GPIO36/DSPI0_CS0/FLEXPWM_0_X1/SSCM_DEBUG4/SIUL2_REQ22 G3/GPIO99/FLEXPWM_0_A2/ETIMER_0_ETC4 PG3 [10]
(GPIO) 13 100 (GPIO)
[9] PC5 C5/GPIO37/DSPI0_SCK/SSCM_DEBUG5/FLEXPWM_0_FAULT3/SIUL2_REQ23 G4/GPIO100/FLEXPWM_0_B2/ETIMER_0_ETC5 PG4 [10]
(GPIO) 142 85 (GPIO)
[9] PC6 C6/GPIO38/DSPI0_SOUT/FLEXPWM_0_B1/SSCM_DEBUG6/SIUL2_REQ24 G5/GPIO101/FLEXPWM_0_X3/DSPI2_CS3/ENET_0_TX_EN PG5 [10]
(GPIO) 15 98 (GPIO)
[9] PC7 C7/GPIO39/FLEXPWM_0_A1/SSCM_DEBUG7/DSPI0_SIN G6/GPIO102/FLEXPWM_0_A3 PG6 [10]
(GPIO) 111 83 (GPIO)
[10] PC10 C10/GPIO42/DSPI2_CS2/FLEXPWM_0_A3/FLEXPWM_0_FAULT1 G7/GPIO103/FLEXPWM_0_B3/LFAST PG7 [9]
(LED_RED) 80 81 (FR_DBG0)
[9] PC11 C11/GPIO43/ETIMER_0_ETC4/DSPI2_CS2/ENET_0_TX_ER/DSPI3_CS0 G8/GPIO104/FLEXRAY_FR_DBG0/DSPI0_CS1/ENET_0_RMII_CLK/FLEXPWM_0_FAULT0/SIUL2_REQ21/SENT0_SENT_RX0/ENET_0_TX_CLK PG8 [7,10]
(LED_GREEN) 82 79 (FR_DBG1)
[9] PC12 C12/GPIO44/ETIMER_0_ETC5/DSPI2_CS3/LFAST/DSPI3_CS1/SENT1_SENT_RX0 G9/GPIO105/FLEXRAY_FR_DBG1/DSPI1_CS1/ENET_0_TX_D0/FLEXPWM_0_FAULT1/SIUL2_REQ29/SENT_1_SENT_RX0 PG9 [7,10]
(LED_BLUE) 101 77 (FR_DBG2)
[9] PC13 C13/GPIO45/ETIMER_1_ETC1/FLEXPWM_1_A0/CTU_0_EXT_IN/FLEXPWM_0_EXT_SYNC G10/GPIO106/FLEXRAY_FR_DBG2/DSPI2_CS3/ENET_0_TX_D1/FLEXPWM_0_FAULT2/SENT_0_SENT_RX1 PG10 [7,10]
[10] PC14 103 75 (FR_DBG3)
(FR_A_TX_EN) 124 C14/GPIO46/ETIMER_1_ETC2/CTU_0_EXT_TGR/DSPI1_CS7/FLEXPWM_1_B0 G11/GPIO107/FLEXRAY_FR_DBG3/ENET_0_TX_D3/FLEXPWM_0_FAULT3/SENT_1_SENT_RX1 PG11 [7,10]
[7] PC15 C15/GPIO47/FLEXRAY_FR_A_TXEN/ETIMER_1_ETC0/FLEXPWM_0_A1/CTU_0_EXT_IN/FLEXPWM_0_EXT_SYNC 95 (GPIO)
(FR_A_TX) J8/GPIO152/ETIMER_2_ETC4/ETIMER_2_ETC2/CAN2_RXD PJ8 [10]
[7] PD0 125 16 (GPIO)
(FR_A_RX) 3 D0/GPIO48/FLEXRAY_FR_A_TX/ETIMER_1_ETC1/FLEXPWM_0_B1 J9/GPIO153/ETIMER_2_ETC5/NPC_NEX_RDY/CTU_1_EXT_IN/ENET_0_RX_D3 PJ9 [10]
[7] PD1 D1/GPIO49/ETIMER_1_ETC2/CTU_0_EXT_TGR/FLEXRAY_FR_A_RX
(GPIO) 140
[9] PD2 D2/GPIO50/ETIMER_1_ETC3/FLEXPWM_0_X3/FLEXRAY_FR_B_RX
(GPIO) 128 31
[10] PD3 D3/GPIO51/FLEXRAY_FR_B_TX/ETIMER_1_ETC4/FLEXPWM_0_A3 RESET MCU-RSTx [6,8,9]
(GPIO) 129
[10] PD4 D4/GPIO52/FLEXRAY_FR_B_TXEN/ETIMER_1_ETC5/FLEXPWM_0_B3
(GPIO) 33 130
[10] PD5 D5/GPIO53/DSPI0_CS3/DSPI3_SOUT/FLEXPWM_0_FAULT2/SENT0_SENT_RX0/ENET_0_RX_D1 EXT_POR MCU_PORSTx [6] VDD_HV_IO
(GPIO) 34
[10] PD6 D6/GPIO54/DSPI0_CS2/FLEXPWM_0_X3/DSPI3_SCK/FLEXPWM_0_FAULT1/ENET_0_RX_D0
(GPIO) 37 38 SILK = FCCU_F0 TPV10
[10] PD7 D7/GPIO55/SGEN_OUT/DSPI1_CS3/DSPI0_CS4/DSPI3_SIN/SENT1_SENT_RX0/ENET_0_RX_DV FCCU_F0
(GPIO) 32 141 SILK = FCCU_F1 TPV11
B [10] PD8 D8/GPIO56/DSPI1_CS2/ETIMER_1_ETC4/DSPI0_CS5/FLEXPWM_0_FAULT3/ENET_0_RX_CLK FCCU_F1 B
(LIN1_TX) 26
[8,9,10] PD9 D9/GPIO57/FLEXPWM_0_X0/LIN1_TXD
(GPIO) 76 87 (TMS)
[10] PD10 D10/GPIO58/FLEXPWM_0_A0/ENET_0_TX_D2/DSPI3_CS0/ETIMER_0_ETC0 TMS MCU_TMS [8]
(GPIO) 78 88 (TCK) R11
VSS_LV_COR2/VSS_LV_PLL

[10] PD11 D11/GPIO59/FLEXPWM_0_B0/DSPI3_CS1/DSPI3_SCK/ETIMER_0_ETC1 TCK MCU_TCK [8]

(LIN1_RX) 99 123 10K
[8,9,10] PD12 D12/GPIO60/FLEXPWM_0_X1/DSPI1_CS6/DSPI3_CS2/DSPI3_SOUT/LIN1_RXD JCOMP MCU_JCOMP [6,8]
(GPIO) 105 9 SILK = MDO0 TPV12
[9] PD14 D14/GPIO62/FLEXPWM_0_B1/DSPI3_CS3/DSPI3_SIN/ETIMER_0_ETC3 MDO0
1
69 NMI

VSS_HV_ADRE0
VSS_HV_ADRE1
[4] BCTRL BCTRL
VSS_LV_COR1

VSS_LV_COR3
VSS_LV_COR4
VSS_LV_COR5
VSS_LV_COR6
VSS_LV_COR7
VSS_LV_COR8

VSS_HV_IO_1
VSS_HV_IO_2
VSS_HV_IO_3
VSS_HV_IO_4

VSS_HV_OSC

VSS_HV_ADV
107 C31
VPP_TEST 29 MCU_XTAL
XTAL 30
EXTAL

1
R12 Y1 12PF
GND 1M 5%
SPC5744PFK1AMLQ9 DNP 40MHz
17
35
40
71
94
96
132
137

7
22
90
127

28

59

51
57

C32 12PF

2
MCU_EXTAL

5%
CX3225GA40000D0PTVZ1 GND
Layout notes on signal Grounds: GND (Optimised for Automotive,
8pF Load capacitance)
- The scheme shown has the analogue and digital grounds connected to the same plane
- This results in better ADC performance than using an analogue grond plane with single entry
point (or ferrite) to digital ground plane.

A
Key to text colours: A

Purple - Comms Physical Interfaces

Orange - Other Peripherals and I/O
Blue - Debug (JTAG & Nexus) ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:

Black - Clock, Reset and Control DEVKIT-MPC5744P

Page Title:

RED - I/O Matrix and other functions (eg. LED, BUTTON) MCU Pins
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Green - I/O Matrix (dedicated)
Date: Wednesday, September 28, 2016 Sheet 5 of 10
5 4 3 2 1
 5 4 3 2 1

Boot, Reset & JTAG

D D

Reset Input / Output PORST

Connect an external LVI to pad 3V3_SR
3V3_SR when supplying external 1.25V so
that PORST is asserted until R13

3V3_SR
exterbal 1.25V supply is at 10K

threshold and stable TPH1

SILK = PORSTx
R14 DNP 1
MCU_PORSTx [5]
C33 270
0.1UF

A
DS3 R17 10K
R15 R16 LED_YELLOW
TARGET Bi Directional reset
U5
Reset from 10K 10K GND RESET line to/from MCU
4 2 RST-INx R18 0
Debugger LED VCC RST MCU-RSTx [5,6,8,9]

8
U4A
1 VCC
[6] JTAG-RSTx

C
7 SYSTEM-RSTx 3 1
RST-SWITCHx 2 MR VSS
GND
1 SW3 4 74LVC2G08 C34 STM6315 GND
U4B
4

TPV13 0.1UF
5
Tri-State Buffered 3
C
2 3
GND RESET signal to 6 C
GND
SILK = RESET reset the MCU
GND SKRPABE010 C35 74LVC2G08
0.1UF GND
Reset Switch
GND

JTAG Standard 14-pin Connector BOOT CONFIGURATION 3V3_SR

3V3_SR
Layout Note:
Clearly mark pin numbers
R20 R21 1, 2, 13 and 14 J35 J34 J33 R83 R84 R85
B HDR 1X2 HDR 1X2 HDR 1X2 B
10K 10K 10K 10K 10K
ONCE Connector

14
P2 U26
TDI (TDI) 1 2 (GND) 13

VCC
[8] TDI_HEADER

1
2

1
2

1
2
TDO (TDO) 3 4 (GND) 12 4OE 11 (MC_RGM_ABS0)
[5,8] MCU_TDO TCLK (TCLK) 5 6 (GND) 4A 4Y PA2 [5,10]
[8] TCLK_HEADER (EVTI) 7 8 (N/C) 10 8 (MC_RGM_ABS2)
DBUG-RSTx (RESET)9 10 (TMS) GND GND GND 9 3OE 3Y PA3 [5,10]
R22 0 (VREF) 11 12 (GND) 3A
(RDY) 13 14 (JCOMP) JCOMP 4 6 (MC_RGM_FAB)
[6] JTAG-RSTx (buffered MCU_JCOMP [5,8] 5 2OE 2Y PA4 [5,10]
reset TO MCU) HDR_2X7 2A
R23 0 R24 1 3
SILK = JTAG Layout Note:

GND
[5,6,8,9] MCU-RSTx 1OE 1Y
10K 2
[5,6,8,9] MCU-RSTx 1A
(bidirectional J33, J34, J35 Mark MC_RGM_ABS0,
MCU reset) 74LVC125
short in bottom layer MC_RGM_ABS2, MC_RGM_FAB

7
Optional default: boot from Flash close to U26 pins
Config
GND
TMS
[8] TMS_HEADER GND

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
DEVKIT-MPC5744P
Page Title:
Boot, Reset & JTAG
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 6 of 10
5 4 3 2 1
 5 4 3 2 1

Flexray, CAN, LIN

FLEXRAY_A Physical Interface

Note on VBAT: Layout notes: decoupling
- Operational range is 4.45V to 60V Place next to power pins.
- Undervoltage detection is max 4.715V FRBATA 5V0_SR 3V3_SR
D FlexRAY D

debug On EVB this is supplied from 5v, In theory this

connector should be to battery with 60uS delay between
C38 C39
P3 DNP applying Vbat and I/O voltages. If necessary, C36 C37 0.1UF 0.1UF
(FR_DBG0) 1 2 (FR_DBG1) 10uF 10uF
[5,10] PG8 (FR_DBG2) 3 4 (FR_DBG3) 12V can be externally supplied by removing the
[5,10] PG10
resistor and connecting pad to 12v
SILK = FR_DBG
3V3_SR 5V0_SR FRBATA
[5,10] PG11 VBAT VCC VIO
TPV14
[5,10] PG9
R25 0 SILK = BATA GND

(FR_A_TX) R26 0 FRA-JTXD

16

11
[5] PD0

3
(FR_A_TX_EN) R27 0 FRA-JTXEN U6
[5] PC15 (FR_A_RX) R28 0 FRA-JRXD

VCC

VBAT
VIO
[5] PD1
R29 C40
4 1 FRA-INH2 47 10PF
TXD INH TPV15
1% C41 5% P4
3V3_SR 5 15 FRA-BP 1 L3 2 FRA-DATA-A 4700pF 1
TXEN BP 2
R30 10K FRA-BGE 7 14 FRA-BM 4 3 FRA-DATA-B
R31 10K BGE BM
DLW43SH SILK = FLEXRAY
R32 10K FRA-STBN 8 R33 C42 GND
STBN 6 47 10PF
R34 10K FRA-EN 2 RXD 1% 5%
Crimped lead - 279-9522
EN
RXEN
9 FRA-RXEN
TPV16 Receptacle housing - 279-9156
GND FRA-WAKE 12 10 FRA-ERRN
WAKE ERRN TPV17
BGE: Bus Guardian Enable. Bus voltage +/- 12V (VBAT = 12v)

GND
Pull high to enable Components spec'd for 12V operation
C TJA1081B C
transmitter

13
R35 R36
10K 10K
DNP DNP
STBN: Standby Input.
Pull High for non standby GND

mode GNDGND

EN: Enable Input.

PUll high to enable

LIN0 Physical Interface Master Mode Pullup Enable

R41 0 VSUP1
D5 DNP
J10 DNP SBR3U30P1 R42 2.0K
3V3_SR 1 2 A C P6
U8 R43 2.0K 1
MC33662LEF LIN transceiver is newer version of 33661 offering:

1
(LIN0_RX) R44 0 LIN0-RX 1 8 HDR 1X2 2
[5,10] PB3 RXD INH
(Enable) 2 7 C A LIN0-VSUP 3
(Wake) 3 EN VSUP 6 D6 SBR3U30P1 LIN0-LIN 4 - Full LIN compliance (33661 no longer compliant)
WAKE LIN
[5,10] PB2
(LIN0_TX) R45 0 LIN0-TX 4
TXD GND
5
C48
- Improved ESD protection on LIN pin up to 15KV
C47
2.2uF
Total current GND HDR 1X4 RA - Improved ESD on Wake and VSUP Pins
MC33662BLEF 0.1UF
GND GND
Battery through resistors - Other EMC and performance improvements
(LEF = 20K Baud) Reverse (LIN Bus at GND)
polarity & = 12mA (0.144W) See www.nxp.com for more details
B B
GND Pulse
Protection Each resistor spec
WAKE = GND ensures no spurious wakeups = 0.1W (0.2W total)
EN = 3.3V enables Transceiver and sets I/O for 3.3V

CAN0 Physical Interface

VDD - 5.0V input supply for

CAN transceiver (4.5 to 5.5V) 5V0_SR 3V3_SR

VI/O - 3.3V for MCU TX and RX pins C44 C46

C43 C45
2.2uF
0.1UF
2.2uF
0.1UF Layout notes:
STB - High for Standby mode, CAN termination resistor
pulled low for normal mode. footprint
Place on underside of PCB
3

GND U7 GND
VDD

VIO

(CAN0_TX) R37 0 CAN0_TX 1 R38 120.0

[5] PB0 TXD
DNP P5
(CAN0_RX) R39 0 CAN0_RX 4 7 CAN0-CANH
[5] PB1 RXD CANH
A 1 A
R40 4.7K CAN0-S 8 6 CAN0-CANL 2
STB CANL 3
GND

4
TPV18
GND SILK = CAN0-S MC33901WEF
2

GNDHDR 1X4 RA
SILK = CAN
GND ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
DEVKIT-MPC5744P
Page Title:
Flexray, CAN, LIN
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 7 of 10
5 4 3 2 1
 5 4 3 2 1

OpenSDA
OpenSDA INTERFACE K20_VOUT33
TP29

U9
Default A
A -> K20 internal regulator
3V3 output A R46 P3V3_SDA
OpenSDA INTERFACE
0
1
VDD1
JTAG CONNECTOR 3V3_SR
TP12 P3V3_SDA U10
D B -> external power supply C49 C50 P3V3_SDA D
B J11
set J13 as 1-2 3V3_SR
0.1UF 10uF
7 SDA_JTAG_TMS 2 1 TCLK_K20
7
6 VCCA VCCB
8
1 TCLK
VDDA SDA_JTAG_TCLK 4 3 TDI_K20 5 1A 1B 2 TDI
SDA_JTAG_TDO 6 5 4 2A 2B 3 OUT_EN_PASS R47 10K
GND GND SDA_JTAG_TDI 8 7 GND DIR
8 SDA_JTAG_RST 10 9
VSSA 12 TP13 GND 74LVC2T45GM,125 GND
JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH5 13
JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH6 HDR 2X5
GND 14 GND
P5V_SDA JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH7 15
JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH0 16 RST_K20 TP14 P3V3_SDA U11 3V3_SR
L4 NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P3
TP5
1 2 11 7 8 TP26
VBAT TMS_K20 6 VCCA VCCB 1 TMS
C51 Y2 JCOMP_K20 5 1A 1B 2 JCOMP R88 0
330 OHM 4.7UF 1 2 4 2A 2B 3 OUT_EN_PASS MCU_JCOMP [5,6]
P5V_SDA GND DIR
8

USB_MICRO_AB 17 SDA_EXTAL 8MHZ

K20_VOUT33 EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0 18 SDA_XTAL C52 C53 TP15 GND 74LVC2T45GM,125
SHELL3

SHELL4

GND 6 XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1 10K

12PF 12PF
SDA_USBSHIELD

1 5 VREGIN R48
VBUS 2 SDA_USB_CONN_DN R49 33 SDA_USB_DN 4 VOUT33
10 D- 3 SDA_USB_CONN_DP R50 33 SDA_USB_DP 3 USB0_DM GND GND
SHELL5 D+ 4 TC_SDA_USB_ID_TP USB0_DP U12 3V3_SR
ID 1 SW4 4 TP16 P3V3_SDA TP27
5 C54 GND
SHELL2

SHELL1

GND TP6 P3V3_SDA 2.2uF 20 OUT_EN_PASS 7 8

ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P5 21 BOOT_ENTRY TDO_K20 6 VCCA VCCB 1 TDO
ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB 1A 1B MCU_TDO [5,6]
GND 10 TXD_K20 5 2 TXD_USB_UART
J12 EXTAL32 2 3 2A 2B PD9 [5,9,10]
GND 9 GND 4 3
7

R51 XTAL32 DS5 SILK = BOOT GND DIR

SILK = SDA
10K GREEN SKRPABE010 P3V3_SDA
L5 TP17 TP28
GND 74LVC2T45GM,125 GND
1 2 C A R52 270
TP7 SDA_JTAG_RST 19
RESET
330 OHM GND TP8 DS6
C GREEN P3V3_SDA P3V3_SDA 3V3_SR C
U13
22 SDA_LED C A R53 270 1 6
2 ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P6 23 JCOMP_K20 RST_K20 5 VCCA VCCB
(Layout Note: VSS1 ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS 24 TXD_K20 DIR
CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/I2S0_TX_BCLK/LLWU_P7
Route USB_N and USB_P with PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P8
25 RXD_K20 3
A B
4
MCU-RSTx [5,6,9]
GND 26 TCLK_K20
90 Ohm Differential Pair. PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P9 27 TDI_K20
CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P10 TDO_K20
Keep tracks CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS
28 R54
GND
2

as short as possible) 1.0K

74LVCH1T45
GND
1%
33 GND
EPAD

GND

P3V3_SDA 3V3_SR
U14 TP25
1 6
29 RXD_TXD_EN RXD_TXD_EN 5 VCCA VCCB
PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P14 30 TMS_K20 DIR
ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT 31 VTGT_EN RXD_K20 3 4 RXD_USB_UART
ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P15 A B PD12 [5,9,10]
32 VFLGA
PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1
P3V3_SDA R55 2
R56 10K GND
10K
TP18
74LVCH1T45
P5V_SDA 5V_TGT_OUT GND
U29
1 6
VIN VOUT GND
C55 C87 12PF 5 4
10uF DNP CSLEW FAULT C56
MK20DX128VFM5 3 2 100uF
ENABLE GND
B B
MIC2005-0.8YM6
R58
GND 10K GND

The CSLEW pin is provided to

GND increase control of the output
voltage ramp at turn-on.
The upper limit on the value
of C87 is 4nF.
3V3_SR
3V3_SR 3V3_SR Herein, C87 is DNP - only
a footprint for further use.

10K
10K
10K
10K

10K
10K

3V3_SR

TP22 TP23 TP24

3V3_SR
R63
R64
R59
R60

R61
R62

U18
8

U17B U17A TMS 1 6

TCLK 5 TDI 1 VCC B VCC
3 TCLK
MCU_TCK [5] 7 TDI
MCU_TDI [5] 2 4 TMS
MCU_TMS [5]
6 2 [6] TMS_HEADER A Y
[6] TCLK_HEADER [6] TDI_HEADER
GND 3 5
74LVC2G08 74LVC2G08 GND NC
4

74LVC1G08
GND

GND

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
DEVKIT-MPC5744P
Page Title:
OpenSDA
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 8 of 10
5 4 3 2 1
 5 4 3 2 1

User Peripherals
User Pushbutton Switches (Active High)
3V3_SR
1 SW1 4
ADC Input Pot and Test Point User RGB LED (Active Low)
(PB_SW1) VDD_AREF RV1
2 3 PF12 [5]
5K
SILK = SW1_PF12
3 1 SILK = RED LED SILK = GREEN LED
SKRPABE010 TP9 TPV19 TPV20
D D
SILK = ADC_PB4 D7

2
R68 R69
GND (LED_RED) 270 LEDRGB_RED 1 4 LEDRGB_GREEN 270 (LED_GREEN)
[5] PC11 PC12 [5]

1
1 SW2 4 (PB_SW2) R G
PF13 [5] (ADC1_AN6) 2 3 LEDRGB_BLUE
R65 0 3V3_SR 270 (LED_BLUE)
PE12 [5] PC13 [5]
B
R66 R67 C57 R70
10K 10K 0.1UF CLV1A-FKB-CJ1M1F1BB7R4S3 TPV21
2 3
SILK = SW1_PF13
SILK = BLUE LED
SKRPABE010

GND GND GND

LEVEL TRANSLATOR FOR FRDM+ HDR_1X3

J38
HDR_1X3
J26
1-2 -> 3.3V 3V3_SR 5V0_SR Arduino UNO compatible pins
1-2 -> 3.3V 3V3_SR Arduino UNO compatible pins 2-3 -> 5V alternative for PWM/IRQ or Analog
5V0_SR

1
2
3
2-3 -> 5V alternative for PWM or Analog VDD_AREF
default PWM/IRQ with jumper on J37
1
2
3

R87 10K R86 10K

default PWM with jumper on J30 VDD_AREF with no jumper on J36
R78 10K R80 10K
with no jumper on J27
alternative Analog with jumper on J36 U27 8

alternative Analog with jumper on J27 U24 8 with no jumper on J37 VCC

7
U28
1
with no jumper on J30

VCCA

VCCB
VCC [5] PE9 1A
3

U22 7
1 5 8 2 1S
C C
VCCA

VCCB

[5] PB15 1A [5] PA9 A1 B1 LT_PA9 [9,10] [9,10] LT_PA9 1B

7 6
5 8 2 1S 4 1 3 2B LT_PA15 [9,10]
[5] PA12 A1 B1 LT_PA12 [9,10] [9,10] LT_PA12 1B 6 [5,10] PA15 A2 B2 LT_PA15 [9,10] 2S 5

GND
2B LT_PA13 [9,10] 2A PE10 [5]
4 1 3 6
[5] PA13 A2 B2 LT_PA13 [9,10] 2S 5 OE
GND

2A PC0 [5] J37 GND

6 NTB0102DP
J36

2
OE 2 FSA1259A
J30 GND 2 1 4
NTB0102DP
J27
2

2 FSA1259A 1
2 1 4
1 HDR 1X2 GND
HDR 1X2 GND
HDR 1X2 GND
FSA1259A active HIGH
HDR 1X2 GND
NTB0102DP active HIGH no jumper -> ON
FSA1259A active HIGH no jumper -> ON
NTB0102DP active HIGH no jumper -> ON jumper on -> OFF
no jumper -> ON jumper on -> OFF
jumper on -> OFF
jumper on -> OFF

HDR_1X3
HDR_1X3 J24
J20 1-2 -> 3.3V 3V3_SR 5V0_SR
1-2 -> 3.3V 3V3_SR 5V0_SR 2-3 -> 5V
2-3 -> 5V

1
2
3
1
2
3

R77 10K
R75 10K
14
1

U19

7
U21
VCCA

VCCB

VCCA

VCCB
B B
2 13
[5] PF0 A1 B1 LT_PF0 [10]
3 12 5 8
[5] PD14 4 A2 B2 11 LT_PD14 [10] [5,8,10] PD12 A1 B1 LT_PD12 [10]
[5] PD2
5 A3 B3 10
LT_PD2 [10]
4 1
1-2 -> 3.3V
[5] PG7 A4 B4 LT_PG7 [10] [5,8,10] PD9 A2 B2 LT_PD9 [10]
2-3 -> 5V

GND
GND1
GND2

8 6 6
OE NC1 9 OE HDR_1X3
J21 NC2 NTB0102DP J32
J25

2
2
NTB0104BQ active HIGH NTB0102DP active HIGH
7
15

1 NTB0104BQ 2 3V3_SR 5V0_SR

no jumper -> ON no jumper -> ON 1
jumper on -> OFF jumper on -> OFF

1
2
3
HDR 1X2
GND HDR 1X2 GND 3V3_SR
U25
1 6
5 VCCA VCCB
[5,6,8] MCU-RSTx DIR
HDR_1X3 HDR_1X3
J22 J28 3 4 LT_MCU-RSTx [10]
A B
1-2 -> 3.3V 3V3_SR 5V0_SR 1-2 -> 3.3V 3V3_SR 5V0_SR
2-3 -> 5V 2-3 -> 5V R82
GND
2
1
2
3

1
2
3

1.0K
74LVCH1T45
GND
R76 10K R79 10K
1%
GND
14
1

U20
VCCA

VCCB

U23
2 13
VCCA

VCCB

[5] PC4 A1 B1 LT_PC4 [10]

3 12
[5] PC5 4 A2 B2 11 LT_PC5 [10] 5 8
[5] PC6 5 A3 B3 10 LT_PC6 [10] [5] PA10 A1 B1 LT_PA10 [10]
[5] PC7 A4 B4 LT_PC7 [10]
4 1
[5] PA11 A2 B2 LT_PA11 [10]
GND1
GND2

A 8 6 A
GND

OE NC1 9 6
J23 NC2 OE
2 NTB0102DP
NTB0104BQ active HIGH J29
7
15

1 NTB0104BQ
no jumper -> ON NTB0102DP active HIGH 2
jumper on -> OFF HDR 1X2
no jumper -> ON 1

GND jumper on -> OFF ICAP Classification: CP: ___ IUO: X PUBI: ___
HDR 1X2 GND Drawing Title:
DEVKIT-MPC5744P
Page Title:
User Peripherals
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 9 of 10
5 4 3 2 1
 5 4 3 2 1

FRDM+ Connectors

[5,6] PA3
[5,6] PA4 FRDM+ I/O interface default 3.3V
D [5] PA5 D
[5] PA6
[5] PA7
[5] PA8
Not all pins are compatible 5V
[5] PE7 Net with prefix "LT" for 5V option
[5] PB6

[5] PC10 PF11 [5] 3V3_SR

[5] PC14 PF10 [5]
[5] PE11 PF15 [5,10]
[5] PD3 PF14 [5,10]
[5] PD4
[5] PD10
[5,7,10] PB2 PA15 [5,9,10]
[5,7,10] PB3 PA14 [5,10]
3V3_SR [5,10] PA14 PF7 [5]
[5,9,10] PA15 PF5 [5]
GND
3V3_SR
4.7K

4.7K

20
18
16
14
12
10

16
14
12
10

20
18
16
14
12
10
8
6
4
2

8
6
4
2

8
6
4
2
J2 J1 J6

4.7K

4.7K
CON 2X10 CON 2X8
CON 2X10
R71

R72
DNP

DNP

19
17
15
13
11
9
7
5
3
1

19
17
15
13
11
9
7
5
3
1
15
13
11
9
7
5
3
1

R73

R74
DNP

DNP
VDD_AREF PF4 [5]
[9] LT_PA15 PF6 [5]
[9] LT_PA9 PF8 [5]
R81 0 EXT_AR_PWR
PF9 [5]
PB3 [5,7,10]
DNP [9] LT_PC5 PB2 [5,7,10]
Populate R81 for GND
[9] LT_PC7 PD12 [5,8,9,10]
[9] LT_PC6 PD9 [5,8,9,10]
external ADC high
C
reference voltage
[9] LT_PC4
[9] LT_PG7
PB3 [5,7,10]
PB2 [5,7,10]
NOTE: C
[9] LT_PD2
Arduino UNO compatible headers:
J1, J2, J3, J4
[9] LT_PA13
12V_IN
[9] LT_PA12
[9] LT_PD14
J39
1
[9] LT_PF0 FDRM+ MC SHIELD/DEVKIT-MOTORGD compatible headers:
[9] LT_PA10
2
[9] LT_PA11 J1, J2, J3, J4, J5
[9] LT_PD9
HDR 1X2 [9] LT_PD12

Check external power

[5] PJ9
[5] PB13
DEVKIT-COMM compatible headers:
before put on the shunt [5] PB7
[5] PB11
J1, J2, J3, J4, J5, J6
[5] PB10
HDR_1X3 [5] PB9
J31 [5] PB12 PA0 [5]
3V3_SR 5V0_SR
[5] PB8 PA1 [5]
PA2 [5,6]
3V3_SR 5V0_SR
PG8 [5,7]
PF3 [5]
1
2
3

PG11 [5,7]
[9] LT_MCU-RSTx PG9 [5,7]
EXT_LV_PWR
PE2 [5]
EXT_HV_PWR
PE5 [5]
PG10 [5,7]
C58
11
13
15

11
13
15
1
3
5
7
9

1
3
5
7
9
2.2uF GND

11
13
15
17
19
1
3
5
7
9
CON 2X8 CON 2X8 CON 2X10
GND J3 J4 J5
2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16
18
20
B B

Layout notes (at least): [5,8,9,10] PD12 PB14 [5]

[5,8,9,10] PD9 PC2 [5]
EXT_LV_PWR: 20mil [5] PJ8 PE4 [5]
3V3_SR
EXT_HV_PWR: 40mil x2 [5] PE13
[5] PE14
PC1 [5]

EXT_AR_PWR: 20mil [5] PE15

5V0_SR: 20mil [5,10] PF14 PD8 [5]
[5,10] PF15 PD7 [5]
3V3_SR: 20mil x3 PD6 [5] GND
PD5 [5]
[5] PE0
[5] PE6
[5] PG2
[5] PG3
[5] PG4
[5] PG5
[5] PG6
[5] PD11

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
DEVKIT-MPC5744P
Page Title:
FRDM+ Connectors
Size Document Number Rev
C SCH-29333 PDF: SPF-29333 B
Date: Wednesday, September 28, 2016 Sheet 10 of 10
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