LABORATORY HANDBOOK & MANUAL

EEE 3401
LAB INVESTIGATIONS I

BACHELOR OF ELECTRICAL & ELECTRONICS ENGINEERING

WITH HONOURS

September 2019
 :: CONTENT ::

GENERAL
I. Module Description
II. Introduction
III. Weekly Plan
IV. General Laboratory Safety Rules
V. Student Conduct and Laboratory Report Submission
VI. Lab Report Format
VII. Lab Report Cover Page and Marking Assessment
VIII. Rubric 1: Marking Scheme - Lab Practical
IX. Rubric 2: Marking Scheme – Lab Report

LIST OF EXPERIMENTS
1. Circuit and Signal I :Circuit Laws - Ohm’s Law and Kirchhoff’s law
2. Communication System - Amplitude Shift Keying (ASK) Modulation &
Demodulation
3. Digital Electronics I - Verification of Logic Gates
4. Circuit and Signal I : Superposition Theorem (Open-Ended Lab)
5. Communication System - Frequency Shift Keying (FSK) Modulation &
Demodulation [Open-ended Lab]
6. Digital Electronics I - Design of Logic Circuit [Open-ended Lab]
REV 10/09/19 AF
 MODULE DESCRIPTOR

Module Info
 Subject : Laboratory Investigations I
 Subject Code : EEE3401
 Assessment : Lab report – 80% (GROUP)
Practical – 20% (INDIVIDUAL)

Learning Objectives
 Develop student’s practical & team communication skills in E&E engineering laboratory
and workshop practice in relevant to theoretical concepts introduced in the course
lectures.

 Introduce students to safety procedures, various experimental areas, technical report,

writing and presentation.

Course Outcomes
On completion of this subject, students will be able to:
CO1: Conduct an investigation to verify basic laws and circuit theorems of electrical circuits.
CO2: Apply and compare the characteristics of logic gates.

CO3: Apply the knowledge of modulation/demodulation techniques in communication

systems.
Introduction
This laboratory manual is available to all students at the beginning of the semester
contains the detailed information about the experiment objectives with each having a brief
introduction, a short description of the facility, suggestions for summary and a few
references. Students must prepare themselves for the next scheduled experiment following
the appropriate hand-out.

Your report should be submitted 1 week after the date of the experiment (by 5 pm).
You must submit a hardcopy version only. Late submission will be subjected to a penalty.
Note that the submission is to be done in GROUP of THREE (3).

Shall any of the group members being absent with a VALID reason, he/she must
submit an INDIVIDUAL REPORT after the replacement lab has been conducted.

I mportant Notes:
Plagiarism – Plagiarism is a form of cheating. Do not use someone else’s ideas or words and
submit them as your own. You will get a 0% grade for plagiarising.
WEEKLY SCHEDULE

Week Date Session Instructor Submission Notes

Week 1 12th Sept 2019

Ir. Ts. Azri Adi &

Lab Briefing, Introduction to Electronic &
Week 2 19th Sept 2019 Ms. Anis Fariza
Electrical Lab (Hands On)

Ir. Ts. Azri Adi

Week 3 26th Sept 2019 Circuit & Signals I -Kirchhoff's law

Lab Report
Week 4 3rd Oct 2019 Communication System - Amplitude Shift Ms. Anis Fariza
Week 3
Keying (ASK) Modulation & Demodulation
Digital Electronics I - Verification of Logic Lab Report
Week 5 10th Oct 2019 Ms. Anis Fariza
Gates Week 4

Lab Report
Week 6 17th Oct 2019
Week 5
Network Theorems: Superposition, Ir. Ts. Azri Adi All Lab Reports MUST BE submitted
Theorem [Open-ended Lab]
only to Lab Technician; Ms Ummul
Week 7 th
24 Oct 2019
Khairah before the start of the next
laboratory session.
Lab Report
Week 8 31st Oct 2019 Report that is submitted later than the
Communication System - [Open-ended Week 6
Ms. Anis Fariza above mentioned period will be
Lab]
Week 9 7th Nov 2019 awarded with ZERO (0). Please sign
the logbook upon submission.
Lab Report
Week 10 14th Nov 2019
Digital Electronics I - Design of Logic Week 8
Ms. Anis Fariza
Circuit [Open-ended Lab]
Week 11 21st Nov 2019

Lab Report
Week 12 28th Nov 2019 Replacement lab (With a valid Absent form)
Week 10

Week 13 5th Dec 2019

Final Submission of ALL REPORTS for Replacement Lab
Week14 12th Dec 2019
 GENERAL LABORATORY SAFETY RULES

1. Food, beverages, substances and related utensils shall not be brought into, stored or
consumed in any laboratory.
2. Smoking is prohibited in all laboratories at all times. Switch off mobile phone during
laboratory session.
3. Appropriate lab apparel and shoes shall be worn in the laboratories at all times. No slipper
allowed.
4. Appropriate eye protection and other safety equipment shall be properly donned when
using dangerous or high voltage electrical equipment and as directed.
5. All occupants shall be familiar with the locations and operation of safety and emergency
equipment, including but not limited to, fire extinguishers, first aid kits, emergency eye
wash stations and emergency showers, emergency power off system, fire alarm pull
stations, emergency telephones, and emergency exits and egress plans.
6. Do not endanger yourself or your colleagues to hazardous electrical situation.
7. Unauthorized person(s) shall not be allowed in a laboratory for any reason.
8. Never open (remove cover) of any equipment in the laboratories. Never ‘jump’, disable,
bypass or otherwise disengage any safety device or feature of any electrical equipment in
the laboratories.
9. Working alone unsupervised in laboratory is forbidden.
10. Do not touch/operate electrical equipment UNLESS under direct supervision of instructor
or qualified personnel.
11. Never operate any of the electrical equipment/tools with WET hands or body.
12. Never run the experiments when you are sleepy or under medication.
13. Ensure that the switches are turn off and unplug from the socket after each experiment.
14. Tidy up and place the electrical equipment, tools and components back to their original
place after each experiment.
15. Notify your instructor immediately of any danger, accident or possible risk.
 STUDENT CONDUCT & LABORATORY REPORT
SUBMISSION

1. Sign in the attendance sheet.

2. Student coming in 20 minutes after laboratory session has started will be considered
ABSENT.

3. Student is subject to 80% ruling of attendance. Failing to achieve 80% of attendance

will cause a student to be BARRED from submitting the report and student shall
RETAKE this module.

4. Each and every data acquired by the student during laboratory session MUST BE
ACKNOWLEDGED by the instructor (stamped or signed).

5. FAILING TO ADHERE ANY OF THE LABORATORY REGULATIONS

STATED HEREWITH, NO MARK WILL BE AWARDED TO THE
STUDENT.

6. All coursework MUST be submitted in accordance with the due date indicated on the
lab manual.

7. Late submission:
a) a deduction of 10% of the maximum mark available from the actual mark
achieved by the student shall be imposed upon expiry of the deadline;

b) a further deduction of 5% of the maximum mark available from the actual mark
achieved by the student shall then be imposed on each of the next subsequent
working days;

c) any piece of work submitted 10 or more days after the expiry of the deadline will
not be marked but will be assigned a mark of zero and deemed to be a non-
submission;

8. Mitigating Circumstances: If there are any exceptional circumstances proof which

may have affected your ability to undertake or submit this lab report, please make
sure you contact the lecturer responsible.

9. IT IS YOUR RESPONSIBILITY TO KEEP A RECORD OF ALL WORK

SUBMITTED.

10. Work MUST be submitted to the member of academic staff responsible for setting
your work.
 LAB REPORT FORMAT

1. Cover Page

2. Marking Assessment & Marker’s Feedback

3. Rubric 1: Marking Scheme – Lab Practical (3 copies)

4. Rubric 1: Marking Scheme – Lab Report

5. Introduction / Theoretical Principles

6. Experimental Procedure

7. Result

8. Discussion

9. Conclusion

10. Reference

*All report must be written in font type Times New Roman, size 12 only.

*Bold style is only allowed for the words listed above.

 SEGi University

Bachelor of Electrical and Electronics Engineering

EEE3401 LAB INVESTIGATION I

Experiment Title:

Lecturer :
Group Members: 1)
2)
3)
Submission Form Hardcopy: Yes/ No Softcopy: Yes/No

Declaration
We/ I declare that this material, which we/I now submit for assessment, is entirely our/my
own work and has not been taken from the work of others, save and to the extent that such
work has been cited and acknowledged within the text of my work. We/I understand that
plagiarism, collusion, and copying are serious in the university and accept the penalties that
would be imposed should we/I engage in plagiarism, collusion or copying.

Student Signature : 1)

2)

3)

Date of Submission:
 MARKING & ASSESSMENT

Marks Awarded
Marks
Marking Scheme Student 1: Student 2: Student 3:
Available

See Rubric 1 (Attached) –

20
Lab Practical.

See Rubric 2 (Attached) – 80

Lab Report.

Marks Awarded 100

MARKER’S FEEDBACK

Lecturer’s Comments:

……………………………………………………………………………………………………………

……………………………………………………………………………………………………………

Lecturer’s signature: Date:

All marks are subject to confirmation by the Board of Examiners

 Rubric 1: Marking Scheme – Lab Practical (Individual)

Categories Score Score Awarded

Process Skills 1 2 3 4 Student 1: Student 2: Student 3:

P art 1/5  Set-up of equipment is not  Set-up of equipment is  Set-up of equipment is  All set-up of equipment
Set-up and accurate. generally workable with generally accurate with accurately placed and
Equipment  Unprepared, major assistance several helps that need few that need workable.
Care is required. refinement. refinement.

P art 2/5  Lacks the appropriate  Demonstrates general  Demonstrates sound  Demonstrates very
Experiment knowledge of the knowledge of experiment knowledge of the good knowledge of
Procedure experiment procedures. procedures. experiment procedures. experiment procedures.
 Unaware, requires major  Little initiative to mitigate  Good initiative to  Strong initiative,
assistance even for basic procedural problems, resolve procedural helpful /supportive
procedures. requires several problems, requires minor throughout experiment
assistances. assistances. procedures.

P art 3/5  Measurements are  Measurements having  Measurements are  Measurements are both
Data incomplete, inaccurate and several errors. mostly accurate with accurate and precise.
Collection imprecise.  Relationship observations reasonable  Relationships
 Relationship observations are recorded in a confusing precision. observations are
are incomplete or not way.  Relationship thorough and clear.
recorded.  Some redo/retake of observations are  Work is neat and
 Major redo/retake of measurement is required. generally comply. organized.
measurement is required.  Work is generally
organized.
P art 4/5  Proper safety precautions are  Proper safety precautions  Proper safety  Proper safety
Safety consistently missed. are often missed. precautions are generally procedures are
Compliance  Often needs to be reminded  Needs to be reminded more used. consistently used.
during the lab. than once during the lab.  May need to be  Uses general reminders
reminded once during of safe practices
the lab. independently.
P art 5/5  Poor clean-up  Needs to be reminded  Proper clean-up  Consistently uses
Attitude and awareness, often requires during the lab of the proper acceptable although may proper clean-up
Clean-up help to complete clean- clean-up procedures. need some help on procedures, station
Awareness up.  Fair cooperation with occasion to complete generally neat and
 Poor cooperation with group group members. tasks. clean.
members.  Good cooperation with  Excellent cooperation
group members. with group members.

TOTAL MARKS
 Rubric 2: Marking Scheme – Lab Report (Group)
Categories
2 4
P art 1/7 Very little background
information provided or
Introduction/
information is incorrect.
theoretical/
principles
P art 2/7 Missing several
important experimental
Experimental
details or not written in
procedure
order.
P art 3/7 Figures, graphs, tables
contain errors or are
Results:
poorly constructed, have
data, figures,
missing titles, captions or
graphs, tables, etc.
numbers, units missing or
incorrect, etc.
P art 4/7 Very incomplete or
incorrect interpretation of
Discussion
trends and comparison of
data indicating a lack of
understanding of results.
Total Marks: /80
Score Weight- Total Score
age (Weightage x
Score)
6 8
Some introductory Introduction is nearly Introduction complete and
information, but still complete, missing some well-written; provides all
missing some major minor points. necessary background
1.5
points. principles for the
experiment.
Written in rough order Written in good order, Well-written procedures,
but readable, still important experimental all experimental details are
missing some important details are covered, some covered. 0.5
experimental details. minor details missing.
Most figures, graphs, All figures, graphs, tables All figures, graphs, tables
tables OK, some still are correctly drawn, but are correctly drawn, are
missing some important some have minor numbered and contain
or required features problems or could still be titles/captions. 3
improved.
Some of the results have Almost all of the results All important trends and
been correctly have been correctly data comparisons have
interpreted and interpreted and discussed, been interpreted correctly
discussed; partial but only minor improvements and discussed, good
3
incomplete are needed. understanding of results is
understanding of results conveyed.
is still evident.
P art 5/7 Conclusions missing or Conclusions regarding All important conclusions All important conclusions
missing the important major points are drawn, have been drawn, could have been clearly made,
Conclusions
points. but many are misstated, be better stated. student shows good
1
indicating a lack of understanding.
understanding.

P art 6/7 Sections out of order, Sections in order, All sections in order, All sections in order, well-
sloppy formatting. formatting is rough but formatting generally good formatted, very readable.
Appearance and
readable. could still be improved.
formatting

Frequent grammar and/or Occasional Less than 30% All grammar/spelling

0.5
spelling errors, writing grammar/spelling errors, grammar/spelling errors, correct and very well-
Spelling, grammar
style is rough and generally readable with mature, readable style. written.
and sentence
immature. some rough spots in
structure
writing style.

P art 7/7 No references provided. References provided are References provided are References are in order
incomplete, confusing in order, formatting and well formatted.
References
format. generally good but could 0.5
still be improved.

TOTAL MARKS
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS 1

EXPERIMENT 1: OHM’S LAW AND KIRCHHOFF’LAWS

10.1 OBJECTIVE
i. The purpose of this lab experiment is to verify Ohm's Law using resistor in a dc circuits.
ii. To become familiar with series and parallel circuits
iii. To become familiar with the application of kirchhoff’s laws

2.1 THEORY/INTRODUCTION

Ohm’s law discovered by German physicist Simon Ohm (1787 – 1854) is an important law
that describes the relationship of voltage V to current I and resistance R. It is often referred to
as the foundation of circuit analysis and can be expressed by three different ways:

where ‘V’ is the potential difference from one end of a resistance element to the other, in volt.

‘I’ is the current through the same resistance element in amperes.

‘R’ is the resistance of the same element, in ohms.

There are many circuits that are so complex that they cannot be solved by Ohm’s Law.
These circuits have many branches or many power sources, and Ohm’s Law would be either
impractical or impossible to use on them. Methods for solving complex circuits have been
developed, and are based on the experiments of a German physicist, Gustav Kirchhoff. About

14
1857, Kirchhoff developed two conclusions, known as Kirchhoff’s Laws, can be stated as
follows:

i. Kirchhoff’s voltage law

Kirchhoffs voltage law is also known as his first law. It is stated that the sum of the voltage
drops around any closed loop is equal to the sum of the emfs in that loop. It gives the
relationship between the voltage drops around any closed loop in a circuit and the voltage
sources in that loop. The totals of these two quantities are always equal. This can be given in
equation form as: E = ∑IR, where the symbol ∑, which is the Greek letter sigma, means “the
sum of.”

ii. Kirchhoff’s current law

Kirchhoff’s current law is called his second law. It is stated that the current arriving at any
junction point in a circuit is equal to the current leaving that point. Current cannot collect or
build up at a point. Thus, if 1A of current arrives at a junction that has two paths leading
away from it, the 1A will divide among the two paths, but the total 1A must leave the
junction. This can be given in equation form as: ∑Iin - ∑ Iout = 0 or ∑Iin = ∑ Iout. Normally,
Kirchhoff’s current law is not used by itself, but together with the voltage law in solving a
circuit problem.

3.0 APPARATUS
Table 1: Apparatus Setting for Section 4.1

S.NO COMPONENTS RATING QUANTITY

1. Ammeter Multimeter 1
2. Voltmeter Multimeter 1
1
3. Variable Power supply 0-30 V, DC 1
4. Resistance R1=….. R2=….. 1
5. Breadboard - 1
6. Connecting Wires - Few

15
 Table 2 Apparatus Setting for Section 4.2

S.NO COMPONENTS RATING QUANTITY

1. Ammeter Multimeter 2
2. Voltmeter Multimeter 2
3. Variable Power supply 0-30 V, DC 1
4. Resistance R1=….. R2=….. 2
5. Breadboard - 1
6. Connecting Wires - Few

4.1 PROCEDURES
4.2 Experiment 1: Ohm’s Law

1. Using ohmmeter, measure and record the value of resistance R1 in Table 3.

2. Connect the circuit as shown in Figure 1.

Figure 1

3. The voltmeter is connected across R1 resistor and an ammeter is connected in series

with the resistor R1.
4. Switch on the dc power supply and for different values of input voltage, E; find the
voltage (V) across R1 and current (I) through R1.
5. Record the readings in Table 3.
6. Repeat the same procedure using a different value of resistor.

Note: If the student is using multimeter instead of voltmeter or ammeter or ohmmeter,

make sure that the leads are correctly set for required measurement and rating.
The value of R1 is differs for different groups.

4.3 Experiment 2: Kirchhoff’s Law

1. Using ohmmeter, measure and record the value of resistance R1 and R2 in Table 4 .
2. Connect the circuit as shown in Figure 3.

Figure 3

3. Switch on the dc power supply.

4. For a given value of R1 and R2, record the readings (VT, V1, V2 and I) in the Table 4.
5. Check whether RT = R1 + R2 for a series circuit.
6. Check whether VT = V1 + V2 (Kirchhoff’s voltage law verification).
7. Repeat the same procedure by setting a different value of resistor R2.
8. Using ohmmeter, measure and record the value of resistance R1 and R2 in Table 5.
9. Connect the circuit as shown in Figure 4.

Figure 4
 10. Switch on the dc power supply.
11. For a given value of R1 and R2, record the readings (VT, V1, V2, I1, I2 and I) in the table
5.

12. Check whether RT R1  R2

for a parallel circuit.
= R1  R2
13. Check whether IT = I1 + I2 (Kirchhoff’s current law verification).
14. You can also check if voltage across parallel resistor is same.
15. Repeat the same procedure by setting a different value of resistor R2.
Note: If the student is using multimeter instead of voltmeter or ammeter or ohmmeter,
make sure that the leads are correctly set for required measurement and rating.

The value of R1 is differs for different groups.

5.1 RESULTS
Table 3: Data for Verification of Ohm’s Law for Figure 1

CURRENT(A)
RESISTOR(Ω) VOLTAGE(V)
Practical value Theoretical value

R1 =...........Ω 4V

8V

12V

15V

R2 = …….Ω 4V

8V

12V

15V

i. Students are expected to calculate the error for experimental values.

ii. Prepare a graph with voltage vs. current.
 Table 4: Study of Resistors in Series and Kirchhoff’s Voltage Law

RT VT
R1() R2() V1 (V) V2(V) I(A)
P T P T

Table 5: Study of Resistors in Parallel and Kirchhoff’s Current Law

RT IT
R1() R2() V1 (V) V2 (V) VT I1 (A) I2 (A) I (A)
P T P T

Students are expected to do the Theoretical(T) calculations

6.1 DISCUSSION
i. Compare the theoretical and practical values in Table 3, 4 and 5.
ii. From the plotted graph, establish the relationship between voltage and current with
explanation .
iii. Comment on the accuracy of the experiment and ways of improving it.
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS 1

EXPERIMENT 2:
AMPLITUDE SHIFT KEYING (ASK) MODULATION & DEMODULATION

OBJECTIVES
1. To demonstrate the concept of amplitude modulation and demodulation.
2. To identify Binary ASK modulation principles and its realization methods.
3. To identify Binary ASK demodulation principles and its realization methods.

EQUIPMENTS
1. Digital Communication Training System (Scientech 2137)
2. Dual trace Oscilloscope for external signal analysis on mimic.

THEORY
Amplitude-Shift Keying (ASK) or Binary Digital Amplitude Modulation (BDAM) or On Off
Keying (OOK) is a form of modulation that represents digital data as variations in the
amplitude of a carrier wave. The amplitude of an analog carrier signal varies in accordance
with the bit stream (modulating signal), keeping frequency and phase constant. The level of
amplitude can be used to represent binary logic 0s and 1s. We can think of a carrier signal as
an ON or OFF switch. In the modulated signal, logic 0 is represented by the absence of a
carrier, thus giving OFF/ON keying operation and hence the name given. Mathematically

20
ASK is given by:

20
In the above equation, the modulating signal (vm(t)) is a normalized binary waveform, where
+1V = logic 1 and -1V = logic 0. Therefore, for logic 1 equation reduces to:

for logic 0 equation reduces to:

Thus the modulated wave vask(t) , is either [ A cos(ωct )] or 0. As shown in the waveform
diagram below.

Waveform of ASK modulation

21
Block diagram of ASK transmitter

Transmitter

Receiver: The incoming modulated ASK signal is multiplied with the sine signal generated
from the NCO. The output of the multiplier contains high (fin – fnco) and low (fin + fnco)
frequency components. The high frequency components are filtered out by the low pass
filters (called as Arm filters). The output of low pass filter will resemble the input data for
modulation. With the help of thresh hold detector (decoder) input signal is received.

Receiver
Test Point Detail

Transmitter:
TP1 : Serial Data Input for modulation.
TP2 : Data Sampling Clock for Transmitter (bit clock).
TP11 : Sine Carrier.
TP17 : ASK modulated signal from transmitter.

Receiver:
TP18 : Sine NCO.
TP22 : Multiplied result of modulated signal with receiver sin NCO.
TP23 : Low Pass Filter output for Multiplied result of modulated signal with
receiver sin NCO.
TP32 : Data Sampling Clock for Receiver.
TP33 : Serial Data output after demodulation.

PROCEDURE
1. Connect power supply and switch on .make sure that led for power supply should glow.
2. Select ASK modulation from home window on touch panel LCD.
3. Touch on enter button on LCD.
4. Now we can see the block diagram of ASK transmitter/receiver along with test point for
the corresponding signal from modulation to be analyzed.
5. Select test point for signals which you want to analyze on MSO for eg:-select test point 1,
2, 11, 17, 32, 33. Then touch on MSO button and analyze the signal for the test points you
have selected.
6. Adjust the settings according to your need using menu button and mimic control.
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS

EXPERIMENT 3: VERIFICATION OF LOGIC GATES

1.1 OBJECTIVE
To study and verify the truth table of logic gates

1.2 INTRODUCTION

The basic logic gates are the building blocks of more complex logic circuits. These logic
gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion,
Exclusive- OR. Each gate has one or two binary inputs, A and B, and one binary output, C.
The small circle on the output of the circuit symbols designates the logic complement. The
AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can
be extended to have multiple inputs if the binary operation it represents is commutative and
associative.

The voltage in a digital circuit is allowed to be in only one of two states: HIGH or LOW.
HIGH is taken to mean logical (1) or logical TRUE. LOW is taken to mean logical (0) or
logical FALSE. In the TTL logic family, the “ideal” HIGH and LOW voltage levels are 5 V
and 0 V but any output voltage in the range 2.7 to 5.0 V is interpreted as HIGH, and any
output voltage in the range 0 to 0.4 V as LOW. Voltages outside this range are undefined, and
therefore “illegal,” except if they occur briefly during transitions.
Figure 1: TTL Output Voltage Level

7486
1.3 APPARATUS

a. Power Supply
b. Digital IC 7404 (NOT gate), 7408 (AND gate), 7432 (OR gate), 7400 (NAND
gate), 7402 (NOR gate) and 7486 (X-OR gate)
c. Multimeter
d. Some connecting wires.

1.4 PROCEDURES
a. Connect the Vcc and GND to the power supply accordingly
b. You are required to apply various combinations of input according to the truth
table designated for each logic gates based on the datasheet provided.
c. State the voltage reading using the multimeter in the output column for these
various combinations of inputs

1.5 RESULT

NOT GATE (7404)

INPUT OUTPUT
A Volt Logic
0
0

AND GATE (7408)

INPUT OUTPUT
A B Volt Logic
0 0
0 1
1 0
1 1
 OR GATE (7432)
INPUT OUTPUT
A B Volt Logic
0 0
0 1
1 0
1 1

NAND GATE (7400)

INPUT OUTPUT
A B Volt Logic
0 0
0 1
1 0
1 1

NOR GATE (7402)

INPUT OUTPUT
A B Volt Logic
0 0
0 1
1 0
1 1

X-OR GATE (7486)

INPUT OUTPUT
A B Volt Logic
0 0
0 1
1 0
1 1
1.6 DISCUSSION
a. Explain in details your observation to both digital output tables as tabulated in
your results.
b. Compare your results with the theoretical values and discuss the possibilities of
result discrepancies.

1.7 CONCLUSION
a. Conclude on the logic output comparison between the theoretical and the practical
data.
b. Comment on the accuracy of the experiment and ways of improving it.

1.3 REFERENCES
a. Thomas L. Floyd, 2009, Digital Fundamentals, 10th Edition, Pearson Hall, -
Chapter 3 on Boolean Algebra and Logic Simplification, pp. 40 – 50.
b. Tocci & Widmer, 2007, Digital Systems Principles and Applications, 10th Edition,
Prentice Hall.
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS 1

EXPERIMENT 4: SUPERPOSITION THEOREM (OPEN-ENDED LAB)

1.0 OBJECTIVE:

To verify superposition theorem.

2.0 INSTRUCTION:

For Figure 1:

(a) Construct the circuit (with ammeter and voltmeter placed properly) to find the current
through RL and voltage across RL.

(b) Construct the circuit to verify your results using superposition theorem.

Figure 1

3.0 RESULT AND DISCUSSION:

(a) Provide a record of the data obtained during the experiment. Data should be retrieved
from the experiment conducted and presented in a clear manner using tables.
(b) Compare the theoretical and practical values. Comment on the accuracy of the experiment
and ways of improving it.
(c) Discuss how well the superposition theorem is satisfied.
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS 1

EXPERIMENT 5: FSK MODULATION AND DEMODULATION (OPEN ENDED)

OBJECTIVES

1. To demonstrate the concept of frequency shift keying modulation (FSK) and

demodulation.
2. To identify FSK modulation principles and its realization methods.
3. To identify FSK demodulation principles and its realization methods.

EQUIPMENT
1. Digital Communication Training System (Scientech 2137)
2. Dual trace Oscilloscope for external signal analysis on mimic.

INSTRUCTION:

1. Based on the previous ASK experiment, demonstrate the FSK modulation and
demodulation using the equipment above.

2. Set you own parameter and constraints of the experiment.

3. Discuss the principle of modulation and demodulation based on the experiment

performed.

30
 FACULTY OF ENGINEERING & BUILT ENVIRONMENT

SUBJECT: EEE3401 LABORATORY INVESTIGATIONS 1

EXPERIMENT 6: DESIGN OF LOGIC CIRCUIT (OPEN-ENDED LAB)

1.0 OBJECTIVE:

To design a combinational logic circuit with simplification techniques.

2.0 INSTRUCTION:

In a 7-segment display, each of the seven segments is activated for various digits as shown

below:

Figure Q1

Since each digit can be represented by a BCD code, design the logic circuit for segment a.

3.0 RESULT AND DISCUSSION:

Show all of the necessary steps in designing the simplest logic circuit using all techniques
learned during lectures.

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