FORM LD-1 APPLICATION FOR REGISTRATION OF LAYOUT-DESIGN [Section 8(1). Rule 22] (to be filed in triplicate) Application is hereby made forthe registration of layout-design’ in the name(s) of: — whose address(s)’ is claim(s) to be the proprietor thereof in respect ofthe said layout-design. Endorsed herowith is the duly completed Statement of Particulars relating tothe ayout-design ‘The particulars set forth in the enclosed Statement of Particulars are true to the best of my/our knowledge, information and belie, Dated this day of ———20—. To ‘The Registrar Semiconductor Integrated Circuits Layout-Design, Office of the Semiconductor Integrated Circuits Layout-Design Registry a’ T Title of the layout design. 2. Insert legibly the full name, description and nationality of the applicant, incorporation or the names and description ofthe partnen camposing the fr and the nature of regitation, if any, should be stated. See rule 15, 13. The applicant must sate the adress of his principal place of busines in Indi, if any. See rules 3 and 16, 44, Signatue ofthe applicant or his agent (egal praitoner or registered Iayout~design agent or person inthe sole and regular employment of the applicants. ce section 84). 5. State the name of the place of the appropriate office of the Semiconductor Integrated Cireuits Layout-Design Repistry. See rule 4 46. Layout design drawings should be preferably on a paper of size 3-centimeter by 20-centimeter. the case of « body corporate or firm the country of the eae may be, Statement of Particulars (Refer Form LD-1) Application No. (to be filled in by the Semiconductor Integrated Circuits Layout-Design Registry): 2. Title of the layout-design 3. Classification of the semiconductor integrated circuit which can be manufactured using the layout-design @ Structure' @ Technique? i) Function? Brief description of the layout-design S. Whether the layout-design has been commercially exploited [ Yes /No] . I yes, then in Place / Country on Dated this day of ———— Year— 6 Documents enclosed @ Drawings! photograph (three sets) @ Semiconductor integrate circuits pecs) [Where an Integrated Circuit (IC) has been made using layout-design applied for registration] (ii) Details of the fees deposited (i) Others 7. Nameand address ofthe agent & Others, ifany implies ike Bipolar, MOS, BicMOS, Optical IC, Othe (specify) ie giving techique details like TTL, DTL, CMOS, NMOS, PMOS, Other (epacity) ics giving functional deals ke Logie, Memory, Linear, Microcomputer. Other (specify) Siete oft spn tae pl pcre yon pr porn the le nd eae of the applicant. See section 84.)