PD - 95369A

IRFR2405PbF
IRFU2405PbF
l Surface Mount (IRFR2405) HEXFET® Power MOSFET
l Straight Lead (IRFU2405)
l Advanced Process Technology D
l Dynamic dv/dt Rating VDSS = 55V
l Fast Switching
l Fully Avalanche Rated RDS(on) = 0.016Ω
l Lead-Free G
Description ID = 56A†
Seventh Generation HEXFET® Power MOSFETs from S
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications.

The D-Pak is designed for surface mounting using

vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through- D-Pak I-Pak
hole mounting applications. Power dissipation levels
IRFR2405 IRFU2405
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 56†
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 40† A
IDM Pulsed Drain Current  220
PD @TC = 25°C Power Dissipation 110 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 130 mJ
IAR Avalanche Current 34 A
EAR Repetitive Avalanche Energy 11 mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.4
RθJA Junction-to-Ambient (PCB mount)* ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
* When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to application note #AN-994
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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.052 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.0118 0.016 Ω VGS = 10V, ID = 34A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 30 ––– ––– S VDS = 25V, ID = 34A
––– ––– 20 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 70 110 ID = 34A
Qgs Gate-to-Source Charge ––– 16 23 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– 19 29 VGS = 10V„
td(on) Turn-On Delay Time ––– 15 ––– VDD = 28V
tr Rise Time ––– 130 ––– ID = 34A
ns
td(off) Turn-Off Delay Time ––– 55 ––– RG = 6.8Ω
tf Fall Time ––– 78 ––– VGS = 10V „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact S

Ciss Input Capacitance ––– 2430 ––– VGS = 0V

Coss Output Capacitance ––– 470 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 100 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 2040 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 350 ––– VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 350 ––– VGS = 0V, VDS = 0V to 44V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 56†
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 220

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 34A, VGS = 0V „
trr Reverse Recovery Time ––– 62 93 ns TJ = 25°C, IF = 34A
Qrr Reverse RecoveryCharge ––– 170 260 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature.
… Coss eff. is a fixed capacitance that gives the same charging time
‚ Starting TJ = 25°C, L = 0.22mH as Coss while VDS is rising from 0 to 80% VDSS
R G = 25Ω, IAS = 34A.
† Calculated continuous current based on maximum allowable
ƒ ISD ≤ 34A, di/dt ≤ 190A/µs, VDD ≤ V(BR)DSS, junction temperature. Package limitation current is 30A
TJ ≤ 175°C

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1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V

I D , Drain-to-Source Current (A)

8.0V
I D , Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V

100 100

4.5V

4.5V
20µs PULSE WIDTH 20µs PULSE WIDTH
TJ = 25 °C TJ = 175 ° C
10 10
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 56A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

2.0

TJ = 25 ° C
(Normalized)

1.5
TJ = 175 ° C
100

1.0

0.5

V DS = 25V
20µs PULSE WIDTH VGS = 10V
10 0.0
4.0 5.0 6.0 7.0 8.0 9.0 10.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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4000 20
VGS = 0V, f = 1MHz ID = 34A
Ciss = Cgs + Cgd , Cds SHORTED VDS = 44V
Crss = Cgd

VGS , Gate-to-Source Voltage (V)

VDS = 27V
3200 Coss = Cds + Cgd 16 VDS = 11V
C, Capacitance (pF)

Ciss
2400 12

1600 8

800 Coss 4

Crss FOR TEST CIRCUIT

SEE FIGURE 13
0 0
1 10 100 0 20 40 60 80 100
VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ISD , Reverse Drain Current (A)

ID , Drain Current (A)

10us
100 100
TJ = 175 ° C

100us
TJ = 25 ° C
10 10
1ms

TC = 25 ° C 10ms
TJ = 175 ° C
V GS = 0 V Single Pulse
1 1
0.4 0.8 1.2 1.6 2.0 2.4 1 10 100
VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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60
RD
V DS
LIMITED BY PACKAGE
VGS
50 D.U.T.
RG
+
-VDD
I D , Drain Current (A)

40
VGS
Pulse Width ≤ 1 µs
30 Duty Factor ≤ 0.1 %

20 Fig 10a. Switching Time Test Circuit

VDS
10
90%

0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

1
D = 0.50

0.20

0.10
PDM
0.1 0.05
SINGLE PULSE t1
0.02
0.01 (THERMAL RESPONSE) t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U2405OPbF

240
ID

EAS , Single Pulse Avalanche Energy (mJ)

15V

TOP 14A
200 24A
L DRIVER BOTTOM 34A
VDS

160
RG D.U.T +
V
- DD
IAS A
120
20V
tp 0.01Ω

80
Fig 12a. Unclamped Inductive Test Circuit

40

V(BR)DSS 0
tp
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( °C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
I AS

Fig 12b. Unclamped Inductive Waveforms

Current Regulator
QG Same Type as D.U.T.

50KΩ
QGS QGD 12V .2µF
.3µF

+
V
D.U.T. - DS
VG
VGS

3mA
Charge
IG ID
Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T
• Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test

Driver Gate Drive

P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFET® Power MOSFETs

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D-Pak (TO-252AA) Package Outline

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: T HIS IS AN IRF R120
PART NUMBER
WIT H AS S EMBLY INT ERNAT IONAL
LOT CODE 1234 RECT IFIER IRFU120 DAT E CODE
AS S EMBLED ON WW 16, 1999 LOGO 916A YEAR 9 = 1999
IN T HE AS S EMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in ass embly line position AS S EMBLY
indicates "Lead-F ree" LOT CODE

OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER IRF U120 DAT E CODE
LOGO P = DES IGNAT ES LEAD-F REE
PRODUCT (OPT IONAL)
12 34
YEAR 9 = 1999
AS S EMBLY WEEK 16
LOT CODE
A = AS S EMBLY S IT E CODE

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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: T HIS IS AN IRFU120 PART NUMBER
INTE RNAT IONAL
WIT H ASSEMBLY
RECT IF IER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 919A YEAR 9 = 1999
ASSE MBLE D ON WW 19, 1999
56 78 WEEK 19
IN T HE ASSEMBLY LINE "A"
LINE A
ASSEMBLY
Note: "P" in ass embly line
LOT CODE
pos ition indicates "Lead-Free"

OR
PART NUMBE R
INT ERNAT IONAL
RECTIF IER IRFU120 DATE CODE
LOGO P = DES IGNAT ES LEAD-F REE
56 78 PRODUCT (OPTIONAL)
YEAR 9 = 1999
AS SEMBLY WE EK 19
LOT CODE A = ASS EMBLY SIT E CODE

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D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/