LFSR USING CDFF AND GDI

1
Kiruthiga S,
2
Rajesh Kumar S P, 3Shangeeth M, 4Sowndarya R.

1
Associate professor, Department of ECE, Sri Krishna College of
Technology,kiruthiga261992@gmail.com
234
UG Student, Department of ECE, Sri Krishna College of Technology,
16tuec208@skct.edu.in,16tuec220@skct.edu.in,16tuec235@skct.edu.in

ABSTRACT: A new design of the Linear-face shift

register (LFSR) using the Gate-Diffusion-Input (GDI)
and the conditional discharge flip-flop (CDFF) technique
is discussed. This method results in efficient result
parameters such as low power, reduced area and
minimum usage of transistor than conventional
techniques. Performance comparison with other LFSR
designing techniques is presented, with respect to the
above parameters. The resultant bits from LFSR are
usually sampled for n-bit random number generation.
Most importantly complexity of the design is very simple.
With the proposed LFSR architecture, the average power
consumed is saved up to 33%. Implementation techniques Fig 1 : GDI CELL
and net results are produced with Tanner EDA tool.
The internal switching activities are reduced by
Keywords: LFSR, CDFF, GDI. using CDFF method [7]. Reason to choose CDFF in
designing a flip-flop is discussed as a comparison in the
INTRODUCTION following Table 1 ,
In the view of generating a pseudo-random pattern,
LFSR is foremost. Linear Feedback Shift Register has input
bit as a linear function of previous state output. A
combination of flip-flop and XOR gate is the conventional
way of implementing LFSR, the changes made to the
existing methods and its advancements are discussed here.
To discuss other methods of implementation, GDI stands
unique for its minimized number of transistors. Size is the
most considerable parameter in the eyes of VLSI devices,
Gate Diffusion Input is one of the impressive technique in
the aspect of the size of transistor and area. It is an
alternative for logic design in standard CMOS and SOI
technologies. Structure of GDI are discussed below, where
Fig1 discuss some logic functions that can be implemented
with a single GDI cell [8].

Table-1: COMPARISION OF CDFF WITH

OTHER TECHNOLOGIES
 In this discussion, a new implementation of the GDI
and CDFF based DFF technique is explained. This
unconventional design allows reducing power-delay product
and area of the circuit, with low complexity in the design
flow. This technique is compared with other design
techniques on aspects like the gate area, the number of
transistors, delay, and power dissipation. As a result, it is
shown either technique is practically possible with all good
deeds discussed above. Structure of LFSR, CDFF and GDI
are discussed below, where Table 2 explains some logic
functions that can be implemented with a single GDI cell [8].
Table 2: FUNCTIONS OF SINGLE CELL GDI
LITERATURE SURVEY
The model for the power optimization of the linear feedback
shift register (LFSR) for low power BIST implementation in
a hardware description language (HDL). They used an LFSR
based pseudo-random test pattern generator for the testing of
ASIC chips that generates a sequence of test patterns [2]. The
model for the study and analysis of various LFSR
architectures. They used CMOS, GDI (Gate Diffusion
Input), MGDI (Modified Gate Diffusion Input), and
MTCMOS (Multi-threshold CMOS) techniques in cadence
virtuoso for the implementation of LFSR which employed in
low power testing. These techniques provide low
complexity, delay, and reduction in area [3]. The model for
low power implementation of Linear feedback shift register
(LFSR). This low power LFSR used for pseudo-random
sequence generation, encryption and decryption of the
systems [4].
The model for test power a wire STUMP (Self Testing
Using MISR and parallel SRSG) BIST. They proposed the
architecture of low test power BIST which reduces the test
power by 56% with area overhead of 1% [5]. The design
and analysis of LFSR based on various tap connections.
They used LFSR for the production of a pseudo-random
pattern for the SOC testing. They used Xilinx vertex-6
FPGA for the reduction of volume and area [6]. The model
suggested methods for low power operations in FPGA
based system design which have produced a high speed
design architecture with overall lower logical chip area
consumption [9].
EXISTING METHOD:
LFSR is a combination of flip flops and XOR gates. In
the design of LFSR, it looks like a chain where the output of one
flip flop is fed as input to the following flip flop and the chain
continues. Depending on the characteristic polynomial, the
circuit has been designed to yield the required diffused bits as
output. The feedback delay which determines the operating
speed of an LFSR depends on the delay of the XOR gate. The
characteristic polynomial determines the number of XOR gates.
LFSR with complex polynomial will result in more number of
XOR gates which end up with a high delay [1]. Characteristic
polynomial x8 + x7 +x3 + x2 + 1 is shown in Fig 2.
Fig 2: 8 bit LFSR
PROPOSED METHOD
In general, LFSR is combination of flip-flop and XOR
gate. Our proposed system is a combination of GDI and CDFF
techniques as discussed earlier. XOR gate is implemented using
GDI and flip-flop is implemented using conditional discharge
technology.
XOR USING GDI As a result, the output node will be charged to HIGH in the
second stage.
In VLSI design, GDI is power and area minimizing HIGH-to-LOW input transition is capture in Stage 2. If
technique. GDI implements functions using at most two LOW input is fed during the sampling period, this shows the first
MOS transistors. The simplest GDI cell contains three input: stage is disabled, and pre charge state is continued in
G is the common input to the gate of nMOS and pMOS, P is intermediate node. As the result, final node will be HIGH and in
feed to the source of pMOS, and N is feed to the source of the sampling period, the discharge path in the second stage will
nMOS as shown in Fig 3. In GDI bulk of pMOS and nMOS be enabled, allowing the output node to discharge and to
are connected to P or N terminals rather than to GND and correctly capture the input data. Fig 4, shows the simple
VDD. The main reasons for GDI are simpler gates, reduced implementation of a flip flop [7].
number of transistors and lesser power dissipation. Fig 3
displays implementation of the XOR gate using GDI logic. It
consists of a body gate and an inverter. The body gate is
controlled by one input and the bulk of pMOS is tied to the
other input signal, while the bulk of nMOS is connected to
the output of inverter section nMOS. Clock signal fed to
body gates determines the state of the circuit. Clock creates
two alternative paths, to hold the states of the latch and
transparent state. Inverters complement the values to input
and they buffer internal signals for swing restoration. With
respect to the preset input initial value of LFSR is set. This
technique has lesser power dissipation, area, and power delay
[3].

Fig 4: Flip flop using CDFF

SIMULATION RESULT

Fig 3: XOR USING GDI In this design the proposed LFSR with conditional
discharge flip flop (CDFF) and gain diffusion input (GDI) based
FLIPFLOP USING CDFF XOR gate is analyzed in the T-spice.

Conditional discharge flip-flop (CDFF) has two
stages, responsibility for capturing the LOW-to-HIGH
transition is taken by stage one. In the sampling window if
the input is HIGH, the internal node is discharged, assuming
that were initially (LOW, HIGH) for the discharge path
to be enabled.
The conditional discharge flip flop consumes
5.170142e-005 watts and the proposed LFSR consumes
1.382332e-004 watts. The waveform results are shown in the
following Fig 5, proposed LFSR architecture and Fig 6, the
conditional discharge flip flop (CDFF).
 CONCLUSION

The efficient power consumption of LFSR is

achieved through conventional discharge flip flop and gain
diffusion input based XOR gate. This proposed model is
33% efficient in power consumption to that of normal LFSR
architecture. Using this model the many applications like
generation of pseudo random sequences can be achieved
with low power consumption architecture. Table 3 shows
the comparison of the basic design of normal LFSR and the
proposed LFSR model.

MODEL Average power

consumption
D flip flop 5.264883e-005 watts
Proposed CDFF 5.170142e-005 watts
LFSR 4.117074e-004 watts
Proposed LFSR 1.382332e-004 watts

Table 3: Power consumption of each model

Fig 5: Proposed LFSR simulation REFERENCES

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