RISC-V Quick Reference

COSC 130
Stephen Marz
RISC-V Tools
• All tools are in:
• /home/smarz1/Programs/riscv/bin
• This needs to be added to your PATH
Assembling and Compiling
riscv64-g++ –o <output> <source1> … <sourceN>

Example: riscv64-g++ –o test test.cpp test.S

--Assembles test.S, compiles test.cpp, and links into
executable test
NOTE

-Source can be a .c file (C code)

-Source can be a .cpp file (C++ code)
-Source can be a .S file (Assembly code)
-Source can be a .o file (Object code)
-You can mix-and-match sources!
 RISC-V is
Little Endian
Data Types
Type Size Assembler Directive
Integral 1 (char) .byte
2 (short) .half
4 (int) .word
8 (long) .dword
Floating-Point 4 (float) .float
8 (double) .double
Manually encoded instruction 4 (int) .word
String (NOT 0-terminated) 1 (char) .ascii
C-Style string (0 terminated) 1 (char) .asciz
Data Instructions
Operation Instruction Action
Move add Rd, Rm, zero Rd := Rm
Load Immediate li Rd, <imm16> Rd := <imm16> [-](0-65535)
Address la Rd, <label> Rd := &label

Load Dword ld Rd, offset(Rm) Rd := *((long*)Rm + offset)

Load Word lw Rd, offset(Rm) Rd := *((int*)Rm + offset)
Load Halfword lh Rd, offset(Rm) Rd := *((short*)Rm + offset)
Load Byte lb Rd, offset(Rm) Rd := *((char*)Rm + offset)

Store Dword sd Rd, offset(Rm) *((long*)Rm + offset) := Rd

Store Word sw Rd, offset(Rm) *((int*)Rm + offset) := Rd
Store Halfword sh Rd, offset(Rm) *((short*)Rm + offset) := Rd
Store Byte sb Rd, offset(Rm) *((char*)Rm + offset) := Rd
Arithmetic Instructions
Operation Instruction Action
Add add Rd, Rn, Rm Rd := Rn + Rm
addi Rd, Rn, <imm12> Rd := Rn + <imm12> (0-4096)
Subtract sub Rd, Rn, Rm Rd := Rn - Rm
addi Rd, Rn, -<imm12> Rd := Rn - <imm12> (0-4096)
Negate sub Rd, zero, Rn Rd := -Rn
Multiply mul Rd, Rn, Rm Rd := Rn * Rm
Divide div Rd, Rn, Rm Rd := Rn / Rm
Remainder rem Rd, Rn, Rm Rd := Rn % Rm
Logical Instructions
Operation Instruction Action
And and Rd, Rm, Rn Rd := Rm & Rn
andi Rd, Rm, <imm12/13> Rd := Rm & <imm12/13> (13 if 64-bit only)
Or or Rd, Rm, Rn Rd := Rm | Rn
ori Rd, Rm, <imm12/13> Rd := Rm | <imm12/13> (13 if 64-bit only)
Exclusive-Or xor Rd, Rm, Rn Rd := Rm ^ Rn
xori Rd, Rm, <imm12/13> Rd := Rm ^ <imm12/13> (13 if 64-bit only)
Not xori Rd, Rn, -1 Rd := ~Rn

Shift Left sll Rd, Rm, Rn Rd := Rm << Rn

slli Rd, Rm, <shift> Rd := Rm << <shift> (shift: 0-31 [w] or 0-63 [x])

Shift Right srl Rd, Rm, Rn Rd := (unsigned)Rm >> Rn

srli Rd, Rm, <shift> Rd := (unsigned)Rm >> <shift>
sra Rd, Rm, Rn Rd := (signed)Rm >> Rn
srai Rd, Rm, <shift> Rd := (signed)Rm >> <shift>
Branch Instructions
Operation Instruction Action
Unconditional jump j <label> goto <label>
Function call call <label> goto <label>; ra := <pc+4>
Jump to register jr Rd goto Rd
Jump and link jal <label> or jalr Rd ra := <pc+4>, goto <label>
Return ret (alias for jalr ra) goto ra
Conditions eq (equal) A == B
b<cond> Rd, Rm, <label> ne (not equal) A != B
lt (less than) A < B
le (less than/equal) A <= B
gt (greater than) A > B
ge (greater than/equal) A >= B
ltu (less than unsigned) A < B (unsigned)
gtu (greater than unsigned) A > B (unsigned)