2019 - 2020 VLSI IEEE FINAL YEAR Projects @ JP iNFOTeCH

S.NO
Project IEEE 2019-20 VLSI Project Titles
Code

LOW POWER

1 JPV1901 A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

2 JPV1902 A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

3 JPV1903 A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-
In Coarse Gain Calibration

4 JPV1904 A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs

5 JPV1905 A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130
nm CMOS

6 JPV1906 Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced
Bandwidth and Slew Rate

7 JPV1907 Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power
Reduction

8 JPV1908 Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

9 JPV1909 Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation

10 JPV1910 Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static
Linearity Test of ADCs

11 JPV1911 Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for
Array Augmentation in 32-nm CMOS

12 JPV1912 Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise
Cellular Applications

13 JPV1913 Multiloop Control for Fast Transient DC–DC Converter

14 JPV1914 Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

HIGH SPEED AND SIGNAL PROCESSING

15 JPV1915 A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

Contact: Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D., Mobile: (0)9952649690

Web: www.jpinfotech.org | Blog: www.jpinfotech.blogspot.com | Email: jpinfotechprojects@gmail.com
16 JPV1916 A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient

17 JPV1917 A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

18 JPV1918 An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and
Data Recovery Loops

19 JPV1919 An Analog LO Harmonic Suppression Technique for SDR Receivers

20 JPV1920 An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175
μW/Channel in 65-nm CMOS

21 JPV1921 Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing

22 JPV1922 CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

23 JPV1923 Design of Reconfigurable Digital IF Filter with Low Complexity

24 JPV1924 Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

25 JPV1925 Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive
Digit Chopping

26 JPV1926 Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA

27 JPV1927 Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

AREA EFFICIENT/ TIMING & DELAY REDUCTION

28 JPV1928 A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth
Multipliers in Datapaths

29 JPV1929 A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

30 JPV1930 A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

31 JPV1931 An Energy-efficient Accelerator based on Hybrid CPU-FPGA Devices for Password Recovery

32 JPV1932 Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

33 JPV1933 Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

34 JPV1934 Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

35 JPV1935 Efficient Design for Fixed-Width Adder-Tree

Contact: Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D., Mobile: (0)9952649690

Web: www.jpinfotech.org | Blog: www.jpinfotech.blogspot.com | Email: jpinfotechprojects@gmail.com
36 JPV1936 Hardware-Efficient Post-processing Architectures for True Random Number Generators

37 JPV1937 Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for
Large-Scale Array Applications

38 JPV1938 New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

39 JPV1939 Rapid Balise Telegram Decoder with Modified LFSR Architecture for Train Protection Systems

PROJECT SUPPORT TO REGISTERED STUDENTS:

1) IEEE Base paper.

2) Abstract Document.

3) Future Enhancement (based on Requirement).

4) Modified Title / Modified Abstract (based on Requirement).

5) Complete Source Code/Simulation File/ Hardware Kit.

6) How to Run execution help file.

7) Software Packages

8) International Conference / International Journal Publication based on your

project.

OUR OTHER SALIENT FEATURES:

 Number 1 Project Master in Pondicherry/Puducherry.
 Guided more than 60,000 students.
 Successfully conducted more than 25 International Conferences in all over
South India from 2013 to 2019.
 For the academic year 2019- 2020, we have Signed MoU with Many
Engineering Colleges in all over India to Conduct International
Conferences in academic year 2019 – 2020, Where the Registered Students
of JP INFOTECH, can easily publish their Project Papers.

Contact: Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D., Mobile: (0)9952649690

Web: www.jpinfotech.org | Blog: www.jpinfotech.blogspot.com | Email: jpinfotechprojects@gmail.com
  Published more than 6000 Research Articles of Our
Ph.D./M.Phil/ME/M.Tech./BE/B.Tech. Students in Leading
International Conferences and International Journals from 2013 to 2019.
 From the year 2013 to 2019, we are Recognized and Awarded from the
following colleges: “Paavai College of Engg”, “Arjun College of
Technology”, “K.S.R. College of Engineering”, “Vetri Vinayaha College Of
Engineering And Technology”, “SKR Engineering College”, “Sree Sastha
Institute of Engineering and Technology”, “Jaya Engineering College”,
“V.P.Muthaiah Pillai Meenakshi Ammal Engineering College for Women”,
“Muthayammal Arts and Science College”, “Sri Raaja Raajan College of
Engineering and Technology”, “Latha Mathavan Engineering College”,
“Dr Pauls Engineering College”, “Jain College of Engineering”, “Manakula
Vinayagar Institute of Technology”, “CK College of Engineering &
Technology” etc.
 Recognized and published article about JP INFOTECH and its director in
“THE HINDU”, “DINAKARAN” and many more newspapers and Media.
 Leaders with more than 9+ years of experience
 We assist and guarantee you to publish a paper on your project in
INTERNATIONAL JOURNAL PUBLICATIONS / INTERNATIONAL
CONFERENCE PUBLICATIONS.
 NO FALSE PROMISES
 100% Assurance for Project Execution
 Valid Project Completion Certificate
 100% PLACEMENT SUPPORT
 Own Projects are also welcomed.

So don’t wait any more!!! Join us and be a part of us. Walk-in to our Office OR E-
mail us your requirements and Register your projects.

Contact: Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D., Mobile: (0)9952649690

Web: www.jpinfotech.org | Blog: www.jpinfotech.blogspot.com | Email: jpinfotechprojects@gmail.com
For any queries Contact:
Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D.,
Managing Director, JP INFOTECH.

MOBILE: (0)9952649690
EMAIL: jpinfotechprojects@gmail.com
WEBSITE: www.jpinfotech.org

Watch Video Demos on our Youtube Channel:

https://www.youtube.com/jpinfotechprojects

Contact: Dr.R.JAYAPRAKASH BE,MBA,M.Tech.,Ph.D., Mobile: (0)9952649690

Web: www.jpinfotech.org | Blog: www.jpinfotech.blogspot.com | Email: jpinfotechprojects@gmail.com