Professional Documents
Culture Documents
25C080
25C080
25C080
25AA080/25LC080/25C080
8K SPI™ Bus Serial EEPROM
Device Selection Table Description:
Part VCC Max. Clock Temp. The Microchip Technology Inc. 25AA080/25LC080/
Number Range Frequency Ranges 25C080 (25XX080*) are 8 Kbit Serial Electrically
Erasable PROMs. The memory is accessed via a
25AA080 1.8-5.5V 1 MHz I simple Serial Peripheral Interface™ (SPI™) compati-
25LC080 2.5-5.5V 2 MHz I ble serial bus. The bus signals required are a clock
25C080 4.5-5.5V 3 MHz I,E input (SCK) plus separate data in (SI) and data out
(SO) lines. Access to the device is controlled through a
Chip Select (CS) input.
Features:
Communication to the device can be paused via the
• Low-power CMOS technology: hold pin (HOLD). While the device is paused, transi-
- Write current: 3 mA maximum tions on its inputs will be ignored, with the exception of
- Read current: 500 µA typical chip select, allowing the host to service higher priority
interrupts.
- Standby current: 500 nA typical
• 1024 x 8-bit organization
Package Types
• 16 byte page
• Write cycle time: 5 ms max. PDIP/SOIC
• Self-timed erase and write cycles
CS 1 8 VCC
• Block write protection:
25AA080/
- Protect none, 1/4, 1/2 or all of array SO 2 7 HOLD
• Built-in write protection: WP 3 6 SCK
- Power-on/off data protection circuitry VSS 4 5 SI
- Write enable latch
- Write-protect pin
• Sequential read Block Diagram
• High reliability:
Status
- Endurance: 1 M cycles HV Generator
Register
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP and SOIC (150 mil)
• Temperature ranges supported:
Memory EEPROM
- Industrial (I): -40°C to +85°C I/O Control X
Control Array
- Automotive (E) (25C080): -40°C to +125°C Logic
Logic Dec
Page Latches
SI
SO Y Decoder
CS
SCK
HOLD Sense Amp.
R/W Control
WP
VCC
*25XX080 is used in this document as a generic part number for the VSS
25AA080/25LC080/25C080 devices.
SPI™ is a trademark of Motorola Inc.
† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability.
1.1 DC Characteristics
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
DC CHARACTERISTICS
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 only)
Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
D001 VIH1 High-level input 2.0 VCC+1 V VCC ≥ 2.7V (Note)
D002 VIH2 voltage 0.7 VCC VCC+1 V VCC< 2.7V (Note)
D003 VIL1 Low-level input -0.3 0.8 V VCC ≥ 2.7V (Note)
D004 VIL2 voltage -0.3 0.3 VCC V VCC < 2.7V (Note)
D005 VOL Low-level output — 0.4 V IOL = 2.1 mA
D006 VOL voltage — 0.2 V IOL = 1.0 mA, VCC < 2.5V
D007 VOH High-level output VCC -0.5 — V IOH = -400 µA
voltage
D008 ILI Input leakage current -10 10 µA CS = VCC, VIN = VSS TO VCC
D009 ILO Output leakage -10 10 µA CS = VCC, VOUT = VSS TO VCC
current
D010 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0 MHz,
(all inputs and VCC = 5.0V (Note)
outputs)
D011 ICC Read — 1 mA VCC = 5.5V; FCLK = 3.0 MHz;
— 500 µA SO = Open
Operating Current VCC = 2.5V; FCLK = 2.0 MHz;
SO = Open
D012 ICC Write — 5 mA VCC = 5.5V
— 3 mA VCC = 2.5V
D013 ICCS — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or
Standby Current — 1 µA VSS
CS = VCC = 2.5V, Inputs tied to VCC or
VSS
Note: This parameter is periodically sampled and not 100% tested.
Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
1 FCLK Clock Frequency — 3 MHz VCC = 4.5V to 5.5V
— 2 MHz VCC = 2.5V to 4.5V
— 1 MHz VCC = 1.8V to 2.5V
2 TCSS CS Setup Time 100 — ns VCC = 4.5V to 5.5V
250 — ns VCC = 2.5V to 4.5V
500 — ns VCC = 1.8V to 2.5V
3 TCSH CS Hold Time 150 — ns VCC = 4.5V to 5.5V
250 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
4 TCSD CS Disable Time 500 — ns —
5 Tsu Data Setup Time 30 — ns VCC = 4.5V to 5.5V
50 — ns VCC = 2.5V to 4.5V
50 — ns VCC = 1.8V to 2.5V
6 THD Data Hold Time 50 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
100 — ns VCC = 1.8V to 2.5V
7 TR CLK Rise Time — 2 µs (Note 1)
8 TF CLK Fall Time — 2 µs (Note 1)
9 THI Clock High Time 150 — ns VCC = 4.5V to 5.5V
230 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
10 TLO Clock Low Time 150 — ns VCC = 4.5V to 5.5V
230 — ns VCC = 2.5V to 4.5V
475 — ns VCC = 1.8V to 2.5V
11 TCLD Clock Delay Time 50 — ns —
12 TCLE Clock Enable Time 50 — ns —
13 TV Output Valid from Clock Low — 150 ns VCC = 4.5V to 5.5V
— 230 ns VCC = 2.5V to 4.5V
— 475 ns VCC = 1.8V to 2.5V
14 THO Output Hold Time 0 — ns (Note 1)
15 TDIS Output Disable Time — 200 ns VCC = 4.5V to 5.5V (Note 1)
— 250 ns VCC = 2.5V to 4.5V (Note 1)
— 500 ns VCC = 1.8V to 2.5V (Note 1)
16 THS HOLD Setup Time 100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
200 — ns VCC = 1.8V to 2.5V
17 THH HOLD Hold Time 100 — ns VCC = 4.5V to 5.5V
100 — ns VCC = 2.5V to 4.5V
200 — ns VCC = 1.8V to 2.5V
18 THZ HOLD Low to Output High-Z 100 — ns VCC = 4.5V to 5.5V (Note 1)
150 — ns VCC = 2.5V to 4.5V (Note 1)
200 — ns VCC = 1.8V to 2.5V (Note 1)
19 THV HOLD High to Output Valid 100 — ns VCC = 4.5V to 5.5V
150 — ns VCC = 2.5V to 4.5V
200 — ns VCC = 1.8V to 2.5V
20 TWC Internal Write Cycle Time — 5 ms —
21 — Endurance 1M — E/W (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.
SCK
18 19
High-impedance
SO n+2 n+1 n n n-1
don’t care 5
SI n+2 n+1 n n n-1
HOLD
CS 12
2 11
7
Mode 1,1 8 3
SI MSB in LSB in
High-impedance
SO
CS
9 10 3
Mode 1,1
SCK Mode 0,0
13
14 15
don’t care
SI
AC Waveform: VCC
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
2.25 KΩ
VHI = 4.0V (Note 2)
Timing Measurement Reference Level SO
Input 0.5 VCC
1.8 KΩ 100 pF
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
data out
High-impedance
SO 7 6 5 4 3 2 1 0
CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
High-impedance
SO
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
instruction 16-bit address data byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
data byte 2 data byte 3 data byte n (16 max)
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CS
0 1 2 3 4 5 6 7
SCK
SI 0 0 0 0 0 1 1 0
High-impedance
SO
CS
0 1 2 3 4 5 6 7
SCK
SI 0 0 0 0 0 1 10 0
High-impedance
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
instruction
SI 0 0 0 0 0 1 0 1
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
High-impedance
SO
XXXXXXXX 25LC080
XXXXXNNN /PNNN
YYWW YYWW
XXXXXXXX 25LC080
XXXXYYWW /SNYYWW
NNN NNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
E1
n 1
A A2
L
c
A1
β B1
p
eB B
E1
D
2
B n 1
h α
45×
c
A A2
f
β L A1
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.