Commands used in Soc Workshop from 19th feb till 22 feb

1 top
2 sudo apt-get install git
3 sudo su
4 sudo apt-get install git
5 sudo apt-get -f install //if any problem in git installation comes
6 sudo apt-get -f dist-upgrade//if any problem in git installation comes
7 apt-get update//if any problem in git installation comes
8 sudo apt-get update//if any problem in git installation comes
9 sudo apt-get install git
10 apt-mark showhold
11 sudo dpkg --configure -a
12 sudo apt-get install -f
13 sudo apt-get clean && sudo apt-get update
14 sudo apt-get dist-upgrade
15 sudo apt-get purge zlib1g-dev
16 sudo apt-get autoremove
17 sudo aptitude install libssl-dev zliblg-dev=1:1.2.8.dfsg-1ubuntu1
18 sudo apt-get update

Steps to install eda tool

19 sudo apt-get install git to inatsll eda tool Step1
20 git clone https://github.com/kunalg123/vsdflow.git Step2
21 sudo git clone https://github.com/kunalg123/vsdflow.git Step3
22 cd vsdflow/ Step4
23 chmod 777 opensource_eda_tool_install.sh Step 5
24 sudo ./opensource_eda_tool_install.sh Step6
25 ./vsdflow spi_slave_design_details.csv Step7
26 cd verilog/
27 pwd
28 mkdir source synthesis layout
29 ls -ltr
30 cp picorv32.v source/.
31 ls -ltr source/
32 gflow gui &
33 cd vsdflow/verilog/
34 ls -ltr
35 ls -ltr source/
36 qflow gui &
37 sudo apt-get install python3-tk
38 sudo apt install ngspice
39 qflow gui &
40 ls -ltr /usr/local/share/qflow/tech
41 ls -ltr /usr/local/share/qflow/tech/osu018
42 qflow gui &
43 less source /picorv32.v
44 less source/picorv32.v
45 ls -ltr source/
46 less source/picorv32.ys
47 less synthesis/picorv32.rtl.v
48 less log/synth.log
49 cd vsdflow/
50 cd outdir_spi_slave/
51 qflow gui &
52 cd../verilog
53 ls -ltr
54 cp picorv32.v source/.
55 cd..
56 cd ..
57 cd vsdflow/
58 cd verilog/
59 pwd
60 ls -ltr
61 cp picorv32.v source/.
62 gflow gui &
63 qflow gui &
64 cd vsdflow/
65 cd verilog/
66 cd picorv32
67 ls -ltr
68 vd picorv32.v source/
69 cd picoRV32.V
70 cd picorv32.v source/
71 qflow gui &
72 cd
73 pwd
74 git clone https://github.com/kunalg123/flipflop_design.git //Day 3
75 ls -ltr
76 cd flipflop_design/
77 ls -ltr
78 magic -T min2.tech &
79 less min2.tech
80 magic &
81 magic -T min2.tech &
82 magic -T min2.tech
83 magic -T min2.tech inv2.mag &
84 less my_inv.mag
85 ls -ltr
86 less my_inv.lef
87 less my_inv.spice
88 git clone https://github.com/kunalg123/flipflop_design.git
89 cd ..
 90 cd
91 pwd
92 cd flipflop_design/
93 ls -ltr
94 magic -T min2.tech inv2.mag &
95 la -ltr
96 ls -ltr
97 less inv2.spice
98 gedit
99 less inv2.spice
100 gedit
101 sudo apt-get install ngspice
102 ndspice
103 ngspice
104 ngspice inv2.spice
105 ls -ltr
106 gedit
107 ngspice inv2.spice
108 cd vsdflow/
109 cd verilog/
110 qflow gui &
111 qflow display picorv32.v //Day3
112 sta
113 ls -ltr synthesis/
114 pwd
115 ls /home/dbit/vsdflow/verilog/synthesis/picorv32.rtl.v
116 ls /user/local/share/qflow/tech/osu018/osu018_stdcells.lib
117 ls /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
118 gedit sta.conf
119 gedit picorv32.sdc
120 sta sta.conf
121 gedit picorv32.sdc
122 gedit sta.conf &
123 sta sta.conf
124 gedit sta.conf &
125 sta sta.conf

In gedit sta.conf &

Following lines need to copy peast

read_liberty -max /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib

read_verilog /home/dbit/vsdflow/verilog/synthesis/picorv32.rtl.v
link_design picorv32
read_sdc /home/dbit/vsdflow/verilog/picorv32.sdc
report_checks

In gedit picorv32.sdc
Following lines need to copy peast
create_clock -name clk -period 2 -waveform {0 1} [get_ports clk]

To run
sta sta.conf

This window will apear

o/p of sta sta conf

Delay Time Description

---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ DFFPOSX1_724/CLK (DFFPOSX1)
0.34 0.34 v DFFPOSX1_724/Q (DFFPOSX1)
0.27 0.62 ^ NAND2X1_612/Y (NAND2X1)
0.19 0.80 ^ BUFX4_1155/Y (BUFX4)
0.23 1.03 v OAI21X1_2193/Y (OAI21X1)
0.12 1.14 ^ INVX4_37/Y (INVX4)
0.09 1.23 v NOR2X1_914/Y (NOR2X1)
0.27 1.50 ^ NAND3X1_59/Y (NAND3X1)
0.19 1.70 ^ OR2X2_28/Y (OR2X2)
0.17 1.87 v NOR3X1_2/Y (NOR3X1)
 0.20 2.07 ^ NAND3X1_63/Y (NAND3X1)
0.17 2.24 v NOR3X1_3/Y (NOR3X1)
0.21 2.44 ^ NAND3X1_66/Y (NAND3X1)
0.16 2.61 v NOR3X1_4/Y (NOR3X1)
0.10 2.71 ^ NAND3X1_70/Y (NAND3X1)
0.08 2.79 v AOI21X1_796/Y (AOI21X1)
0.09 2.88 ^ OAI21X1_2395/Y (OAI21X1)
0.06 2.94 v AOI21X1_797/Y (AOI21X1)
0.00 2.94 v DFFPOSX1_614/D (DFFPOSX1)
2.94 data arrival time

10.00 10.00 clock clk (rise edge)

0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ DFFPOSX1_614/CLK (DFFPOSX1)
-0.16 9.84 library setup time
9.84 data required time
---------------------------------------------------------
9.84 data required time
-2.94 data arrival time
---------------------------------------------------------
6.90 slack (MET)

% set_clock_uncertainty 0.2 [get_clocks clk]

% report_checks
Startpoint: DFFPOSX1_724 (rising edge-triggered flip-flop clocked by clk)
Endpoint: DFFPOSX1_614 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Delay Time Description

---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ DFFPOSX1_724/CLK (DFFPOSX1)
0.34 0.34 v DFFPOSX1_724/Q (DFFPOSX1)
0.27 0.62 ^ NAND2X1_612/Y (NAND2X1)
0.19 0.80 ^ BUFX4_1155/Y (BUFX4)
0.23 1.03 v OAI21X1_2193/Y (OAI21X1)
0.12 1.14 ^ INVX4_37/Y (INVX4)
0.09 1.23 v NOR2X1_914/Y (NOR2X1)
0.27 1.50 ^ NAND3X1_59/Y (NAND3X1)
0.19 1.70 ^ OR2X2_28/Y (OR2X2)
0.17 1.87 v NOR3X1_2/Y (NOR3X1)
0.20 2.07 ^ NAND3X1_63/Y (NAND3X1)
 0.17 2.24 v NOR3X1_3/Y (NOR3X1)
0.21 2.44 ^ NAND3X1_66/Y (NAND3X1)
0.16 2.61 v NOR3X1_4/Y (NOR3X1)
0.10 2.71 ^ NAND3X1_70/Y (NAND3X1)
0.08 2.79 v AOI21X1_796/Y (AOI21X1)
0.09 2.88 ^ OAI21X1_2395/Y (OAI21X1)
0.06 2.94 v AOI21X1_797/Y (AOI21X1)
0.00 2.94 v DFFPOSX1_614/D (DFFPOSX1)
2.94 data arrival time

10.00 10.00 clock clk (rise edge)

0.00 10.00 clock network delay (ideal)
-0.20 9.80 clock uncertainty
0.00 9.80 clock reconvergence pessimism
9.80 ^ DFFPOSX1_614/CLK (DFFPOSX1)
-0.16 9.64 library setup time
9.64 data required time
---------------------------------------------------------
9.64 data required time
-2.94 data arrival time
---------------------------------------------------------
6.70 slack (MET)

% set_propagated_clock [all_clocks]
% report checks
ambiguous command name "report": report_annotated_check report_annotated_delay
report_arrival report_cell report_check_types report_checks report_clock_properties
report_clock_skew report_constant report_dcalc report_disabled_edges report_edges
report_instance report_lib_cell report_net report_object_full_names report_object_names
report_path report_pin report_power report_pulse_width_checks report_required
report_slack report_slews report_tns report_wns report_worst_slack
% report_checks
Startpoint: DFFPOSX1_724 (rising edge-triggered flip-flop clocked by clk)
Endpoint: DFFPOSX1_614 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Delay Time Description

---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.56 0.56 clock network delay (propagated)
0.00 0.56 ^ DFFPOSX1_724/CLK (DFFPOSX1)
0.36 0.92 v DFFPOSX1_724/Q (DFFPOSX1)
0.27 1.19 ^ NAND2X1_612/Y (NAND2X1)
0.19 1.38 ^ BUFX4_1155/Y (BUFX4)
 0.23 1.60 v OAI21X1_2193/Y (OAI21X1)
0.12 1.72 ^ INVX4_37/Y (INVX4)
0.09 1.81 v NOR2X1_914/Y (NOR2X1)
0.27 2.08 ^ NAND3X1_59/Y (NAND3X1)
0.19 2.27 ^ OR2X2_28/Y (OR2X2)
0.17 2.45 v NOR3X1_2/Y (NOR3X1)
0.20 2.64 ^ NAND3X1_63/Y (NAND3X1)
0.17 2.81 v NOR3X1_3/Y (NOR3X1)
0.21 3.02 ^ NAND3X1_66/Y (NAND3X1)
0.16 3.18 v NOR3X1_4/Y (NOR3X1)
0.10 3.29 ^ NAND3X1_70/Y (NAND3X1)
0.08 3.37 v AOI21X1_796/Y (AOI21X1)
0.09 3.46 ^ OAI21X1_2395/Y (OAI21X1)
0.06 3.51 v AOI21X1_797/Y (AOI21X1)
0.00 3.51 v DFFPOSX1_614/D (DFFPOSX1)
3.51 data arrival time

10.00 10.00 clock clk (rise edge)

0.56 10.56 clock network delay (propagated)
-0.20 10.36 clock uncertainty
0.00 10.36 clock reconvergence pessimism
10.36 ^ DFFPOSX1_614/CLK (DFFPOSX1)
-0.26 10.10 library setup time
10.10 data required time
---------------------------------------------------------
10.10 data required time
-3.51 data arrival time
---------------------------------------------------------
6.59 slack (MET)

% report_checks -format full_clock_expanded

Startpoint: DFFPOSX1_724 (rising edge-triggered flip-flop clocked by clk)
Endpoint: DFFPOSX1_614 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Delay Time Description

---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.27 0.27 ^ BUFX4_49/Y (BUFX4)
0.29 0.56 ^ CLKBUF1_102/Y (CLKBUF1)
0.00 0.56 ^ DFFPOSX1_724/CLK (DFFPOSX1)
0.36 0.92 v DFFPOSX1_724/Q (DFFPOSX1)
 0.27 1.19 ^ NAND2X1_612/Y (NAND2X1)
0.19 1.38 ^ BUFX4_1155/Y (BUFX4)
0.23 1.60 v OAI21X1_2193/Y (OAI21X1)
0.12 1.72 ^ INVX4_37/Y (INVX4)
0.09 1.81 v NOR2X1_914/Y (NOR2X1)
0.27 2.08 ^ NAND3X1_59/Y (NAND3X1)
0.19 2.27 ^ OR2X2_28/Y (OR2X2)
0.17 2.45 v NOR3X1_2/Y (NOR3X1)
0.20 2.64 ^ NAND3X1_63/Y (NAND3X1)
0.17 2.81 v NOR3X1_3/Y (NOR3X1)
0.21 3.02 ^ NAND3X1_66/Y (NAND3X1)
0.16 3.18 v NOR3X1_4/Y (NOR3X1)
0.10 3.29 ^ NAND3X1_70/Y (NAND3X1)
0.08 3.37 v AOI21X1_796/Y (AOI21X1)
0.09 3.46 ^ OAI21X1_2395/Y (OAI21X1)
0.06 3.51 v AOI21X1_797/Y (AOI21X1)
0.00 3.51 v DFFPOSX1_614/D (DFFPOSX1)
3.51 data arrival time

10.00 10.00 clock clk (rise edge)

0.00 10.00 clock source latency
0.00 10.00 ^ clk (in)
0.27 10.27 ^ BUFX4_48/Y (BUFX4)
0.29 10.56 ^ CLKBUF1_11/Y (CLKBUF1)
0.00 10.56 ^ DFFPOSX1_614/CLK (DFFPOSX1)
-0.20 10.36 clock uncertainty
0.00 10.36 clock reconvergence pessimism
-0.26 10.10 library setup time
10.10 data required time
---------------------------------------------------------
10.10 data required time
-3.51 data arrival time
---------------------------------------------------------
6.59 slack (MET)

% report_checks -fields {capacitance slew input_pin net}

Startpoint: DFFPOSX1_724 (rising edge-triggered flip-flop clocked by clk)
Endpoint: DFFPOSX1_614 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description

----------------------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.56 0.56 clock network delay (propagated)
 0.22 0.00 0.56 ^ DFFPOSX1_724/CLK (DFFPOSX1)
0.23 0.36 0.92 v DFFPOSX1_724/Q (DFFPOSX1)
9 0.20 latched_branch (net)
0.23 0.00 0.92 v NAND2X1_612/A (NAND2X1)
0.27 0.27 1.19 ^ NAND2X1_612/Y (NAND2X1)
7 0.10 _10112_ (net)
0.27 0.00 1.19 ^ BUFX4_1155/A (BUFX4)
0.10 0.19 1.38 ^ BUFX4_1155/Y (BUFX4)
7 0.13 _10112__bF_buf0 (net)
0.10 0.00 1.38 ^ OAI21X1_2193/B (OAI21X1)
0.26 0.23 1.60 v OAI21X1_2193/Y (OAI21X1)
6 0.14 _10201_ (net)
0.26 0.00 1.60 v INVX4_37/A (INVX4)
0.10 0.12 1.72 ^ INVX4_37/Y (INVX4)
5 0.08 _10205_ (net)
0.10 0.00 1.72 ^ NOR2X1_914/B (NOR2X1)
0.10 0.09 1.81 v NOR2X1_914/Y (NOR2X1)
2 0.03 _10206_ (net)
0.10 0.00 1.81 v NAND3X1_59/B (NAND3X1)
0.32 0.27 2.08 ^ NAND3X1_59/Y (NAND3X1)
8 0.12 _10242_ (net)
0.32 0.00 2.08 ^ OR2X2_28/A (OR2X2)
0.11 0.19 2.27 ^ OR2X2_28/Y (OR2X2)
4 0.07 _10333_ (net)
0.11 0.00 2.27 ^ NOR3X1_2/C (NOR3X1)
0.19 0.17 2.45 v NOR3X1_2/Y (NOR3X1)
5 0.07 _10451_ (net)
0.19 0.00 2.45 v NAND3X1_63/C (NAND3X1)
0.20 0.20 2.64 ^ NAND3X1_63/Y (NAND3X1)
4 0.06 _10490_ (net)
0.20 0.00 2.64 ^ NOR3X1_3/C (NOR3X1)
0.16 0.17 2.81 v NOR3X1_3/Y (NOR3X1)
3 0.06 _10678_ (net)
0.16 0.00 2.81 v NAND3X1_66/C (NAND3X1)
0.22 0.21 3.02 ^ NAND3X1_66/Y (NAND3X1)
4 0.07 _10691_ (net)
0.22 0.00 3.02 ^ NOR3X1_4/C (NOR3X1)
0.15 0.16 3.18 v NOR3X1_4/Y (NOR3X1)
3 0.05 _1142_ (net)
0.15 0.00 3.18 v NAND3X1_70/C (NAND3X1)
0.11 0.10 3.29 ^ NAND3X1_70/Y (NAND3X1)
1 0.02 _1189_ (net)
0.11 0.00 3.29 ^ AOI21X1_796/B (AOI21X1)
0.08 0.08 3.37 v AOI21X1_796/Y (AOI21X1)
1 0.02 _1194_ (net)
0.08 0.00 3.37 v OAI21X1_2395/B (OAI21X1)
 0.08 0.09 3.46 ^ OAI21X1_2395/Y (OAI21X1)
1 0.02 _1196_ (net)
0.08 0.00 3.46 ^ AOI21X1_797/B (AOI21X1)
0.06 0.06 3.51 v AOI21X1_797/Y (AOI21X1)
1 0.01 _80__31_ (net)
0.06 0.00 3.51 v DFFPOSX1_614/D (DFFPOSX1)
3.51 data arrival time

10.00 10.00 clock clk (rise edge)

0.56 10.56 clock network delay (propagated)
-0.20 10.36 clock uncertainty
0.00 10.36 clock reconvergence pessimism
10.36 ^ DFFPOSX1_614/CLK (DFFPOSX1)
-0.26 10.10 library setup time
10.10 data required time
----------------------------------------------------------------------------
10.10 data required time
-3.51 data arrival time
----------------------------------------------------------------------------
6.59 slack (MET)

Day 5
130 cd vsdflow/
131 cd verilog/
132 ls -ltr
133 qflow sta picorv32
134 ls -ltr log/
135 less log/sta.log
136 qflow route picorv32
137 less log/
138 qflow backanno picorv32
139 less log/
140 less log/post_sta.log
141 less synthesis/picorv32.spef
142 qflow backanno picorv32
143 less synthesis/picorv32.spef
144 less synthesis/picorv32.spwf //spelling mistake
145 less synthesis/picorv32.spef
146 less sta.conf
147 gedit sta.conf
148 sta sta.conf
149 gedit sta.conf
150 sta sta.conf
151 gedit sta.conf
152 sta sta.conf
153 gedit sta.conf
154 sta sta.conf
155 gedit sta.conf
156 sta sta.conf
157 gedit sta.conf
 158 sta.log/
159 qflow display picorv32

go to
scs.sifive.com

contactvsd@vlsisystemdesign.com
password vsd12345

go to
Customer Core Designs
E31 Standard Core Trial v2p0

Download

terminal
cd
dbit@elab1-33:~/vsdflow/verilog$ cd ..
dbit@elab1-33:~/vsdflow$ cd verilog
dbit@elab1-33:~/vsdflow/verilog$ pwd
/home/dbit/vsdflow/verilog
dbit@elab1-33:~/vsdflow/verilog$ cd
dbit@elab1-33:~$ mkdir my_project^C
dbit@elab1-33:~$ mkdir my_project
dbit@elab1-33:~$ cd my_project/
dbit@elab1-33:~/my_project$ ls -ltr ~/dpwnloads/
ls: cannot access '/home/dbit/dpwnloads/': No such file or directory
dbit@elab1-33:~/my_project$ la -ltr ~/downloads/
ls: cannot access '/home/dbit/downloads/': No such file or directory
dbit@elab1-33:~/my_project$ la -ltr ~/Downloads/
total 9092
-rw-rw-r-- 1 dbit dbit 8388608 Feb 23 14:30 0123735807.pdf
-rw-rw-r-- 1 dbit dbit 919998 Feb 23 14:44 sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz
dbit@elab1-33:~/my_project$ mv
~/Downloads/sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz
mv: missing destination file operand after
'/home/dbit/Downloads/sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz'
Try 'mv --help' for more information.
dbit@elab1-33:~/my_project$ mv
~/Downloads/sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz .
dbit@elab1-33:~/my_project$ ls -ltr
total 900
-rw-rw-r-- 1 dbit dbit 919998 Feb 23 14:44 sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz
dbit@elab1-33:~/my_project$ tar -xzf sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz
dbit@elab1-33:~/my_project$ ls -ltr
total 904
drwxrwxr-x 5 dbit dbit 4096 Feb 3 2018 sifive_coreip_E31_AHB_rtl_eval_v2p0
-rw-rw-r-- 1 dbit dbit 919998 Feb 23 14:44 sifive_coreip_E31_AHB_rtl_eval_v2p0.tar.gz
dbit@elab1-33:~/my_project$ ls -ltr sifive_coreip_E31_AHB_rtl_eval_v2p0
total 20
drwxrwxr-x 5 dbit dbit 4096 Feb 3 2018 tests
-rw-rw-r-- 1 dbit dbit 2750 Feb 3 2018 release.txt
drwxrwxr-x 2 dbit dbit 4096 Feb 3 2018 info
drwxrwxr-x 5 dbit dbit 4096 Feb 3 2018 verilog
-rw-rw-r-- 1 dbit dbit 1579 Feb 3 2018 Makefile
dbit@elab1-33:~/my_project$ cd sifive_coreip_E31_AHB_rtl_eval_v2p0/
dbit@elab1-33:~/my_project/sifive_coreip_E31_AHB_rtl_eval_v2p0$ ^C
dbit@elab1-33:~/my_project/sifive_coreip_E31_AHB_rtl_eval_v2p0$ ls -ltr verilog/design
total 4128
-rw-rw-r-- 1 dbit dbit 30081 Feb 3 2018 E31__EVAL_143.v
-rw-rw-r-- 1 dbit dbit 10733 Feb 3 2018 E31__EVAL_142.v
-rw-rw-r-- 1 dbit dbit 1006 Feb 3 2018 E31__EVAL_141.v

Or
Commands given by Kunal for project
0
mv
cp
mkdir
cp <source directory> <destination directory>
qflow gui &
qflow -T osu018 <Design NAme>

qflow place <Design Name>

qflow sta <Design Name>

qflow backanno <Design Name>