SQ7414EN Product Bundle PDF

SQ7414EN
www.vishay.com
Vishay Siliconix
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
FEATURES
PRODUCT SUMMARY
• TrenchFET® Power MOSFET
VDS (V) 60
• Low Thermal Resistance PowerPAK® 1212-8
RDS(on) () at VGS = 10 V 0.025
Package with 1.07 mm Profile
RDS(on) () at VGS = 4.5 V 0.036
• PWM Optimized
ID (A) 5.6
• AEC-Q101 Qualified
Configuration Single
• 100 % Rg and UIS Tested
D
PowerPAK 1212-8 • Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
3.30 mm S
3.30 mm
1
S
2
S G
3
G
4
D
8
D S
7
D
6
D N-Channel MOSFET
5
Bottom View
Part Marking Code: Q001
ORDERING INFORMATION
Package PowerPAK 1212-8
Lead (Pb)-free and Halogen-free SQ7414EN-T1-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL 10 s STEADY STATE UNIT
Drain-Source Voltage VDS 60 60
V
Gate-Source Voltage VGS ± 20 ± 20
TC = 25 °C 8.7 5.6
Continuous Drain Currenta ID
TC = 70 °C 7 4.4
Continuous Source Current (Diode Conduction)a IS 3.2 1.3 A
Pulsed Drain Currentb IDM 30 30
Single Pulse Avalanche Current IAS 19 19
L = 0.1 mH
Single Pulse Avalanche Energy EAS 18 18 mJ
TC = 25 °C 3.8 1.5
Maximum Power Dissipationb PD W
TA = 25 °C 2 0.8
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 175 - 55 to + 175
°C
Soldering Recommendations (Peak Temperature)d, e 260 260
THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
t  10 s 26 33
Junction-to-Ambient RthJA
PCB Mountc 65 81 °C/W
Junction-to-Case (Drain) RthJC 1.9 2.4
Notes
a. Package limited.
b. Pulse test; pulse width  300 μs, duty cycle  2 %.
c. When mounted on 1" square PCB (FR-4 material).
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S13-1462-Rev. E, 01-Jul-13 1 Document Number: 74489

For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ7414EN
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 60 - -
V
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.5 - 2.5
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VGS = 0 V VDS = 60 V - - 1
Zero Gate Voltage Drain Current IDSS VGS = 0 V VDS = 60 V, TJ = 55 °C - - 5 μA
VGS = 0 V VDS = 60 V, TJ = 175 °C - - 150
On-State Drain Currenta ID(on) VGS = 10 V VDS5 V 30 - - A
VGS = 10 V ID = 8.7 A - 0.021 0.025
VGS = 10 V ID = 8.7 A, TJ = 125 °C - - 0.049
Drain-Source On-State Resistancea RDS(on) 
VGS = 10 V ID = 8.7 A, TJ = 175 °C - - 0.061
VGS = 4.5 V ID = 7.3 A - 0.030 0.036
Forward Transconductancea gfs VDS = 15 V, ID = 8.7 A - 18 - S
Dynamicb
Input Capacitance Ciss - 740 925
Output Capacitance Coss VGS = 0 V VDS = 25 V, f = 1 MHz - 140 175 pF
Reverse Transfer Capacitance Crss - 50 63
Total Gate Chargec Qg - 16 25
Gate-Source Chargec Qgs VGS = 10 V VDS = 30 V, ID = 8.7 A - 2.7 - nC
Gate-Drain Chargec Qgd - 4.4 -
Gate Resistance Rg f = 1 MHz 0.2 1 1.8 
Turn-On Delay Timec td(on) - 15 25
Rise Timec tr VDD = 30 V, RL = 30  - 12 20
ns
Turn-Off Delay Timec td(off) ID  1 A, VGEN = 10 V, Rg = 6  - 30 50
Fall Timec tf - 12 20
Source-Drain Diode Ratings and Characteristicsb
Pulsed Currenta ISM - - 30 A
Forward Voltage VSD IF = 85 A, VGS = 0 V - - 1.2 V
Reverse Recovery Time trr IF = 3.2 A, dI/dt = 100 A/μs - 45 90 ns
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.




Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

SQ7414EN
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
30 30
VGS = 10 V thru 5 V
4V 25
24
I D - Drain Current (A)

I D - Drain Current (A)
20
18
15
12
10
TC = 125 °C
6
5
3V 25 °C
- 55 °C
0 0
0 1 2 3 4 5 0 1 2 3 4 5
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)
Output Characteristics Transfer Characteristics

0.06 1200
0.05 1000
R DS(on) - On-Resistance ()
C - Capacitance (pF)
0.04 800
Ciss
VGS = 4.5 V
0.03 600
VGS = 10 V
0.02 400
Coss
Crss
0.01 200
0.00 0
0 5 10 15 20 25 30 0 10 20 30 40 50 60
ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current Capacitance
10 2.0
VDS = 30 V VGS = 10 V
R DS(on) - On-Resistance (Normalized)
1.8
VGS - Gate-to-Source Voltage (V)
8 ID = 8.7 A ID = 8.7 A
1.6
6
1.4
1.2
4
1.0
2
0.8
0 0.6
0 4 8 12 16 - 50 - 25 0 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)
Gate Charge On-Resistance vs. Junction Temperature

SQ7414EN
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
30 0.08
ID = 8.7 A
R DS(on) - On-Resistance ()

TJ = 150 °C 0.06
I S - Source Current (A)
10
0.04
TJ = 25 °C 0.02
1 0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage
0.4 50
ID = 250 µA
0.2 40
V GS(th) Variance (V)
0.0
Power (W)
30
- 0.2
20
- 0.4
10
- 0.6
- 0.8 0
- 50 - 25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 600
TJ - Temperature (°C) Time (s)
Threshold Voltage Single Pulse Power, Junction-to-Ambient

SQ7414EN
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
1
Normalized Effective Transient
Duty Cycle = 0.5

Thermal Impedance
0.2
Notes:
0.1 PDM
0.1
0.05 t1
t2
t1
1. Duty Cycle, D =
0.02 t2
2. Per Unit Base = R thJA = 65 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4 10-3 10-2 10-1 1 10 100 600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Duty Cycle = 0.5

Thermal Impedance
0.2
0.1
0.1 Single Pulse

0.05
0.02
0.01
10-4 10-3 10-2 10-1 1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case

Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.











Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74489.

Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® 1212-8, (Single / Dual)
L
H E2 K
D4
W E4
θ
M
8
1 1
e
Z
2
D1
D2
D5
2
D
3
4 5 4
b
θ
L1 E3
θ θ A1
Backside view of single pad
L
H K
A
E2
E4
c
D2 D3(2x) D4
2
1
E1 Detail Z D1
E 2
D5
Notes 3
K1
1. Inch will govern
2 Dimensions exclusive of mold gate burrs D2
4
b
3. Dimensions exclusive of mold flash and cutting burrs
E3
Backside view of dual pad
MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.23 0.30 0.41 0.009 0.012 0.016
c 0.23 0.28 0.33 0.009 0.011 0.013
D 3.20 3.30 3.40 0.126 0.130 0.134
D1 2.95 3.05 3.15 0.116 0.120 0.124
D2 1.98 2.11 2.24 0.078 0.083 0.088
D3 0.48 - 0.89 0.019 - 0.035
D4 0.47 typ. 0.0185 typ
D5 2.3 typ. 0.090 typ
E 3.20 3.30 3.40 0.126 0.130 0.134
E1 2.95 3.05 3.15 0.116 0.120 0.124
E2 1.47 1.60 1.73 0.058 0.063 0.068
E3 1.75 1.85 1.98 0.069 0.073 0.078
E4 0.034 typ. 0.013 typ.
e 0.65 BSC 0.026 BSC
K 0.86 typ. 0.034 typ.
K1 0.35 - - 0.014 - -
H 0.30 0.41 0.51 0.012 0.016 0.020
L 0.30 0.43 0.56 0.012 0.017 0.022
L1 0.06 0.13 0.20 0.002 0.005 0.008
 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882
Revison: 09-Jan-17 1 Document Number: 71656

For technical questions, contact: pmostechsupport@vishay.com
Package Information
www.vishay.com
Vishay Siliconix
Flat Pack: 16 Leads
L
E3
16 15 14 13 12 11 10 9
E2
1 2 3 4 5 6 7 8
C
e
B Q
S S1 A
MILLIMETERS INCHES
DIM.
MIN. MAX. MIN. MAX.
A 1.52 2.54 0.060 0.100
B 0.38 0.48 0.015 0.019
C 0.10 0.15 0.004 0.006
D 9.91 10.41 0.390 0.410
E 6.60 7.11 0.260 0.280
E2 4.45 4.95 0.175 0.195
E3 0.76 1.27 0.030 0.050
e 1.27 BSC 0.050 BSC
L 7.62 8.89 0.300 0.350
Q 0.66 1.14 0.026 0.045
S - 1.14 - 0.045
S1 0.013 - 0.005 -
ECN: S15-1674-Rev. D, 27-Jul-15
DWG: 5343
Revison: 27-Jul-15 1 Document Number: 74786
AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available The PowerPAK 1212-8 has a footprint area compara-
with die on resistances around 1 mΩ and with the ble to TSOP-6. It is over 40 % smaller than standard
capability to handle 85 A. While these die capabilities TSSOP-8. Its die capacity is more than twice the size
represent a major advance over what was available of the standard TSOP-6’s. It has thermal performance
just a few years ago, it is important for power MOSFET an order of magnitude better than the SO-8, and 20
packaging technology to keep pace. It should be obvi- times better than TSSOP-8. Its thermal performance is
ous that degradation of a high performance die by the better than all current SMT packages in the market. It
package is undesirable. PowerPAK is a new package will take the advantage of any PC board heat sink
technology that addresses these issues. The PowerPAK capability. Bringing the junction temperature down also
1212-8 provides ultra-low thermal impedance in a increases the die efficiency by around 20 % compared
small package that is ideal for space-constrained with TSSOP-8. For applications where bigger pack-
applications. In this application note, the PowerPAK ages are typically required solely for thermal consider-
1212-8’s construction is described. Following this, ation, the PowerPAK 1212-8 is a good option.
mounting information is presented. Finally, thermal
and electrical performance is discussed. Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
THE PowerPAK PACKAGE The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
The PowerPAK 1212-8 package (Figure 1) is a deriva-
space constraints.
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
PowerPAK 1212 SINGLE MOUNTING
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is To take the advantage of the single PowerPAK 1212-8’s
mounted on. The PowerPAK 1212-8 thus translates thermal performance see Application Note 826,
the benefits of the PowerPAK SO-8 into a smaller Recommended Minimum Pad Patterns With Outline
package, with the same level of thermal performance. Drawing Access for Vishay Siliconix MOSFETs. Click
(Please refer to application note “PowerPAK SO-8 on the PowerPAK 1212-8 single in the index of this
Mounting and Thermal Considerations.”) document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681 www.vishay.com

03-Mar-06 1
AN822
Vishay Siliconix
PowerPAK 1212 DUAL

To take the advantage of the dual PowerPAK 1212-8’s ture profile used, and the temperatures and time
thermal performance, the minimum recommended duration, are shown in Figures 2 and 3. For the lead
land pattern can be found in Application Note 826, (Pb)-free solder profile, see http://www.vishay.com/
Recommended Minimum Pad Patterns With Outline doc?73257.
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an Ramp-Up Rate + 6 °C /Second Maximum
area of about 0.3 to 0.5 in2 of will yield little improve- Temperature at 155 ± 15 °C 120 Seconds Maximum
ment in thermal performance. Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature 20 - 40 Seconds
REFLOW SOLDERING
Ramp-Down Rate + 6 °C/Second Maximum
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
Figure 2. Solder Reflow Temperature Profile
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
10 s (max)
210 - 220 °C
3 ° C/s (max) 4 ° C/s (max)
183 °C
140 - 170 °C
50 s (max)
3° C/s (max) 60 s (min) Reflow Zone

Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
www.vishay.com Document Number 71681

2 03-Mar-06
AN822
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TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8
Configuration Single Dual Single Dual Single Dual Single Dual Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5
PowerPAK 1212 Standard SO-8 Standard TSSOP-8 TSOP-6

49.8 °C 85 °C 149 °C 125 °C
2.4 °C/W 20 °C/W 52 °C/W 40 °C/W
PC Board at 45 °C
Figure 4. Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction Spreading Copper
A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to
the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It
junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal
is measured for the device mounted to an infinite heat performance for a given area of spreading copper.
sink and is therefore a characterization of the device Figure 5 and Figure 6 show the thermal resistance of a
only, in other words, independent of the properties of the PowerPAK 1212-8 single and dual devices mounted on
object to which the device is mounted. Table 1 shows a a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
comparison of the PowerPAK 1212-8, PowerPAK SO-8, nal layers and the backside layer are solid copper. The
standard TSSOP-8 and SO-8 equivalent steady state internal layers were chosen as solid copper to model the
performance. large power and ground planes common in many appli-
By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and
MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance
ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an
a PC board with a board temperature of 45 °C (Figure 4). area above 0.2 to 0.3 square inches of spreading copper
Suppose each device is dissipating 2 W. Using the junc- gives no additional thermal performance improvement.
tion-to-foot thermal resistance characteristics of the A subsequent experiment was run where the copper on
PowerPAK 1212-8 and the other SMT packages, die the back-side was reduced, first to 50 % in stripes to
temperatures are determined to be 49.8 °C for the Pow- mimic circuit traces, and then totally removed. No signif-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for icant effect was observed.
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Document Number 71681 www.vishay.com

03-Mar-06 3
AN822
Vishay Siliconix
105 130
Spreading Copper (sq. in.) 120 Spreading Copper (sq. in.)

95
110
85
100
RthJ A (°C/W)
RthJA (°C/W)
75 90
80
65 50 % 100 %
70
100 %
55 0%
50 % 60
0%
45 50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac-
1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal
been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies
mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run
smaller than the standard TSSOP-8. cooler, keeps rDS(ON) low, and permits the device to
Recommended PowerPAK 1212-8 land patterns are handle more current than a same- or larger-size MOS-
provided to aid in PC board layout for designs using this FET die in the standard TSSOP-8 or SO-8 packages.
new package.
www.vishay.com Document Number 71681

4 03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.152
(3.860)
0.039 0.068 0.010

(0.990) (1.725) (0.255)
0.016
(0.405)
(2.235)
(2.390)
0.088
0.094
0.026
(0.660)
0.025 0.030
(0.635) (0.760)
Recommended Minimum Pads

Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72597 www.vishay.com

Revision: 21-Jan-08 7
VISHAY SILICONIX
Power MOSFETs Application Note 914
"PowerPAK 1212-8", The Proven Automotive Package

By Kandarp Pandya
INTRODUCTION
This application note presents useful information on the
PowerPAK 1212-8 to facilitate SQE and design engineers.
Vishay introduced the PowerPAK power MOSFET package
family in the late 1990s to provide a thermally efficient
solution for the computer and telecom markets.
PowerPAK’s combination of a small form factor and high
power handling capabilities quickly brought industry-wide
acceptance in various applications such as dc-to-dc power
supplies, point of load, and control actuators. In most such
applications, the PowerPAK SO-8 and often the PowerPAK
1212-8 can replace the much larger and bulkier DPAK.
The automotive industry embraces a new package type only
after a track record has been established and extensive
Fig. 1 - PowerPAK 1212-8 Single
testing has been carried out both by manufacturers and
systems engineers. The PowerPAK 1212-8 has undoubtedly
won the industry’s acceptance and has been successfully
tested for AEC-Q101 compliance. The package has also
successfully been tested on a 16-layer PC board assembly
for solder joint reliability, passing the temperature cycles,
including the re-work, as per IPC 9701 test guidelines.
Automotive designers have ventured to use the PowerPAK
1212-8 in such crucial applications as engine control units
(ECU) and fuel injection systems. These applications
demand power cycling and some UIS capabilities.
PowerPAK’s reliability has likewise encouraged designers to
use the PowerPAK 1212-8 to replace die-level
implementations, thereby eliminating the associated
assembly costs while utilizing well established reflow
processes. As of April 2010, more than 5.5 million
PowerPAK power MOSFETs had been shipped to Vishay
Fig. 2 - PowerPAK 1212-8 Single and Dual
APPLICATION NOTE
automotive customers worldwide.
TABLE 1 - PACKAGE COMPARISON

PACKAGE DIMENSION (mm) PCB AREA (mm2) COMPARABLE PART POWER RATING (W)
PowerPAK 1212-8 3.4 x 3.4 x 1.12 11.56 1.5
SOIC-8 5.0 x 4.0 x 1.75 20 1.7
DPAK 10.41 x 6.73 x 2.38 70.06 2.0

Revision: 17-May-10 1
Vishay Siliconix
0.172
(4.369)
0.028
(0.711)
(6.248)
0.246
(3.861)
0.152
0.047
(1.194)
0.022 0.050
Fig. 3 - SOIC-8 (0.559) (1.270)
Fig. 6 - SOIC-8
0.224
(5.690)
(6.180)
0.243
(10.668)
0.420
(2.202)
0.087
Fig. 4 - DPAK (2.286)
0.090
RECOMMENDED MINIMUM PADS

0.180 0.055
(4.572) (1.397)
0.152
(3.860) Fig. 7 - DPAK (TO-252)
0.039 0.068
(0.990) (1.725) AEC-Q101 COMPLIANCE FOR AUTOMOTIVE
0.016 APPLICATIONS
(0.405)
The power temperature cycling test specified by Automotive
APPLICATION NOTE
0.039 0.010
(0.990) (0.255) Electronic Council document AEC Q101 for discrete
components is one of the most crucial tests for automotive
0.094 applications. The test requires temperature cycling of the
(2.390)
die with a delta of 100 °C by means of active power
0.039 dissipation in the die. This process puts severe thermal
0.026 (0.990) stresses on the package from the inside out. The solder
(0.660)
joints on the PCB assembly must also sustain the thermal
0.025 0.030 stress. PowerPAK 1212-8 was designed to address both
(0.635) (0.760) these aspects of thermal stress and has thus achieved
AEC Q101 qualification as well as passing further DV/PV
Fig. 5 - PowerPAK 1212-8 Dual tests at the automotive electronics design center. The
AEC-Q101 qualification test definitions are given in the
www.vishay.com Document Number: 72146

2 Revision: 17-May-10
Vishay Siliconix
following table:
TABLE 2 - QUALIFICATION TEST DEFINITIONS

SAMPLE ACCEPT REFERENCE
DATA # OF
# STRESS ABRV NOTE SIZE PER ON # (CURRENT ADDITIONAL REQUIREMENTS
TYPE LOTS
LOT FAILED REVISION
Tested per duration indicated in Timing
Requirements table on Page 13.
Intermittent TA = 25 °C. Devices powered to insure
DGTU 1 MIL-STD-750
10 Operational IOL 1 77 0 TJ 100 °C (not to exceed absolute
WP Note B Method 1037
Life maximum ratings).
Test before and after IOL as
a minimum.
Perform PTC if TJ 100 °C cannot be
achieved with IOL. Tested per duration
indicated for Timing Requirements in
Power and
10 DGTU 1 JESD22 Table 2A. Devices powered and
Temperature PTC 1 77 0
alt W Note B A-105 chamber cycled to insure TJ 100 °C
Cycle
(not to exceed absolute maximum
ratings). Test before and after PTC as
a minimum.
TABLE 2A - INTERMITTENT OPERATIONAL LIFE (TEST 10) OR POWER TEMP CYCLING

(ITEM 10ALT) TIMING REQUIREMENTS
NUMBER OF CYCLES NUMBER OF CYCLES
PACKAGE TYPE TIME PER CYCLE
REQUIRED TJ  100 °C REQUIRED TJ  125 °C
Small (e.g. SMD SOTS thru
15 000 7500 2 min. on/2 min. off
DPAK, and all LEDs)
Medium (e.g. TO-220, D2PAK) 8572 4286 3.5 min. on/3.5 min. off
Large (e.g. TO-3, TO-247) 6000 3000 5 min. on/5 min. off
Leadless 60 000/(x+y) 30 000/(x+y) Fastest capable (minimum 2min.
Not to exceed: 15 000 cycles 7500 cycles on/off) x min. on + y min. off
Note
• Example 1: A package capable of 2 min. on/4 min. off would require 10 000 cycles [60 000/(2 + 4)] at TJ  100 °C or 5000 cycles at
TJ  125 °C
• Example 2: A package capable of 1 min. on/1 min. off would require 15 000 cycles at TJ  100 °C or 7500 cycles at TJ  125 °C
All Vishay Siliconix automotive grade, AEC-Q101 qualified different solder paste and reflow profiles," web link:
power MOSFETs are numbered with an SQ prefix, i.e. http://www.vishay.com/docs/72116/72116.pdf.
SQxxx.
APPLICATION NOTE
The second DOE used a16-layer FR4 PC board with

SOLDER JOINT RELIABILITY ON FR4 PC dimensions of 130 mm x 115 mm x 3.175 mm. Refer to
BOARDS figure 8. This considerable thermal mass subjects the solder
The PowerPAK 1212-8 is qualified for Solder Joint Reliability joint to considerably severe stress during temperature
based on the guidelines stated in IPC 9701. Two separate cycling. Such a PCB design thus covers most of the extreme
DOEs were conducted with different third-party vendors for applications. The layer stack comprised two outer copper
PC board assembly and temperature cycle testing. layers of 35 μm (1.0 oz.) and 14 inner copper layers of 12 μm
The first DOE employed simple double-sided. 2-layer FR4 (0.5 oz.). Each insulation layer of the FR-4 in between is
PCB measuring 50 mm x 50 mm x 1.5 mm with 0.076 mm 231 μm (7709 μin.). Appendix A covers the PCB
(2 oz.) copper on both sides. A detailed test description is specifications. For this experiment, an immersion silver
covered in application note AN825 "The Solderability of the board finish was used as per recommendations from
PowerPAK SO-8 and PowerPAK 1212-8 when using external contract manufacturers.

Vishay Siliconix
each part. Refer to figure 10.
Fig. 9 - Daisy Chain Layout
Pin 1
Fig. 8 - FR4 16-layer PCB
Overview of Assembly Process

(1) Lead (Pb)-free and tin-lead solder paste test samples
were used:
a. Lead (Pb)-free solder paste SAC-387 (Tamura
TLF-206-93G)
b. Tin-lead (Sn-Pb) no-clean solder paste Sn63-Pb37 Fig. 10 - Component Modification for Daisy Chain Connection
(Alpha Metal UP78)
(2) A suitable lead (Pb)-free reflow assembly process was Evenly distribute the samples on 6 PC board. Each PCB
developed by multiple experiments involving different consisted of seven PowerPAK 1212-8 dual parts. Thus the
parameters such as aperture, stencil thickness, solder 8th loaction on the PBC is unused. Identify and re-work last
paste printing pressure. Also various solder pastes were two parts from the first five PC boards. Total 10 re-worked
experimented with to determine suitability of a paste. parts.
(3) In addition, a control lot was employed using regular Re-Work Steps
parts and tin-lead (Sn-Pb) solder paste. The latter • Removing existing part using hot air BGA re-work station
establishes a base line for comparison. (laboratory setup)
IPC 9710 GUIDELINES FOR TEMPERATURE • Clean up pads using soldering iron and de-soldering wick
CYCLING TEST FOR SOLDER JOINT • Solder bump pads using a soldering iron and solder wire
RELIABILITY SAC 305
Sample size: 42 pieces of PowerPAK 1212-8 dual • Apply no clean gel flux on pads
APPLICATION NOTE
Test vehicle: PCB designed to connect each pin of a part in • Place fresh component using hot air BGA rework station
a daisy chain and terminated on end connector to facilitate • Solder the component using hot-air BGA rework station
monitoring the daisy chain for each part on an automatic using reflow profile shown in figure 12
scanner. The PCB design also facilitates isolating each part
DOE Reflow Process Development
and remove from the PCB assembly for further analysis,
without disturbing the remaining parts’ daisy chains. Refer The goal here is to develop/define a reflow process that can
to figure 9. maintain the solder void level = < 20 %. The key variables
are solder paste and stencil design - aspect ratio, aperture
This DOE involves the part modifications: (a) Dies are
opening, machine parameters such as solder paste printing
dummy - no electrical connections. (b) Place internal bond
speed, pressure etc. All this eventually turns into in-house
wire jumpers - shown dotted blue lines - between two
expertise of the assembly house/contract manufacturers.
consecutive pins in pairs. The later in conjunction with the
2DX and if necessary 5DX x-ray results help narrow down
PCB layout facilitates a single daisy chain connection for

Vishay Siliconix
the solder paste selection and profile tweaking. Metal UP78)
Equipment and Material • 4-mil and 5-mil stencils with a variety of aperture and
• EKRA E5 solder paste printer aspect ratios
• Juki E2060 pick and place machine • Vishay PowerPAK components
• BTU Pyramax 98 reflow oven • Vishay Siliconix PCB version SMD125T16L_Ver C Side A
• Agilent 5DX Series 5300 laminography X-ray Reflow Profile Definitions
• Nicolet NXR-1400 transmission X-ray • Ramp-to-spike: RTS, figure 11
• 30x microscope • Ramp-soak-spike: Reg RSS, figure 12
• Lead (Pb)-free solder paste SAC-387 (Tamura • Ramp-long-soak-spike: Long RSS, figure 13
TLF-206-93G) • Ramp-soak-spike: Reg RSS for tin-lead (Sn63/Pb37)
• Tin-lead (Sn-Pb) no-clean solder paste Sn63-Pb37 (Alpha solder paste, figure 14
Peak temp. 235 °C

Time above 220 °C: 30 s
Soak time (120 °C to 200 °C): 70 s
Fig. 11 - RTS Profile for Lead (Pb)-free Solder Paste
APPLICATION NOTE
Peak temp. 237 °C


Vishay Siliconix
Fig. 12 - RSS Profile for Lead (Pb)-free Solder Paste
Peak temp. 235 °C

Soak time (120 °C to 200 °C): 159 s
Fig. 13 - LRSS Profile for Lead (Pb)-free Solder Paste
Peak temp. 215 °C

Soak time (140 °C to 160 °C): 54 s
Fig. 14 - RSS Profile for Tin Lead (Sn63/Pb37) Solder Paste

APPLICATION NOTE
TABLE 3 - ASSEMBLY PARAMETERS

STENCIL APERTURE DESIGN
VERSION COMP TYPE BUILD QTY PROFILE
THICKNESS SIGNAL (MILS) GROUND
AA PowerPAK 1212D 7 RSS 4 mils 16.8 x 44 Equal to Comp.

Vishay Siliconix
Fig. 15 - Best Case Soldering Fig. 16 - Worst Case Soldering
Conclusions and Recommendations of the DOE

• The minimum acceptable aspect ratio (smallest aperture opening/stencil thickness) is 2.5
• The minimum acceptable area ratio (LxW / 2(L + W)T) is 0.8
• The RSS profile shown in figure 12 is recommended for lead (Pb)-free solder paste
• The RSS profile shown in figure 14 is recommended for tin-lead solder paste
PHASE II SOLDER JOINT RELIABILITY STUDY

Temperature Cycling
• 3000 cycles of 0 °C to 100 °C temp. cycling with event recording for Daisy-Chain solder joint
Vishay board # 1
0 °C to 100°C
10 min. ramp and 10 min. dwell
120
110
100
90
80
70
60 TC 15
°C
50
40
30
20
10
0
APPLICATION NOTE
18:35
18:40
18:45
18:50
18:55
19:00
19:05
19:10
19:15
19:20
19:25
19:30
19:35
- 10
- 20
Time
Vishay PCB A Solderability Data

IPC9701 • Status
Cycling • 3000 Temp. cycles completed
0/100 40 min • Statistics
cycle
PACKAGE FIRST FAIL # FAILED % FAILED SOLDER

PPAK 1212D 0 0% Lead-free

Vishay Siliconix
SLOT # BOARD # PACKAGE PCB DES. PCB SIDE SITE ID NET # FAIL CYCLE
7 1 PowerPAK 1212D A Front U1 97
7 1 N/A A Front U8 104 N/A
APPLICATION NOTE


Vishay Siliconix
Summary
• PowerPAK 1212 can replace the SOIC-8 and DPAK in
applications requiring power dissipation up to 1.5 W.
• AEC-Q101 qualification proves the ruggedness
demanded by automotive applications.
• IPC-9701 qualification establishes solderability, both for
the simple two-layer PCB described in the application
note AN825 and in the toughest board design described
in the DOE above.
• The purpose of the DOE is to exemplify a successful
assembly for a given PCB board assembly and
manufacturing process. However, these simple guidelines
can be used for developing the pad designs, solder
profiles, aperture design and other manufacturing process
parameters for successful reflow assembly of PowerPAK
1212-8 package in other PC board designs. However, we
should note that each individual assembly may
necessitate parameter tweaking to match the assembly
house set-up. The assembly house internal expertise
usually evolves the suitable process.
APPLICATION NOTE

Part Marking Information
www.vishay.com
Vishay Siliconix
Devices:
PowerPAK® SO-8, PowerPAK SO-8L
PowerPAK 1212-8, PowerPAK 1212-8S, PowerPAK 1212-8W
PowerPAIR® 6 x 3.7, PowerPAIR 6 x 5, PowerPAIR 3 x 3
Single and Dual
7401
LL
TYWF
7401 = Example Base Part Number or marking code a
= Siliconix Logo
LL = Lot Code
= ESD Symbol
= Pin 1 Indicator
T = Assembly Factory Code
Y = Year Code
W = Week Code
F = Wafer Fab Code
The current marking strategy is reflected. Contact your local sales representative for historical marking strategies for these
packages.
Note
a. These digits will be a code, if indicated on the datasheet. Otherwise, the digits will be the base number like indicated in the
example.
Revision: 08-Jun-15 1 Document Number: 72758
Device Orientation
www.vishay.com
Vishay Siliconix
Device Orientation
PowerPAK® 1212-8, PowerPAK 1212-8S, PowerPAK 1212-8W
PowerPAK SO-8
DEVICE ORIENTATION
PACKAGE METHOD
PowerPAK 1212-8 T1
PowerPAK 1212-8S T1
PowerPAK 1212-8W T1
PowerPAK SO-8 T1
User Direction of Feed
Revision control of this drawing is maintained through Document Control, Pack Specification-PACK-0007-14
08-Jun-15 1 Document Number: 72724
Tape Information
www.vishay.com
Vishay Siliconix
PowerPAK® 1212
8.00
1.75 ± 0.10
2.00 ± 0.05 see note 6 + 0.1
Ø 1.50 0.0
4.00 see note 1
0.30 ± 0.05 Ø 1.50 min. A
R0.2 max.
(R0.3 max. for version 1)
12.0 ± 0.3
Bo
5.5 ± 0.05 see note 6

Ko Ao A
R0.3 typ.
Section A-A (R.O.5 typ. for version 1)
Version A0 B0 K0
-1 3.7 ± 0.1 3.7 ± 0.1 1.4 ± 0.1
- 2 (TW only) 3.6 ± 0.1 3.6 ± 0.1 1.4 ± 0.1
Notes
(1) 10 sprocket hole pitch cumulative tolerance ± 0.2
(2) Camber not to exceed 1 mm in 100 mm, also not to exceed 1.5 cm in 1 m actually
(3) Material: black conductive or black static dissipative
(4) A and B measured on a plane 0.3 mm above the bottom of the pocket
0 0
(5) K measured from a plane on the inside bottom of the pocket to the top surface of the carrier
0
(6) It should be measured from:
a. sprocket hole to pocket center
and
b. sprocket hole to pocket hole
(7) All sizes in mm unless specified
(8) Tolerances will be ± 0.1 mm unless specified
(9) Vishay part number must be labeled at all reels of carrier tape
(10) Surface resistivity: 1 x 104 to 1 x 1111 
QUANTITY PER REEL

T1 3000
ECN: C18-0765-Rev. G, 02-Jul-2018
DWG: 90-2379-X
Revision: 02-Jul-2018 1 Document Number: 71383

Reel Information
www.vishay.com
Vishay Siliconix
Reel
330 mm Reel (Lock Reel)
Measured
at hub
Open
Vender’s logo (50 x 15 ref)
Notes
1. Material: antistatic or conductor plastic
2. All dimensions in mm
3. ESD-surface resistivity -104 Ω to 1011 Ω
4. Color: black
VER APPLICATION A W TAPE WIDTH H T

SOIC-14/16 PowerPAK MLF 9 x 9
TO-251 (Short Lead) PowerPAK MLP 6 x 6
TO-252/TO-252 (Reverse Lead) MLF 8 x 8 +2
-1 PLCC-20 PowerPAK 8 x 8L 330 ± 2 16.4 16 100 ± 1 2.5 ± 0.5
TSSOP-8/14/16/20/28 PowerPAK 8 x 8 -0
SSOP-24 MLP57/MLP66/MLP77
SOIC-16 (W) PowerPAK 5 x 9
SOIC-8 (N), SOIC-8 (N) epad
PolarPAK®
MSOP-8/10
PowerPAIR® 6 x 5
PowerPAK® SO-8
PowerPAIR 6 x 3 J
PowerPAK 1212
PowerPAIR SO-8L +2
-2 PowerPAK 1212-8W 330 ± 2 12.4 12 100 ± 1 2.5 ± 0.5
PolarPAK1215 -0
MICRO FOOT®
PowerPAIR 6 x 3.7
MLP33-5, MLP33-8, MLP33-10
PowerPAK SO-8L
QFN (4 x 4)/(3 x 3)/DFN-10 (3 x 3)
PKSO8DCWL
MLP44/MLP4535/MLP55/MLP65
SOT-23/143 TSOP-6, 1206-8 ChipFET +1.5
-4 SC70 PowerPAK SC70 330 ± 2 8.4 8.4 100 ± 1 2.5 ± 0.5
MICRO FOOT PowerPAK SC75 -0
SOIC-20W/24W PowerPAK MLF 10 x 10

D2PAK MLP60-A6C +2
-5 330 ± 2 24.4 24 100 ± 1 2.5 ± 0.5
SSOP-28 -0
QSOP-36
+2
-8 KGD 330 ± 2 16.4 16 130 ± 1 2.5 ± 0.5
-0
Revision: 18-Mar-2019 1 Document Number: 71385
Reel Information
www.vishay.com
Vishay Siliconix
178 mm Reel (Complete Reel)
Front Back Side
Vender’s logo (24 x 7 ref)
Notes
1. Material: antistatic or conductor plastic
2. All dimensions in mm
3. ESD-surface resistivity -104 Ω to 1011 Ω
4. Color: black
VER APPLICATION A W TAPE WIDTH H T

PowerPAK SC75
SOT-23/143 MiniQFN
TSOP-5/6/SC70JW-8L
1206-8 ChipFET® PowerPAK MLP22-5
PowerPAK ChipFET
SC70/SC75A/SC89 PowerPAK SC75-6L (PIC)
MICRO FOOT +1.5
-3 SC-89 (SOT-666) PowerPAK TSC75-6L (PIC) 178 ± 2 8.4 8.4 62 ± 2 1.5 ± 0.5
TDFN4 1.2 x 1.6, -0
SOT23-5, 6 TDFN8 2 x 2
KGD
WCSP Thin PowerPAK SC-70
Thin PowerPAK SC-75
PowerPAK 0806 μDFN-6L 1 x 1
PowerPAK SC70
μDFN-4L 1 x 1
MICRO FOOT KGD +2
-7 178 ± 2 12.4 12 55 ± 2 1.6 ± 0.25
PowerPAK 2 x 5 -0
ECN: T19-0069-Rev. BX, 18-Mar-2019
DWG: 93-5211-X
Revision: 18-Mar-2019 2 Document Number: 71385
Package Reliability
www.vishay.com
Vishay Siliconix
ENVIRONMENTAL AND PACKAGE TESTING DATA FOR PowerPAK® 1212-8

STRESS SAMPLE SIZE DEVICE HR./CYC CONDITION TOTAL FAILS FAIL PERCENTAGE
BOND INT 440 220 000 200 °C + N2 0 0
HAST 5880 580 046 130 °C, 85 % RH 0 0
Pressure Pot 6048 580 608 121°, 15 PSIG 0 0
Solder DUNK 379 1137 260 °C, 10 s 0 0
Solderability 45 360 883 M2003 0 0
Temp. Cycle 7156 6 063 580 -55 °C to 150 °C 0 0
Revision: 22-Dec-15 1 Document Number: 72459

Silicon Technology Reliability
www.vishay.com
Vishay Siliconix
N-CHANNEL ACCELERATED OPERATING LIFE TEST RESULT

Sample Size 61 467
Equivalent Device Hours 16 773 973 749
Failure Rate in FIT 2.033
Failure Rate in FIT is calculated according to JEDEC Standard JESD85, Methods for Calculating Failure Rates in Units of FITs,
based on accelerated high temperature operating life test results by using an apparent activation energy of 0.7 eV. The junction
temperature of the device at use is assumed to be 55 °C. A constant failure rate distribution is assumed. The upper confidence
bound of the failure rate is 60 %.
Revision: 23-Apr-12 1 Document Number: 72541

Package Reliability
www.vishay.com
Vishay Siliconix
ENVIRONMENTAL AND PACKAGE TESTING DATA FOR PowerPAK® 1212-8

STRESS SAMPLE SIZE DEVICE HR./CYC CONDITION TOTAL FAILS FAIL PERCENTAGE
BOND INT 640 320 000 200 °C + N2 0 0.00
HAST 2756 275 600 130 °C, 85 % RH 0 0.00
Power Cycle 1394 20 582 000 DELTA TJ = 100 °C 0 0.00
Pressure Pot 2842 272 832 121°, 15 PSIG 0 0.00
Solder DUNK 1420 4260 260 °C, 10 s 0 0.00
Solderability 315 2520 883 M2003 0 0.00
Temp. Cycle 3478 3 014 000 -55 °C to 150 °C 0 0.00
Revision: 16-Dec-15 1 Document Number: 69631

Silicon Technology Reliability
www.vishay.com
Vishay Siliconix
N-CHANNEL ACCELERATED OPERATING LIFE TEST RESULT

Sample Size 33 325
Equivalent Device Hours 16 824 598 011
Failure Rate in FIT 1.545
Failure Rate in FIT is calculated according to JEDEC Standard JESD85, Methods for Calculating Failure Rates in Units of FITs,
based on accelerated high temperature operating life test results by using an apparent activation energy of 0.7 eV. The junction
temperature of the device at use is assumed to be 55 °C. A constant failure rate distribution is assumed. The upper confidence
bound of the failure rate is 60 %.
Revision: 15-May-12 1 Document Number: 73885

Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17 1 Document Number: 91000

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SQ7414EN

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

THERMAL RESISTANCE RATINGS

S13-1462-Rev. E, 01-Jul-13 1 Document Number: 74489

SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

S13-1462-Rev. E, 01-Jul-13 2 Document Number: 74489

I D - Drain Current (A)

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

S13-1462-Rev. E, 01-Jul-13 3 Document Number: 74489

R DS(on) - On-Resistance ()

VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Threshold Voltage Single Pulse Power, Junction-to-Ambient

S13-1462-Rev. E, 01-Jul-13 4 Document Number: 74489

Duty Cycle = 0.5

Normalized Thermal Transient Impedance, Junction-to-Ambient

Duty Cycle = 0.5

0.1 Single Pulse

Normalized Thermal Transient Impedance, Junction-to-Case

S13-1462-Rev. E, 01-Jul-13 5 Document Number: 74489

Revison: 09-Jan-17 1 Document Number: 71656

Revison: 27-Jul-15 1 Document Number: 74786

PowerPAK® 1212 Mounting and Thermal Considerations

Figure 1. PowerPAK 1212 Devices

Document Number 71681 www.vishay.com

PowerPAK 1212 DUAL

3 ° C/s (max) 4 ° C/s (max)

3° C/s (max) 60 s (min) Reflow Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

www.vishay.com Document Number 71681

TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

PowerPAK 1212 Standard SO-8 Standard TSSOP-8 TSOP-6

2.4 °C/W 20 °C/W 52 °C/W 40 °C/W

Figure 4. Temperature of Devices on a PC Board

Introduction Spreading Copper

Document Number 71681 www.vishay.com

Spreading Copper (sq. in.) 120 Spreading Copper (sq. in.)

Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance

www.vishay.com Document Number 71681

RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single

0.039 0.068 0.010

Recommended Minimum Pads

Document Number: 72597 www.vishay.com

Power MOSFETs Application Note 914

"PowerPAK 1212-8", The Proven Automotive Package

automotive customers worldwide.

TABLE 1 - PACKAGE COMPARISON

Document Number: 72146 www.vishay.com

"PowerPAK 1212-8", The Proven Automotive Package

RECOMMENDED MINIMUM PADS

www.vishay.com Document Number: 72146

"PowerPAK 1212-8", The Proven Automotive Package

TABLE 2 - QUALIFICATION TEST DEFINITIONS

TABLE 2A - INTERMITTENT OPERATIONAL LIFE (TEST 10) OR POWER TEMP CYCLING