DEC30032 – COMPUTER

ARCHITECTURE & ORGANIZATION

CHAPTER 3
ARITHMETIC LOGIC UNIT
(ALU)

LECTURER : PN. NOOR AZILA BT AHMAD ZAKI

 INTRODUCTION
• An ALU is a digital circuit that performs arithmetic and logical
operations.
• Where two words can be added, subtracted, multiplied or
divided.
• The ALU is a fundamental building block of the central
processing unit (CPU) of a computer.
• The ALU has direct input and output access to the processor
controller, main memory, and input/output devices.
• The input consists of an instruction word that contains an
operation code, one or more operands, and sometimes a
format code.
Diagram of ALU
 INTEGER REPRESENT IN ALU
• An ALU process numbers using the same
format.
• The format of modern processors is the two's
complement binary number representation.
• In binary number system, numbers can be
representing with just the digits zero and one.
• For purpose of computer storage and
processing, only binary digits (0 and 1) may
used to represent numbers.
 ADDER
• The most basic arithmetic operation is the
addition of two binary digits.
• A combinational circuit that adds two bits,
according the scheme outlined below, is called
a half adder.
• A full adder is one that adds three bits, the
third produced from a previous addition
operation.
 HALF ADDER
• A half adder is used to add two binary digits
together, A and B.
• It produces S, the sum of A and B, and the
corresponding carry out, Cout.

a) Logic Diagram b) Logic Symbol

 Truth Table for Half Adder
A B SUM Cout
(S)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 Boolean equation – Half Adder
• SUM, S
SUM (∑) = A  B

• CARRY OUT
Cout = AB
 FULL ADDER
• A full adder is a combinational circuit that performs the
arithmetic sum of three bits: A, B and a carry in, C.
• Also, as in the case of the half adder, the full adder
produces the corresponding sum, S, and a carry out
Cout.
• A full adder maybe designed by two half adders or
more.
• The sum of A and B are fed to a second half adder,
which then adds it to the carry in C to generate the
final sum S.
• The carry out, Co, is the result of an OR operation
taken from the carry outs of both half adders.
Logic Diagram
Logic Symbol
Truth table for full adder
A B Cin SUM Cout
(S)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 PARALLEL BINARY ADDER
General block diagram
4 Bit Parallel Binary Adder
1) Consider the addition of the following 4-bit binary
numbers:
Where
A3 = 0, A2 = 1, A1 = 1, A0 = 1
B3 = 1, B2 = 1, B1 = 0, B0= 0, Cin = 0
1
1 0 111
+ 1100
10011

Sum = 0011, Cout /C4 = 1

2) Consider the addition of the following 4-bit binary numbers:
Where
A3 = 1, A2 = 1, A1 = 1, A0 = 1
B3 = 1, B2 = 0, B1 = 1, B0= 1, Cin = 0

1 1 1
11 1 1 1
1 01 1
+ 1
11 01 1

Sum = 1011, Cout /C4 = 1

 EXERCISE
With aided 4 bit parallel adder
diagram, show how to add a
binary number, A = 10112 with
B = 11012 and the carry is, Cin = 12
 Answer

 The answer = 11001 @ Sum = 1001, Cout = 1

SUBTRACTOR
LOGIC DIAGRAM – HALF SUBTRACTOR
TRUTH TABLE – HALF SUBTRACTOR

INPUT OUTPUT
A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
LOGIC DIAGRAM – FULL SUBTRACTOR
TRUTH TABLE – FULL SUBTRACTOR
INPUT OUTPUT
C
A B DIFFERENCE BORROW
(BORin)

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
4 BIT ADDER SUBTRACTOR
• When M = 0, the full–adders see A + B
because B  0 = B.
• When M = 1, the full–adders see A + B’ + 1
because B 1 = B’ and C0 = M.
• B’ is the 1’s complement of B
• So (B’ + 1) is the 2’s complement of B.
a) 2 bit Parallel Binary Adder Subtractor have input A = 10 and
B = 01. Calculate the output for both situation M=0 and M=1.

ANSWER
When M=0, Adder process = A + B

A+B=10 +01=11  SUM = 1 1

When M=1, Subtract process = A + B’ + 1

B’ + 1 = 1 0 + 1 = 1 1

so, A + (B’ +1) = 1 0 + 1 1 = 1 0 1  SUM = 0 1, COUT = 1

b) 4 bit Parallel Binary Adder Subtractor have input A = 1100 and B =
1001. Calculate the output for both situation M=0 and M=1.

ANSWER
When M=0, Adder process = A + B

A+B = 1 1100
+ 1001
10101

When M=1, Subtract process = A + B’ + 1

B’ + 1 = 0 1 1 0 + 1 = 0 1 1 1
1
so, A + (B’ +1) = 1 1 100
+ 0 111
10 011
SHIFT REGISTER
• Is a cascade of flip flops & sharing the same
clock.
• Shift registers can have both parallel and serial
inputs and outputs.
A) Serial-in, parallel-out (SIPO)
B) Parallel-in, serial-out (PISO)
• A flip-flop stores 1 bit of data/information.
• When a set of n flip-flops is used to store n
bits of information, these combination of flip
flop called a REGISTER.
• A register that provides the ability to shift its
contents is called a SHIFT REGISTER.
• A register is a digital circuit with 2 basic
functions
1. Data storage
2. Data movement
• The shift capability of a register permits the
movement of data from stage to stage within
the register
• Sample output of Shift Register
 Function of Shift Register in ALU
1. To produce time delay
 The serial in-serial out (SISO) shift register can be used as a time
delay device.
2. To simplify combinational logic
 The ring counter technique can be effectively utilized to
implement synchronous sequential circuits.
3. To convert serial data to parallel data
 Serial In Parallel Out Register can be used to convert serial data
from external device to parallel format to communicate with
external devices or microprocessor.
4. Memory device
 Most of the registers possess no characteristic internal sequence
of states. All the flip-flops are driven by a common clock, and all
are set or reset simultaneously make it suitable as memory
device.
MULTIPLEXER
• Multiplexer (MUX) as known as DATA
SELECTOR.
• MUX is a logic circuit that accepts several
digital data input and SELECT ONE of them at
any given time to pass on to the output
• The multiplexer has several data-input lines
and a single output line.
• It also has data-select inputs, which permits
digital data on any one of the inputs to be
switched to the output line.
 MULTIPLEXER EIGHT INPUT
Block Diagram MUX 8 to 1
Please sketch the logic diagram
for MUX 8 to 1
 8 Bit Multiplexer
• An 8-to-1 multiplexer consists of eight data inputs I0 through I7,
three input select lines S2 through S0 and a single output line F.
• Depending on the select lines combinations, multiplexer decodes
the inputs.
• Since the number data bits given to the MUX are eight
(1 input = 3 bits) are needed to select one of the eight data bits.
• In all types of digital system applications, multiplexers allows
multiple inputs to be connected independently to a single output,
these are found in variety of applications including data routing,
logic function generators, control sequencers, parallel-to-serial
converters, etc.
COMPARATOR
• Digital or Binary Comparators are made up from
standard AND, NOR and NOT gates that compare the digital
signals present at their input terminals and produce an
output depending upon the condition of those inputs.

• There are two main types of Digital Comparator are;

i) Identity Comparator
an Identity Comparator is a digital comparator that has only
one output terminal for when A = B either “HIGH” A = B =
1 or “LOW” A = B = 0
ii) Magnitude Comparator
Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater
than, A > B and less than A < B
• The purpose of a Digital Comparator is to
compare a set of variables or unknown numbers,
for example A (A1, A2, A3, …. An, etc) against that
of a constant or unknown value such as B (B1, B2,
B3, …. Bn, etc) and produce an output condition
or flag depending upon the result of the
comparison.
• For example, a magnitude comparator of two 1-
bits, (A and B) inputs would produce the
following three output conditions when
compared to each other.
• Which means: A is greater than B, A is equal
to B, and A is less than B
• This is useful if we want to compare two variables
and want to produce an output when any of the
above three conditions are achieved.
• For example, produce an output from a counter
when a certain count number is reached.
1 bit Digital Comparator Circuit
Find out the truth table for 1
bit comparator
Truth Table 1 bit Comparator
8 Bit Magnitude Comparator
• When comparing large binary or BCD numbers, to save
time the comparator starts by comparing the highest-order
bit (MSB) first.
• If equality exists, A = B then it compares the next lowest bit
and so on until it reaches the lowest-order bit, (LSB).
• If equality still exists then the two numbers are defined as
being equal.
• If inequality is found, either A > B or A < B the relationship
between the two numbers is determined and the
comparison between any additional lower order bits stops.
• Digital Comparator are used widely in Analogue-to-Digital
converters, (ADC) and Arithmetic Logic Units, (ALU) to
perform a variety of arithmetic operations.
THE END…