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Design of I2C Protocol in VHDL PDF
Design of I2C Protocol in VHDL PDF
Design of I2C Protocol in VHDL PDF
by AmCoder
•Two modes - 100 kbits/sec and 400 kbits/sec : slow and fast.
Pure RTL code is used. So the IP is easily portable across all FPGAs. Compact FSM based design using
internally generated clock ensures optimal area and performance.
Test Environment
While testing Master using I2C Slave IP, configure the slave code as per your requirements. You
may want to change the default clock frequency and slave address. Clock frequency should be
configured in the Master code too.
While on-board testing, don't forget pull-up resistors as SDA line is common drain output !!! Check
google for recommended pull-up resistor for different i2c speeds. I used 2.2K for 100 kHz.
If not using test bench and simulating the Master independently, carefully simulate SDA signal, as it
is a bi-directional signal (inout) signal. It has two drivers, master side and slave side. You should
know when to 'force' and when to 'unforce'.
SCL is unidirectional line. No need of pull-up.
Please go thru the IP Documentation thoroughly.
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