2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

16 Bit Power Efficient Carry Select Adder

Nidhi Gaur Anu Mehra Pradeep Kumar
Department of ECE, ASET Department of ECE, ASET Department of ECE, ASET
Amity University Uttar Pradesh Amity University Uttar Pradesh Amity University Uttar Pradesh
NOIDA, INDIA NOIDA, INDIA NOIDA, INDIA
ngaur@amity.edu amehra@amity.edu pkumar4@amity.edu

Sankalp Kallakuri
Mando Softech India Ltd
sankalp.kallakuri@gmail.com

Abstract— The paper presents a new and modified area
and power efficient carry select adder is proposed using
Weinberger architecture and it is compared for efficiency with
modified Carry Select Adder using Han Carlson, Brent Krung,
and Ling adder architectures along with conventional carry
select adder. Carry Select Adder proposed here using
Weinberger architecture turned out to be the best in terms of
area and power. Simulations of all five adder architectures are
performed in Xilinx Vivado tool version 14.4 and hardware
implementations are performed on zynq 7000 FPGA board
which uses 28nm technology.
Keywords— Carry Select Adder; zynq 7000 FPGA; Han
Carlson; Brent Kung; Weinberger architecture and Ling
architecture.
I. INTRODUCTION
In present day scenario, VLSI circuits with low power,
and low area are need of the hour. At the same time delay
remains an important parameter to enhance speed of circuit.
For any VLSI data path design, adders and multipliers form
an integral part of circuit and capable of deciding
performance and efficiency of circuit [1-4]. This paper aims
at implementation of power and area efficient adder circuits.
In 1962, Carry select Adder (CSLA) was designed by O.J.
Bedrij [5]. From the literature it is known that Conventional
CSLA is amongst the fastest adders since it overcomes the
issue of carry propagation. For two probable values of carry
(i.e. ‘1’ and ‘0’) parallel summation is calculated and
multiplexer selects the correct sum based on previous carry
generated (Figure 1) [5]. A number of adder architectures
already exist in literature and this paper aims at optimizing
the concept of all architectures in one to gain the maximum
optimization.
designed by replacing first stage RCA with BEC [9]. CSLA
modified with HCA is found to be delay efficient w.r.t.
CSLA implemented using KSA [10]. In comparative
performance study of existing fast adders, replacement of
RCA stage with Ling adder is found to be area and power
efficient [11,12].
B. Contributions
In this paper, a new CSLA architecture is proposed for
area and power optimization. Here Brent Kung stage in
regular BK CSLA is replaced by Weinberger stage. This
implementation is not reported in literature so far and found
to be power efficient when compared with existing
architectures. Comparative analysis is done by implementing
existing regular linear CSLA, modified Brent Kung CSLA,
modified Han – Carlson CSLA, modified Ling CSLA and
proposed modified Weinberger CSLA (W-CSLA)
architectures on 28nm zynq 7000 FPGA board. The new
proposed adder is area and power efficient. Comparative
analysis of designs is also presented. The working
methodology of our approach is described in Part III.
C. Paper Organization
Paper splits into five sections including introduction.
Section II describes existing modified CSLA designs and
their implementation. Section III describes the proposed
adder design. In section IV Simulation results and
comparison of power, area and delay for new design with
respect to existing designs are discussed. Conclusion of
paper is discussed in section V.

A. Related Research
A lot of work has been done in order to improve the
performance of Carry Select Adder. The CSLA architecture
is delay efficient but parallel implementation increments area
[5]. In a hybrid CSLA, dual Ripple Carry Adder (RCA) stage
was replaced by single RCA and Binary to Excess -1
Converter (BEC) to further improve speed of circuit [6].
Parallel Prefix Adders (PPA) also solves the problem of
carry propagation [7]. PPA designed so far includes Kogge
Stone Adder (KSA), Brent Kung Adder (BKA), Ladner
Fischer Adder (LFA), Han Carlson Adder (HCA), Ling
Fig. 1. Conventional Carry Select Adder
Adder (LA) and Weinberger Adder (WA) [8]. Parallel prefix
addition is done in three steps which include Pre processing,
Carry generation and post processing Stage. Limitation of II. MODIFIED CSLA ARCHITECTURES
PPA lies in large fanout and long interconnection wires
In present work various modified CSLA architectures
which enhance delay [7]. A CSLA implemented using PPA
have been studied and compared for power and area.
improves performance. Power efficient Brent Kung CSLA is

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

978-1-7281-1380-7/19/$31.00 ©2019 IEEE 558
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
A. 16-bit advanced CSLA
A conventional CSLA architecture comprises of two
RCA and a Multiplexer. RCA1 stage does sum and carry
calculation for input carry zero and RCA2 stage calculates
sum and carry for input carry one respectively. The output
for sum and carry is selected by the multiplexer, once the
correct carry in is known. Advanced CSLA is designed by
modifying the second RCA stage of CSLA with BEC
(Binary to excess-1 converter) [6]. Here RCA with Cin=1 is
replaced with BEC. The idea of using BEC is that it uses less
number of logic gates for its implementation. Here the
number of Ex-or gates are reduced. This reduces the area of
design. Figure 2 represents Block diagram of design.
Fig. 2. 16 Bit Advanced CSLA
B. Modified Linear Brent Kung CSLA
Modified linear BK CSLA is designed by replacing RCA
stage for Cin=0 with Brent Kung adder to improve delay of
circuit, and modifying the second stage, i.e. replacing RCA
for Cin=1 with BEC [9]. Architecture has 4 groups and three
stages. When linear BK adder is designed with BEC for
more number of bits then there is a significant reduction in
area. So, a 16-bit modified linear Brent Kung CSLA consists
of 3-stages. Four groups of 4-bit Brent kung at stage1
followed by three groups of N+1 bits i.e. 5-bit BEC, and the
last stage is 10:5 mux. Block diagram of design is
represented in Figure 3.
Fig. 3. Modified Linear Brent Kung CSLA
C. Modified Linear Ling CSLA
It is designed by a modification in Brent kung stage by
changing it with Ling adder [12]. Ling adder is a special case
of faster and cheaper carry look ahead adder. Special Ling
559
carry recurrence algorithm is used for parallel computation
of carry. In Ling algorithm carry computation complexity is
reduced at the cost of sum computational complexity.
Bitwise Generate and propagate signals are calculated as Gi=
Ai.Bi and Pi= Ai+Bi respectively. Propagate term is factored
from carry expression and Ling transformation is applied to
generate pseudo carry which enhances speed of circuit [30].
Modified adder consist of three stages, first stage with four
groups of 4-bit ling adder followed by three 5-bit BEC and
three 10:5 mux as the last stage (Figure 4). This is an area
optimized design.
Fig. 4. Modified Linear Ling CSLA
D. Modified Linear Han Carlson CSLA
Han Carlson adder is based on the idea of utilizing
Koggestone and Brent kung adder features, since
Koggestone is known to have the fastest speed and Brent
kung is known for less area consumption [29]. Modified Han
Carlson CSLA is designed again in the same manner by
replacing Brent kung stage with Han Carlson Adder. It
consists of four groups of 4-bit Han Carlson adder followed
by three groups of 5-bit BEC and lastly three groups of 10:5
mux (Figure 5). The area consumption by this design was
found to be same as that of conventional CSLA and power
consumption was found to be more than conventional linear
CSLA.
Fig. 5. Modified Linear Han Carlson CSLA
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

III. PROPOSED MODIFIED LINEAR CSLA USING WEINBERGER

ADDER (W-CSLA)

The adder proposed in this paper is based on low power and

less area consumption. The Block diagram of the proposed
16 Bit W-CSLA Architecture consists of three parts
• Weinberger adder
• Binary to Excees-1 Converter
• Multiplexer.

A simple Weinberger adder [13, 14] is known to have least

Fig. 7. Output waveform of 16 bit linear CSLA (Sum: 0000001010100010
area, so it is proposed in this design. Weinberger adder uses +1101110100111000= 1101111111111010, Carry: 0 )
the concept of parallel carry computation to enhance speed of
circuit. Special Weinberger recurrence algorithm is applied
for carry computation. The proposed adder is designed by
replacing Brent kung stage in modified Brent Kung adder
described in section II with Weinberger adder. The stages are
four groups of 4-bit Weinberger adder, three groups of 5-bit
BEC at second stage and 10:5 mux at the last i.e. at the third
stage. Carry C3 generated from first group is input to second
group and so on. The input carry can be ‘0’ or ‘1’ as
indicated by C3 (group 2). Calculation of sum and carry is
done at Weinberger stage and BEC stage and lastly mux
selects output of group 2 depending on value of C3. Hence
carry C7 and sum [7:4] is obtained at output of group 2.
Similarly output for rest of the blocks is obtained. For N-bit
Brent Kung stage N+1 BEC is used. This design consumed Fig. 8. Output waveform of CSLA using Brent kung CSLA (Sum:
less area (since BEC requires less number of logic gates than 0000001010100010 +1101110100111001= 1101111111111011, Carry: 0 )
RCA) and also low power as compared to above mentioned
designs in section II with a little compromise in delay.
Proposed architecture is depicted in Figure 6.

Fig. 9. Output waveform of CSLA using Ling (Sum: 0000001010100010

+1101110100111001= 1101111111111011, Carry: 0 )

Fig. 6. Proposed Modified Linear Wein Berger CSLA

IV. SIMULATION RESULTS AND DISCUSSION

All existing designs discussed in section II and proposed
design in section III are designed using Verilog HDL and
simulated in Xilinx Tools. Testbench has been generated
for all adders designs to test for all possible combination of
inputs. Each adder is coded and verified separately. Figures
7,8,9,10 and 11depict sample simulation results of 16 bit
advanced CSLA, CSLA using modified Brent Kung, CSLA
using Ling, CSLA using Han Carlson and proposed W- Fig. 10. Output waveform of CSLA using Han Carlson (Sum:
CSLA. 1111111111111111 +1111111111111111= 1111111111111110, Carry: 1 )

560
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

Ling CSLA

5.PROPOS 120 1 25 12.28

ED W-
CSLA

V. CONCLUSION
In this paper a new area and power efficient CSLA is
proposed which finds its application in various blocks of
digital circuit design including Vedic multiplier. This unit
could be used to optimize ALU designs, enhancing
Fig. 11. Output waveform of Proposed CSLA using Weinberger (Sum:
performance of DSP processors and datapath units.
0000001000010110 +1111110111101000= 1111111111111111, Carry: 0 )
REFERENCES
[1] M. Akila, C. Gowribala and S. Maflin Shaby (2016) ,
Table 1 presents comparative post synthesis report on 28nm ‘Implementation of High Speed Vedic Multiplier using Modified
ZYNQ- 7000 product family part name XC7z020clg484-1 Adder’, International Conference on Communication and Signal
Processing, pp. 2244-2248.
for all adders in terms of power, area and delay. A significant
[2] K. Ram Gavali and P. Kadam (2016), ‘VLSI Design of High Speed
improvement in dynamic power reduction is observed with Vedic Multiplier for FPGA implementation’, 2nd IEEE International
proposed W-CSLA. Comparative analysis of delay, area and Conference on Engineering and Technology.
power of all designs is shown in Figure 12. It can be [3] R. Raju and S. Veerakumar (2016), ‘Design and Implementation of
observed that with a little delay penalty power and area of Low power and High Performance Vedic Multiplier’, International
adder is improved. Conference on Communication and Signal Processing, pp. 0601-
0605.
[4] G. Challa Ram, D. Sudha Rani, Y. Rama Lakshmanna and K. Bala
Delay (In ns) Sindhuri (2016), ‘Area Efficient Modified Vedic Multiplier’,
International Conference on Circuit, Power and Computing
UTILIZATION OF SLICE LUT’S(TOTAL AVAILABLE-53200) Technologies.
DYNAMIC POWER(IN mW) [5] O.J. Bedrij (1962) ‘Carry Select Adder’, ,IRE Transactions on
Electronic Computer, p.p. 340-346.
50 [6] S. Parmar and K. Pal Singh (2013) ‘Design of High Speed Hybrid
40 Carry Select Adder’, International Conference on Advance
Computing (IACC), p.p. 1656-1663.
30
[7] J. Thomas, R. Pushpangadan and S. Jinesh (2015), ‘Comparative
20
Study of Performance Vedic Multipliers on the Basis of Adders
10 Used’, IEEE International WIE Conference on Electrical and
0 Computer Engineering (WIECON-ECE), pp. 325-328.
1.Regular Linear 2.Modified BK 3.Modified Han 4.Modified Ling 5.PROPOSED W- [8] N. Gaur, D. Tyagi, D. Kamboj and A. Mehra (2016), ‘Performance
CSLA CSLA Carlson CSLA CSLA CSLA Comparison of Adder Architectures on 28nm FPGA’, International
Conference on Advances in Computing Communication and
Automation.
Fig. 12. Comparative analysis of dynamic power, delay and area of [9] P. Saxena (2015), ‘Design of Low Power and High Speed Carry
implemented adder designs. Select Adder using Brent Kung Adder’, International Conference on
VLSI Systems, Architecture, Technology and Applications(VLSI-
SATA), 2015, p.p. 1-6.
TABLE I. COMPARATIVE ANALYSIS OF ADDERS IN TERMS OF [10] G. V. George and A. Thomas (2013) , ‘High performance Vedic
POWER, AREA AND DELAY Multiplier Using Han Carlson adder’, International Journal of
Engineering Research and Technology, ISSN: 2278-0181, Vol. 3
Issue 3, pp. 1875-1878.
ADDER Total DYNAM UTILIZATION Delay
[11] P. Kumar and M. Kiran (2013) ‘Design of Optimal Fast Adder’,
POW IC OF SLICE (In ns)
International Conference on Advanced Computing and
ER POWER LUT’S(TOTAL Communications Systems (ICACCS), p.p. 1-4.
(in (IN mW) AVAILABLE-
mW ) 53200) [12] D. N. Chakravarthy, J. Das and B. Islawath (2013), ‘Area Efficient
and High Speed CSLA’, International Journal of Conceptions on
Electronics and Communication, ISSN: 2357 – 2809, Vol. 1, Issue. 1,
1.Regular 124 4 28 10.75 pp. 11-14.
Linear
[13] A. Mehra, P. Kularia, A. Sharma, G. Batra, A. Rawat, N. Gaur (2014),
CSLA
‘Modified Booth Multiplier Architecture Using New (1,1,1) Adder’,
ARPN Journal of Engineering and Applied Sciences, (ISSN 1819-
2.Modified 126 6 29 11.88 6608 ), Issue 10, pp 7316-7319.
BK CSLA [14] R. Suganya and D. Meganathan (2015), ‘High Performance VLSI
Adders’, International Conference on Signal Processing,
Communication and Networking (ICSCN).
3.Modified 125 5 28 11.29
Han
Carlson
CSLA

4.Modified 125 5 25 11.75

561