Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 28 17:09:59 2020
| Host : DESKTOP-PPI8D0T running 64-bit major release (build 9200)
| Command : report_timing -from [all_inputs] -to [all_outputs] -file
C:/Users/Divya/Desktop/impl_timing_4_max.txt
| Design : woodley_multi
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
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Timing Report

Slack (MET) : 1.207ns (required time - arrival time)

Source: b[2]
(input port)
Destination: S[6]
Path Group: **default**
Path Type: Max at Slow Process Corner
Requirement: 9.000ns (MaxDelay Path 9.000ns)
Data Path Delay: 7.793ns (logic 3.772ns (48.401%) route 4.021ns
(51.599%))
Logic Levels: 4 (IBUF=1 LUT5=1 LUT6=1 OBUF=1)
Output Delay: 0.000ns
Timing Exception: MaxDelay Path 9.000ns

Location Delay type Incr(ns) Path(ns) Netlist

Resource(s)
-------------------------------------------------------------------
-------------------
Y4 0.000 0.000 f b[2] (IN)
net (fo=0) 0.000 0.000 b[2]
Y4 IBUF (Prop_ibuf_I_O) 0.945 0.945 f
b_IBUF[2]_inst/O
net (fo=16, routed) 1.610 2.555 b_IBUF[2]
SLICE_X2Y7 LUT6 (Prop_lut6_I3_O) 0.124 2.679 r
S_OBUF[6]_inst_i_2/O
net (fo=1, routed) 0.599 3.278
S_OBUF[6]_inst_i_2_n_0
SLICE_X0Y7 LUT5 (Prop_lut5_I0_O) 0.124 3.402 r
S_OBUF[6]_inst_i_1/O
net (fo=1, routed) 1.812 5.214 S_OBUF[6]
U6 OBUF (Prop_obuf_I_O) 2.580 7.793 r
S_OBUF[6]_inst/O
net (fo=0) 0.000 7.793 S[6]
U6 r S[6] (OUT)
-------------------------------------------------------------------
-------------------

max delay 9.000 9.000

clock pessimism 0.000 9.000
output delay -0.000 9.000
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required time 9.000
arrival time -7.793
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slack 1.207