UNIT 4 : DIGITAL SYSTEM DESIGN

GUIDELINES AND APPLICATIONS

1 Phase Locked Loop

Phase locked loop find it’s applications in Amplitude Modulation,Frequency Modula-
tion, Indirect frequency synthesizers etc. When two signals are compared based on
frequency following observations can be made
• If frequency of one signal is kept constant while that of other signal changed, the
phase difference between these two signal also change or will not be constant.
• If frequency of two signal is same then phase difference will be always constant.
It is not required that it will be always zero.
These two observations form the base of PLL concept. The block diagram of PLL is
shown in fig(1).

Input Voltage
Phase Low Pass Out Voltage
Vi Control
Comparator Filter Vo
Oscillator

Figure 1: PLL Block Diagram

Phase Comparator compare the input or reference signal with the output of voltage
control oscillator(VCO). The error signal which is DC voltage is applied to low pass
filter which removes frequency components. The filtered DC voltage is applied to
VCO who’s output signal frequency will be equal to input voltage. When input
frequency and VCO frequency matched the comparison will stop. This state of PLL
circuit where input signal frequency and VCO frequency matches is called as Phase
Locked State
PLL has two more modes 1. Free Running Mode 2. Capture Mode along with
Phase locked Mode. In Free Running Mode no input is applied PLL circuit is
running with VCO frequency. As input frequency is applied VCO start to change it’s
frequency till it become equal to input frequency. This mode is called as Capture
Mode.

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1.1 CMOS PLL CD 4046
CD4046 micro power PLL IC consist of linear VCO, two different phase comparator
having common input signal amplifier and common comparator input.

1.2 Features of CD4046

• Very low power consumption: 70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V

• Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k

• Low frequency drift: 0.04

• Choice of two phase comparators: Exclusive-OR network (I) Edge-controlled

memory network with phase-pulse output for lock indication (II)

• High VCO linearity: < 1% (typ.) at VDD = 10 V

• VCO inhibit control for ON-OFF keying and ultra-low standby power consump-
tion

• Source-follower output of VCO control input (Demod. output)

• Zener diode to assist supply regulation

• Standardized, symmetrical output characteristics 100

• 5-V, 10-V, and 15-V parametric ratings

Figure(2)shows pinout diagram of iC.

Figure 2: CD4046 Pinout

1.2.1 Functional Description

Figure(3) shows functional block diagram of CD4046.

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 Figure 3: CD4046 Block Diagram

1.2.2 Phase Comparator

Input or reference signal is applied at Signal In pin (14) while VCO output signal is
applied at Comparator In pin (3). The phase-comparator signal input (terminal 14)
can be direct coupled, provided the signal swing is within CMOS logic levels i.e logic
0 ≤ 30 (VDD – VSS ), logic 1 ≥ 70 (VDD – VSS ). For smaller input signal swings, the
signal must be capacitively coupled to the self-biasing amplifier at the signal input to
ensure an over driven digital signal into the phase comparators.
Phase comparator I is an exclusive-OR network that operates analogously to an
over driven balanced mixer. To maximize the lock range, the signal- and comparator-
input frequencies must have 50% duty cycle. With no signal or noise on the signal
input, this phase comparator has an average output voltage equal to VDD/2. The
LPF connected to the output of phase comparator I (pin no 2) supplies the averaged
voltage to the VCO input (pin no 9) and causes the VCO to oscillate at the centre
frequency (fo ). The characteristics of Phase comparator -I are

1. The range of frequencies over which the PLL can acquire lock (capture range)
is dependent on the LPF characteristics and can be made as large as the lock
range.

2. Phase comparator I enables a PLL system to remain in lock despite high

amounts of noise in the signal input.

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 Figure 4: Phase Comparator I & II

3. It can lock onto input frequencies that are close to harmonics of the VCO center
frequency
4. The phase angle between the signal and the comparator input varies between 0
degree and 180 degrees, and is 90 degrees at the centre frequency.
Figure(5)shows the typical, triangular, phase-to-output response characteristic of
phase comparator I. Typical waveforms for a CD4046B employing phase comparator
I in locked condition of fo is shown in Figure(5) Phase Comparator IIis an edge-

Figure 5: Typical Waveforms for the CD4046B Employing Phase Comparator I in

Locked Condition of fo
controlled digital memory network. It consists of four flip-flop stages, control gating,

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and a 3-state output circuit comprising p and n drivers having a common output node
(see Figure 3). When the p-MOS or n-MOS drivers are on, they pull the output up
to VDD or down to VSS, respectively. This type of phase comparator acts only on
the positive edges of the signal and comparator-input signals i.e. VCO output. The
duty cycles of the signal and comparator inputs are not important because positive
transitions control the PLL system that uses this type of comparator.
P-MOS Drver: If the signal-input frequency is higher than the comparator-input
frequency, the p-MOS output driver is maintained on continuously.
If the signal- and comparator-input frequencies are the same, but the signal input
leads the com5parator input in phase, the p-MOS output driver is maintained on for
time corresponding to the phase difference.
N-MOS Driver: If the signal-input frequency is lower than the comparator-input
frequency, the n-MOS output driver is maintained on continuously.
If the signal- and comparator-input frequencies are the same, but the signal input
lags the comparator input in phase, the n-MOS output driver is maintained on for a
time corresponding to the phase difference.
Subsequently, the capacitor voltage of the LPF connected to this type of phase com-
parator is adjusted until the signal and comparator input are equal in both phase and
frequency. At this stable operating point, both p-MOS and n-MOS output drivers
remain off, and the phase-comparator output becomes an open circuit and holds the
voltage on the capacitor of the LPF constant. Moreover, the signal at the phase-pulses
output is at a high level, and can be used for indicating a locked condition. Thus, for
phase comparator II, no phase difference exists between signal and comparator input
over the full VCO frequency range.
Moreover, the power dissipation due to the LPF is reduced when this type of phase
comparator is used because both the p-MOS and n-MOS output drivers are off for
most of the signal-input cycle. Note that the PLL lock range for this type of phase
comparator is equal to the capture range, independent of the LPF.

With no signal present at the signal input, the VCO is adjusted to its lowest
frequency for phase comparator II. Figure 6 shows typical waveforms for a CD4046B
employing phase comparator II in a locked condition. Figure(6)shows typical wave-
form for Phase Control-II.

1.2.3 Design Information

The external component must select as follows:
5K Ω ≤ 5c1 ≥ 100 µ F at VD ≥ 5V c1 5≥ 50 µ F at VD D ≥ 10V

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Figure 6: Typical Waveforms for the CD4046B Employing Phase Comparator II in
Locked Condition

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Figure 7: Design Information