Professional Documents
Culture Documents
40001414e PDF
40001414e PDF
LCD (Com/Seg/Total)
Program Memory
Data Sheet Index
MSSP (I2C/SPI)
CapSense (ch)
Data EEPROM
Flash (words)
Comparators
Data SRAM
(8/16-bit)
EUSART
Debug(1)
(bytes)
(bytes)
Timers
I/Os(2)
ECCP
CCP
XLP
Device
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1 1 48 RB0
RE0 2 47 RB1
RG0 3 46 RB2
RG1 4 45 RB3
RG2 5 44 RB4
RG3 6 43 RB5
VPP/MCLR/RG5 7 42 RB6
PIC16(L)F1946/47
RG4 8 41 VSS
VSS 9 40 RA6
VDD 10 39 RA7
RF7 11 38 VDD
RF6 12 37 RB7
RF5 13 36 RC5
RF4 14 35 RC4
RF3 15 34 RC3
RF2 16 33 RC2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0
RA3
RA2
RA5
RC1
RC0
RC6
RC7
AVDD
RA1
RA0
VDD
RA4
AVSS
VSS
Note: AVDD and AVSS are dedicated power connection pins for the on-board analog circuits of the PIC®
microcontroller. The separate power pins help eliminate digital switching noise interference with the analog
circuitry inside the device, especially on larger devices with more I/O pins and larger switching currents on
the VDD/VSS pins. Customers typically connect these to the appropriate VDD or VSS connections on the
PCB, unless there is a lot of noise on the external power rails. In those situations, they will add additional
noise filtering components (like capacitors) on the AVDD/AVSS pins to help ensure good solid supply to the
analog modules inside the device.
Comparator
Cap Sense
Reference
SR Latch
Interrupt
USART
ANSEL
Pull-up
Timers
MSSP
Basic
CCP
LCD
A/D
I/O
Comparator
Cap Sense
Reference
SR Latch
Interrupt
USART
ANSEL
Pull-up
Timers
MSSP
Basic
CCP
LCD
A/D
I/O
VDD 10 — — — — — — — — — — — — — VDD
26
38
57
VSS 9 — — — — — — — — — — — — — VSS
25
41
56
AVDD 19 — — — — — — — — — — — — — AVDD
AVSS 20 — — — — — — — — — — — — — AVSS
Note 1: Pin functions can be moved using the APFCON register(s). Default location.
2: Pin function can be moved using the APFCON register. Alternate location.
3: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
4: See Section 8.0 “Low Dropout (LDO) Voltage Regulator”.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16(L)F1946
PIC16(L)F1947
Peripheral
ADC ● ●
Capacitive Sensing (CPS) Module ● ●
Data EEPROM ● ●
Digital-to-Analog Converter (DAC) ● ●
Fixed Voltage Reference (FVR) ● ●
LCD ● ●
SR Latch ● ●
Capture/Compare/PWM Modules
ECCP1 ● ●
ECCP2 ● ●
ECCP3 ● ●
CCP4 ● ●
CCP5 ● ●
Comparators
C1 ● ●
C2 ● ●
C3 ● ●
EUSARTS
EUSART1 ● ●
EUSART2 ● ●
Master Synchronous Serial Ports
MSSP1 ● ●
MSSP2 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●
Timer4 ● ●
Timer6 ● ●
Program
Flash Memory
RAM EEPROM
PORTA
OSC2/CLKOUT Timing
Generation
Figure 2-1
PORTC
MCLR
PORTD
PORTE
PORTF
SR ADC PORTG
Latch 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators
15
Configuration
Configuration 8
15 Data Bus
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg
Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
PC<14:0> PC<14:0>
CALL, CALLW 15
RETURN, RETLW
CALL, CALLW 15
RETURN, RETLW
Interrupt, RETFIE Interrupt, RETFIE
Stack Level 0 Stack Level 0
Stack Level 1 Stack Level 1
Page 7
3FFFh
Rollover to Page 0 4000h
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
CALL constants
;… THE CONSTANT IS IN W
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F1946/1947
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch PORTF 30Ch TRISF 38Ch LATF
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh — 20Dh WPUB 28Dh PORTG 30Dh TRISG 38Dh LATG
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh — 20Eh — 28Eh — 30Eh — 38Eh —
00Fh PORTD 08Fh TRISD 10Fh LATD 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PORTE 090h TRISE 110h LATE 190h ANSELE 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h —
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h —
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h —
014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h PWM3CON 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSP1CON1 295h CCP1AS 315h CCP3AS 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L 318h CCPR4L 398h —
019h T1GCON 099h OSCCON 119h DACCON1 199h RC1REG 219h SSP2BUF 299h CCPR2H 319h CCPR4H 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TX1REG 21Ah SSP2ADD 29Ah CCP2CON 31Ah CCP4CON 39Ah —
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SP1BRGL 21Bh SSP2MSK 29Bh PWM2CON 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SP1BRGH 21Ch SSP2STAT 29Ch CCP2AS 31Ch CCPR5L 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RC1STA 21Dh SSP2CON1 29Dh PSTR2CON 31Dh CCPR5H 39Dh —
01Eh CPSCON0 09Eh ADCON1 11Eh CM3CON0 19Eh TX1STA 21Eh SSP2CON2 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —
2010-2016 Microchip Technology Inc.
01Fh CPSCON1 09Fh — 11Fh CM3CON1 19Fh BAUD1CON 21Fh SSP2CON3 29Fh CCPTMRS1 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h General Purpose 3A0h
General General General General General Register General
Purpose Purpose Purpose Purpose Purpose 32Fh 16 Bytes Purpose
General Register Register Register Register Register 330h General Purpose Register
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes(1)
Register
06Fh
Register
0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 64 Bytes(1) 3EFh
96 Bytes
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Not available on PIC16F1946.
TABLE 3-5: PIC16(L)F1946/47 MEMORY MAP, BANKS 8-15
DS40001414E-page 25
PIC16(L)F1946/1947
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0
401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1
402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL
403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS
404h FSR0L 484h FSR0L 504h FSR0L 584h FSR0L 604h FSR0L 684h FSR0L 704h FSR0L 784h FSR0L
405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H
406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L
407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H
408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR
409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG
40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH
40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON
40Ch ANSELF 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —
40Dh ANSELG 48Dh WPUG 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —
40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —
40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —
410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —
411h — 491h RC2REG 511h — 591h — 611h — 691h — 711h — 791h
412h — 492h TX2REG 512h — 592h — 612h — 692h — 712h — 792h
413h — 493h SP2BRGL 513h — 593h — 613h — 693h — 713h — 793h
414h — 494h SP2BRGH 514h — 594h — 614h — 694h — 714h — 794h
415h TMR4 495h RC2STA 515h — 595h — 615h — 695h — 715h — 795h
416h PR4 496h TX2STA 516h — 596h — 616h — 696h — 716h — 796h
417h T4CON 497h BAUD2CON 517h — 597h — 617h — 697h — 717h — 797h
418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h
419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h
41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah
41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh See Table 3-8
41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch
41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh
41Eh T6CON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh
2010-2016 Microchip Technology Inc.
PIC16(L)F1946/1947
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch — B0Ch — B8Ch —
80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh —
80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh — B0Eh — B8Eh —
80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh — B0Fh — B8Fh —
810h — 890h — 910h — 990h — A10h — A90h — B10h — B90h —
811h — 891h — 911h — 991h — A11h — A91h — B11h — B91h —
812h — 892h — 912h — 992h — A12h — A92h — B12h — B92h —
813h — 893h — 913h — 993h — A13h — A93h — B13h — B93h —
814h — 894h — 914h — 994h — A14h — A94h — B14h — B94h —
815h — 895h — 915h — 995h — A15h — A95h — B15h — B95h —
816h — 896h — 916h — 996h — A16h — A96h — B16h — B96h —
817h — 897h — 917h — 997h — A17h — A97h — B17h — B97h —
818h — 898h — 918h — 998h — A18h — A98h — B18h — B98h —
819h — 899h — 919h — 999h — A19h — A99h — B19h — B99h —
81Ah — 89Ah — 91Ah — 99Ah — A1Ah — A9Ah — B1Ah — B9Ah —
81Bh — 89Bh — 91Bh — 99Bh — A1Bh — A9Bh — B1Bh — B9Bh —
81Ch — 89Ch — 91Ch — 99Ch — A1Ch — A9Ch — B1Ch — B9Ch —
81Dh — 89Dh — 91Dh — 99Dh — A1Dh — A9Dh — B1Dh — B9Dh —
81Eh — 89Eh — 91Eh — 99Eh — A1Eh — A9Eh — B1Eh — B9Eh —
2010-2016 Microchip Technology Inc.
PIC16(L)F1946/1947
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0
C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1
C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL
C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS
C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L
C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H
C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L
C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H
C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR
C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG
C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH
C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON
C0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0Ch — F8Ch
C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh — F8Dh
C0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh — F8Eh
C0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh — F8Fh
C10h — C90h — D10h — D90h — E10h — E90h — F10h — F90h
C11h — C91h — D11h — D91h — E11h — E91h — F11h — F91h
C12h — C92h — D12h — D92h — E12h — E92h — F12h — F92h
C13h — C93h — D13h — D93h — E13h — E93h — F13h — F93h
C14h — C94h — D14h — D94h — E14h — E94h — F14h — F94h
C15h — C95h — D15h — D95h — E15h — E95h — F15h — F95h
C16h — C96h — D16h — D96h — E16h — E96h — F16h — F96h
C17h — C97h — D17h — D97h — E17h — E97h — F17h — F97h
C18h — C98h — D18h — D98h — E18h — E98h — F18h — F98h See Table 3-9
C19h — C99h — D19h — D99h — E19h — E99h — F19h — F99h
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah — F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh — F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch — F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh — F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh — F9Eh
2010-2016 Microchip Technology Inc.
Bank 0
000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
001h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
002h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
(2)
003h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
004h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
005h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
006h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
(2)
007h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
008h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000
00Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
00Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
010h PORTE PORTE Data Latch when written: PORTE pins when read xxxx xxxx xxxx uuuu
011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF C3IF CCP2IF 0000 0000 0000 0000
013h PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — -000 0-0- -000 0-0-
014h PIR4 — — RC2IF TX2IF — — BCL2IF SSP2IF --00 --00 --00 --00
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Dh — Unimplemented — —
01Eh CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000
01Fh CPSCON1 — — — CPSCH<4:0> ---0 0000 ---0 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 1
080h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
081h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
082h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
083h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
084h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
085h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
086h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
087h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
08Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
08Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh TRISD PORTD Data Direction Register 1111 1111 1111 1111
090h TRISE PORTE Data Direction Register 1111 1111 1111 1111
091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE 0000 0000 0000 0000
093h PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — -000 0-0- -000 0-0-
094h PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE --00 --00 --00 --00
095h OPTION_REG WPUEN INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0- qqqq qq0-
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 2
100h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
101h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
102h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
103h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
104h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
105h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
106h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
107h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
10Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
10Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH<1:0> 0000 --00 0000 --00
113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH<1:0> 0000 --00 0000 --00
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0 000- 00-0
11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch — Unimplemented — —
11Dh APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 0000 0000 0000 0000
11Eh CM3CON0 C3ON C3OUT C3OE C3POL — C3SP C3HYS C3SYNC 0000 -100 0000 -100
11Fh CM3CON1 C3INTP C3INTN C3PCH1 C3PCH0 — — C3NCH<1:0> 0000 --00 0000 --00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 3
180h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
181h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
184h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
185h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
186h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
187h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
18Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
18Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
18Ch ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111
18Dh — Unimplemented — —
18Eh — Unimplemented — —
18Fh — Unimplemented — —
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
(3)
192h EEADRH — EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
197h — Unimplemented — —
198h — Unimplemented — —
199h RC1REG USART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRGL EUSART1 Baud Rate Generator, Low Byte 0000 0000 0000 0000
19Ch SP1BRGH EUSART1 Baud Rate Generator, High Byte 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 4
200h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
201h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
202h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
203h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
204h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
205h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
206h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
207h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
20Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
20Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
20Ch — Unimplemented — —
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh — Unimplemented — —
20Fh — Unimplemented — —
210h — Unimplemented — —
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h — Unimplemented — —
219h SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
21Ch SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
21Dh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
21Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
21Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 5
280h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
281h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
282h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
283h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
284h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
285h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
286h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
287h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
28Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
28Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
28Ch PORTF PORTF Data Latch when written: PORTF pins when read xxxx xxxx uuuu uuuu
28Dh PORTG — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu
28Eh — Unimplemented — —
28Fh — Unimplemented — —
290h — Unimplemented — —
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000
296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
297h — Unimplemented — —
29Ch CCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000 0000 0000
29Dh PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh CCPTMRS1 — — — — — — C5TSEL<1:0> ---- --00 ---- --00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 6
300h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
301h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
302h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
303h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
304h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
305h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
306h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
307h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
30Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
30Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
30Ch TRISF PORTF Data Direction Register 1111 1111 1111 1111
30Dh TRISG — — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111
30Eh — Unimplemented — —
30Fh — Unimplemented — —
310h — Unimplemented — —
315h CCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000 0000 0000
316h PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001 ---0 0001
317h — Unimplemented — —
31Bh — Unimplemented — —
31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 7
380h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
381h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
382h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
383h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
384h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
385h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
386h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
387h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
38Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
38Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
38Dh LATG — — LATG5 LATG4 LATG3 LATG2 LATG1 LATG0 --xx xxxx --uu uuuu
38Eh — Unimplemented — —
38Fh — Unimplemented — —
390h — Unimplemented — —
391h — Unimplemented — —
392h — Unimplemented — —
393h — Unimplemented — —
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000
397h — Unimplemented — —
398h — Unimplemented — —
399h — Unimplemented — —
39Ah — Unimplemented — —
39Bh — Unimplemented — —
39Ch — Unimplemented — —
39Dh — Unimplemented — —
39Eh — Unimplemented — —
39Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 8
400h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
401h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
402h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
403h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
404h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
405h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
406h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
407h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
40Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
40Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
40Ch ANSELF ANSELF7 ANSELF6 ANSELF5 ANSELF4 ANSELF3 ANSELF2 ANSELF1 ANSELF0 1111 1111 1111 1111
40Dh ANSELG — — — ANSELG4 ANSELG3 ANSELG2 ANSELG1 — ---1 111- ---1 111-
40Eh — Unimplemented — —
40Fh — Unimplemented — —
410h — Unimplemented — —
411h — Unimplemented — —
412h — Unimplemented — —
413h — Unimplemented — —
414h — Unimplemented — —
418h — Unimplemented — —
419h — Unimplemented — —
41Ah — Unimplemented — —
41Bh — Unimplemented — —
41Ch TMR6 Timer 6 Module Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 9
480h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
481h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
482h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
483h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
404h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
485h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
486h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
487h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
48Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
48Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
48Ch — Unimplemented — —
48Eh — Unimplemented — —
48Fh — Unimplemented — —
490h — Unimplemented — —
491h RC2REG USART Receive Data Register 0000 0000 0000 0000
492h TX2REG USART Transmit Data Register 0000 0000 0000 0000
493h SP2BRGL EUSART2 Baud Rate Generator, Low Byte 0000 0000 0000 0000
494h SP2BRGH EUSART2 Baud Rate Generator, High Byte 0000 0000 0000 0000
495h RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
496h TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
497h BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
498h — Unimplemented — —
499h — Unimplemented — —
49Ah — Unimplemented — —
49Bh — Unimplemented — —
49Ch — Unimplemented — —
49Dh — Unimplemented — —
49Eh — Unimplemented — —
49Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Banks 10-14
x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
x80h(2) (not a physical register)
x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
x81h(2) (not a physical register)
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(2)
x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h(2)
x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h(2)
x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h(2)
x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1),(2)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
x8Bh(2)
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 15
780h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
781h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
782h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
783h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
784h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
785h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
786h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
787h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
78Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
78Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
78Ch — Unimplemented — —
78Dh — Unimplemented — —
78Eh — Unimplemented — —
78Fh — Unimplemented — —
790h — Unimplemented — —
791h LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 000- 0011 000- 0011
792h LCDPS WFT BIASMD LCDA WA LP<3:0> 0000 0000 0000 0000
793h LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 000- 000- 000- 000-
796h — Unimplemented — —
797h — Unimplemented — —
79Eh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
79Fh — Unimplemented — —
7A0h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7A1h LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7A2h LCDDATA2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7A3h LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
7A4h LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
7A5h LCDDATA5 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 15 (Continued)
7A6h LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
7A7h LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
7A8h LCDDATA8 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
7A9h LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
7AAh LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
7ABh LCDDATA11 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
7ACh LCDDATA12 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7ADh LCDDATA13 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
7AEh LCDDATA14 — — SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 --xx xxxx --uu uuuu
COM0 COM0 COM0 COM0 COM0 COM0
7AFh LCDDATA15 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
7B0h LCDDATA16 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
7B1h LCDDATA17 — — SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 --xx xxxx --uu uuuu
COM1 COM1 COM1 COM1 COM1 COM1
7B2h LCDDATA18 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
7B3h LCDDATA19 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
7B4h LCDDATA20 — — SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 --xx xxxx --uu uuuu
COM2 COM2 COM2 COM2 COM2 COM2
7B5h LCDDATA21 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
7B6h LCDDATA22 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
7B7h LCDDATA23 — — SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 --xx xxxx --uu uuuu
COM3 COM3 COM3 COM3 COM3 COM3
7B8h — Unimplemented — —
—
7EFh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Banks 16-30
x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
x80h(2) (not a physical register)
x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
x81h(2) (not a physical register)
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(2)
x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h(2)
x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h(2)
x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h(2)
x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1),(2)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
x8Bh(2)
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
Bank 31
F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
F83h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
(2)
F84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
F85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
F86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
F87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
F8Ah(1),(2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
F8Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
F8Ch — Unimplemented — —
—
FE3h
FE5h WREG_ Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FE6h BSR_ Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
SHAD
FECh — Unimplemented — —
FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Unimplemented, read as ‘1’.
14 PCH PCL 0
PC BRA
15
PC + OPCODE <8:0>
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See Vbor parameter for specific trip point voltages.
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See Vbor parameter for specific trip point voltages.
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 4.6 “Device ID and Revision ID” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC16F193X/LF193X/PIC16F194X/LF190X Memory
Programming Specification” (DS41397).
R R R R R R R R
DEV<2:0> REV<4:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared -n = Value when blank or after Bulk Erase
DEVICEID<13:0> Values
Device
DEV<8:0> REV<4:0>
PIC16F1946 10 0011 001 x xxxx
PIC16F1947 10 0011 010 x xxxx
PIC16LF1946 10 0011 011 x xxxx
PIC16LF1947 10 0011 100 x xxxx
External
Oscillator LP, XT, HS, RC, EC
OSC2
Sleep
4 x PLL Sleep
OSC1
Oscillator Timer1 FOSC<2:0> = 100 T1OSC CPU and
MUX
T1OSO Peripherals
T1OSCEN
Enable
T1OSI Oscillator IRCF<3:0>
Internal Oscillator
16 MHz
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz
Clock
Postscaler
1 MHz
HFPLL Control
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz FOSC<2:0> SCS<1:0>
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz Clock Source Option
31 kHz for other modules
31 kHz
Source
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Applications Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
• AN826, Crystal Oscillator Basics and increment and program execution is suspended. The
Crystal Selection for rfPIC® and PIC® OST ensures that the oscillator circuit, using a quartz
Devices (DS00826) crystal resonator or ceramic resonator, has started and
• AN849, Basic PICmicro® Oscillator is providing a stable system clock to the oscillator
Design (DS00849) module.
• AN943, Practical PICmicro® Oscillator In order to minimize latency between external oscillator
Analysis and Design (DS00943) start-up and code execution, the Two-Speed Clock
• AN949, Making Your Oscillator Work Start-up mode can be selected (see Section 5.4
(DS00949) “Two-Speed Clock Start-up Mode”).
5.2.1.4 4x PLL
The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 30.0
“Electrical Specifications”.
The 4x PLL may be enabled for use by one of two
methods:
1. Program the PLLEN bit in Configuration Words
to a ‘1’.
2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Words is
programmed to a ‘1’, then the value of SPLLEN
is ignored.
LFINTOSC
System Clock
LFINTOSC
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
2-
Oscillator Delay(1) cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock
Note: See Table 5-1, Oscillator Switching Delays, for more information.
• Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN
bits in Configuration Words control bit in the T1CON register. See Section 21.0
“Timer1 Module with Gate Control” for more
• Timer1 32 kHz crystal oscillator
information about the Timer1 peripheral.
• Internal Oscillator Block (INTOSC)
5.3.4 TIMER1 OSCILLATOR READY
5.3.1 SYSTEM CLOCK SELECT (SCS)
(T1OSCR) BIT
BITS
The user must ensure that the Timer1 oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the CPU and peripherals.
the OSCSTAT register indicates whether the Timer1
• When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is
the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1
the FOSC<2:0> bits in the Configuration Words. oscillator.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator. 5.3.5 CLOCK SWITCHING BEFORE
• When the SCS bits of the OSCCON register = 1x, SLEEP
the system clock source is chosen by the internal When clock switching from an old clock to a new clock
oscillator frequency selected by the IRCF<3:0> is requested just prior to entering Sleep mode, it is
bits of the OSCCON register. After a Reset, the necessary to confirm that the switch is complete before
SCS bits of the OSCCON register are always the SLEEP instruction is executed. Failure to do so may
cleared. result in an incomplete switch and consequential loss
Note: Any automatic clock switch, which may of the system clock altogether. Clock switching is
occur from Two-Speed Start-up or confirmed by monitoring the clock Status bits in the
Fail-Safe Clock Monitor, does not update OSCSTAT register. Switch confirmation can be
the SCS bits of the OSCCON register. The accomplished by sensing that the Ready bit for the new
user can monitor the OSTS bit of the clock is set or the Ready bit for the old clock is cleared.
OSCSTAT register to determine the current For example, when switching between the internal
system clock source. oscillator with the PLL and the internal oscillator without
the PLL, monitor the PLLR bit. When PLLR is set, the
When switching between clock sources, a delay is switch to 32 MHz operation is complete. Conversely,
required to allow the new clock to stabilize. These when PLLR is cleared the switch from 32 MHz
oscillator delays are shown in Table 5-1. operation to the selected internal clock is complete.
INTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Stack Underflow
Stack Overlfow
MCLRE
VPP/MCLR
Sleep
WDT
Time-out Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
R
Brown-out Power-up
Reset Timer
LFINTOSC
PWRTE
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
0 0 1 1 0 x 1 1 Power-on Reset
0 0 1 1 u 0 1 1 Brown-out Reset
u u u u u u 0 u WDT Reset
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF Interrupt
(TMR1IF) PIR1<0> IOCIE to CPU
PEIE
PIRn<7>
PIEn<7> GIE
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register
have been cleared by software.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
WDTE<1:0> = 01
SWDTEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
MOVLW 0AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable Interrupts
BCF EECON1, WREN ;Disable writes
BTFSC EECON1, WR ;Wait for write to complete
GOTO $-2 ;Done
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4)
RD bit
EEDATH
EEDATL
Register
FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7 5 0 7 0
EEDATH EEDATA
6 8
14 14 14 14
Program Memory
MOVLW 0AAh ;
Required
START_WRITE
BCF EECON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 0AAh ;
Required
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Some ports may have one or more of the following Write LATx
Write PORTx
additional registers. These registers are: CK VDD
• ANSELx (analog select) Data Register
• WPUx (weak pull-up)
Data Bus
In general, when a peripheral is enabled on a port pin,
I/O pin
that pin cannot be used as a general purpose output. Read PORTx
However, the pin can still be read.
To peripherals
VSS
ANSELx
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
EXAMPLE 12-1: INITIALIZING PORTA
PORTB
PORTA
PORTG
PORTC
PORTD
PORTE
PORTF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 123
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 131
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 330
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 330
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 330
LCDSE4 SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 330
LCDSE5 — — SE45 SE44 SE43 SE42 SE41 SE40 330
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 131
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 298
RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 298
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 282
SSP2STAT SMP CKE D/A P S R/W UA BF 281
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 297
TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 297
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 131
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 123
CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 227
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 134
LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 326
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 330
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 134
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 134
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Applies to ECCP modules only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of
actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSE<7:0>: Analog Select between Analog or Digital Function on Pins RE<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 123
ANSELE — — — — — ANSE2 ANSE1 ANSE0 138
CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 227
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 138
LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 326
LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 328
LCDSE2 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 330
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 137
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 137
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Applies to ECCP modules only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSF<7:0>: Analog Select between Analog or Digital Function on Pins RF<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual
I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
IOCBNx D Q4Q1
Q
CK edge
detect
R
RBx
CK write IOCBFx CK
IOCIE
R
Q2
from all other
IOCBFx individual IOC interrupt
pin detectors to CPU core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
• ADC input channel The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
• ADC positive reference
for the reference supplied to the ADC module.
• Comparator positive input Reference Section 16.0 “Analog-to-Digital
• Digital-to-Analog Converter (DAC) Converter (ADC) Module” for additional information.
• Capacitive Sensing (CPS) module The CDAFVR<1:0> bits of the FVRCON register are
• LCD bias generator used to enable and configure the gain amplifier settings
The FVR can be enabled by setting the FVREN bit of for the reference supplied to the Comparators, DAC
the FVRCON register. and CPS module. Reference Section 17.0 “Digital-to-
Analog Converter (DAC) Module”, Section 18.0
“Comparator Module” and Section 26.0 “Capacitive
Sensing (CPS) Module” for additional information.
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC, CPS)
FVR VREF
1.024V Fixed (To LCD Bias Generator)
Reference
+
FVREN
_ FVRRDY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 151
Legend: Shaded cells are not used with the Fixed Voltage Reference.
VREF- ADNREF = 1
ADNREF = 0
VSS
VDD
ADPREF = 00
ADPREF = 11
VREF+ ADPREF = 10
AN0 00000
AN1 00001
VREF-/AN2 00010
VREF+/AN3 00011
AN4 00100
AN5 00101
AN6 00110
AN7 00111 Ref+ Ref-
CHS<4:0>
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
Fosc/4 100 125 ns (2)
200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s (3)
32.0 s(3)
Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s (3)
16.0 s (3)
64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 15.0 “Temperature Indicator Module” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
T C = – C HOLD R IC + R SS + R S ln(1/2047)
–4
= – 10pF 1k + 7k + 10k ln 4.88 10
= 1.37µs
Therefore:
T A CQ = 2µs + 1.37µs + 50°C- 25°C 0.05 µs/°C
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
VSS/VREF-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
VREF- Zero-Scale
Transition Full-Scale
Transition VREF+
IF DACEN = 1
DACR 4:0
VOUT = VSOURCE+ – VSOURCE- ----------------------------- + VSOURCE-
5
2
V OUT = V SOURCE +
V OUT = V SOURCE –
FVR BUFFER2
VSOURCE+
VDD DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
DACEN
DACLPS R
32-to-1 MUX
32 DAC Output (To Comparator, CPS and
Steps ADC Modules)
R
DACOUT
R
DACOE
DACNSS
VREF- VSOURCE-
VSS
PIC® MCU
DAC
R
Module
+
Voltage DACOUT Buffered DAC Output
–
Reference
Output
Impedance
Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
VSOURCE+ VSOURCE+
R R
DACR<4:0> = 11111
R R
DACEN = 0 DACEN = 0
DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder
(see Figure 17-1) (see Figure 17-1)
R R
DACR<4:0> = 00000
VSOURCE- VSOURCE-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
C2
C3
Device
PIC16(L)F1946 ● ● ●
PIC16(L)F1947 ● ● ●
CxNCH<1:0>
CxON(1)
2 Interrupt CxINTP
det
CXIN0- 0 Set CxIF
CXIN1- 1
MUX Interrupt CxINTN
CXIN2- 2 (2) det
CXPOL
CXIN3- 3 CxVN
-
to CMXCON0 (CXOUT)
D Q
Cx(3) and CM2CON1 (MCXOUT)
+
CxVP
Q1 EN
CXIN+ 0
MUX CxHYS
DAC Output 1 (2) CxSP
async_CxOUT
to PWM
FVR Buffer2 2
3
CXSYNC
VSS CxON CXOE
TRIS bit
CXOUT
CXPCH<1:0> 0
2
D Q 1
(from Timer1)
T1CLK sync_CxOUT To Timer1 or
SR Latch
Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.
3: Output of comparator can be frozen during debugging.
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
SRLEN
SRPS Pulse SRQEN
Gen(2)
SRI
SRSPE S Q
SRCLK
SRQ
SRSCKE
sync_C2OUT(3)
SRSC2E
sync_C1OUT(3)
SR
SRSC1E
Latch(1)
SRPR Pulse
Gen(2)
SRI
SRRPE R Q
SRCLK SRNQ
SRRCKE SRLEN
sync_C2OUT(3) SRNQEN
SRRC2E
sync_C1OUT(3)
SRRC1E
111 512 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz
110 256 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz
101 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz
100 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz
011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz
010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz
001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz
000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
FOSC/4
Data Bus
0
8
T0CKI 1
0 Sync
1 2 TCY TMR0
0
From CPSCLK
1 TMR0SE Set Flag bit TMR0IF
TMR0CS 8-bit on Overflow
Prescaler PSA
T0XCS
Overflow to Timer1
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
T1GSS<1:0>
T1G 00 T1GSPM
TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used:
SELECTIONS • Asynchronous event on the T1G pin to Timer1
gate
Timer1
TMR1ON TMR1GE
Operation • C1 or C2 comparator input to Timer1 gate
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Prescaler Reset
FOSC/4 TMRx TMRx Output
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator Sets Flag bit TMRxIF
EQ 1:1 to 1:16
TxCKPS<1:0>
PRx 4
TxOUTPS<3:0>
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSPx modules operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 24.0
TxCKPS<1:0> of the TxCON register. The value of “Master Synchronous Serial Port (MSSP1 and
TMRx is compared to that of the Period register, PRx, on MSSP2) Module”.
each clock cycle. When the two values match, the
comparator generates a match signal as the timer 22.4 Timer2/4/6 Operation During Sleep
output. This signal also resets the value of TMRx to 00h
The Timer2/4/6 timers cannot be operated while the
on the next cycle and drives the output
processor is in Sleep mode. The contents of the TMRx
counter/postscaler (see Section 22.2 “Timer2/4/6
and PRx registers will remain unchanged while the
Interrupt”).
processor is in Sleep mode.
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMRx is not cleared when TxCON is
written.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TMR1H TMR1L
CCPxM<3:0>
System Clock (FOSC)
• PRx registers Table shows the pin assignments for various Enhanced
PWM modes.
• TxCON registers
• CCPRxL registers Note 1: The corresponding TRIS bit must be
• CCPxCON registers cleared to enable the PWM output on the
CCPx pin.
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCPxCON register will
Dead-band Delay and PWM Steering modes: relinquish control of the CCPx pin.
FIGURE 23-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0> PxM<1:0> CCPxM<3:0>
Duty Cycle Registers
2 4
CCPRxL
CCPx/PxA CCPx/PxA
TRISx
CCPRxH (Slave)
PxB PxB
Output TRISx
Comparator R Q
Controller
PxC PxC
TMRx (1)
S TRISx
PxD PxD
Comparator
Clear Timer, TRISx
toggle PWM pin and
latch duty cycle
PRx PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD
(1) (1) (1)
Single 00 Yes Yes Yes Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: PWM Steering enables outputs in Single mode.
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)
Pulse PRx+1
PxM<1:0> Signal 0
Width
Period
PxA Modulated
Delay Delay
10 (Half-Bridge) PxB Modulated
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)
FET
Driver +
PxA
-
Load
FET
Driver
+
PxB
-
V+
FET FET
Driver Driver
PxA
Load
FET FET
Driver Driver
PxB
FET QA QC FET
Driver Driver
PxA
Load
PxB
FET FET
Driver Driver
PxC
QB QD
V-
PxD
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
PxA
PxB
PW
PxC
PxD PW
TON
External Switch C
TOFF
External Switch D
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Shutdown Resumes
Event Occurs Event Clears CCPxASE
Cleared by
Firmware
23.4.4 AUTO-RESTART MODE If auto-restart is enabled, the CCPxASE bit will remain
set as long as the auto-shutdown condition is active.
The Enhanced PWM can be configured to
When the auto-shutdown condition is removed, the
automatically restart the PWM signal once the
CCPxASE bit will be cleared via hardware and normal
auto-shutdown condition has been removed.
operation will resume.
Auto-restart is enabled by setting the PxRSEN bit in the
PWMxCON register.
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Resumes
Event Occurs
Shutdown CCPxASE
Event Clears Cleared by
Hardware
FET
Driver +
PxA V
-
Load
FET
Driver
+
PxB V
-
V-
PORT Data
0
TRIS
STRxB
PORT Data 0
TRIS
STRxC
PxC pin
CCPxM1 1
PORT Data 0
TRIS
STRxD
PORT Data 0
TRIS
PWM Period
PWM
STRx
P1n = PWM
PWM
STRx
P1n = PWM
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
0011 = Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets ECCPx module)
CCP4/CCP5 only:
11xx = PWM mode
ECCP1/ECCP2/ECCP3 only:
1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low
1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high
1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low
1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
Data Bus
Read Write
SSPxBUF Reg
SDIx
SSPxSR Reg
SDOx bit 0 Shift
Clock
Edge
Select
SSPM<3:0>
4
( TMR22Output )
SCKx
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSPxADD)
Internal
data bus <SSPM 3:0>
Read Write
Internal
Data Bus
Read Write
Shift
Clock
SSPxSR Reg
SDAx MSb LSb
SSPxMSK Reg
SSPxADD Reg
SCKx SCKx
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
General I/O
General I/O SCKx
SDIx SPI Slave
SDOx #2
SSx
SCKx
SDIx SPI Slave
SDOx #3
SSx
Slave Select
General I/O SSx
Processor 1 (optional) Processor 2
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
SCK SCK
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
SCK
SDIx SPI Slave
SDOx #2
SSx
SCK
SDIx SPI Slave
SDOx #3
SSx
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDIx bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
SDAx
SCLx
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
DS40001414E-page 250
Bus Master sends
Stop condition
From Slave to Master
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCLx
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV
SSPxIF
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
DS40001414E-page 251
PIC16(L)F1946/47
Master Releases SDAx Master sends
to slave for ACK sequence Stop condition
FIGURE 24-16:
DS40001414E-page 252
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCLx, after ACK after not ACK
PIC16(L)F1946/47
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCLx is released
and SCLx is stretched hardware on 8th falling
edge of SCLx
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Stop condition
Master releases
R/W = 0 SDAx to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
DS40001414E-page 253
PIC16(L)F1946/47
PIC16(L)F1946/47
24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 24-17 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and
and the SCLx pin is held low (see Section 24.5.6 SCLx.
“Clock Stretching” for more details). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
clock, the master will be unable to assert another clock rupt on Start detect is enabled.
pulse until the slave is done, preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPxSR register. Then, SSPxIF.
the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by the user.
of the SSPxCON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCLx input. This
SSPxBUF, clearing BF.
ensures that the SDAx signal is valid during the SCLx
high time. 7. R/W is set so CKP is automatically cleared after
the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCLx input pulse. This ACK
SSPxBUF.
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the
transfer is complete. In this case, when the not ACK is master to clock the data out of the slave.
latched by the slave, the slave goes Idle and waits for 10. SSPxIF is set after the ACK response from the
another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared.
the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSPx interrupt is generated for each data transfer Note 1: If the master ACKs, the clock will be
byte. The SSPxIF bit must be cleared by software and stretched.
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCLx (9th) rather than on
the falling.
24.5.3.1 Slave Mode Bus Collision
13. Steps 9-13 are repeated for each transmitted
A slave receives a Read request and begins shifting byte.
data out on the SDAx line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set.
the BCLxIF bit of the PIRx register is set. Once a bus
15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLxIF bit 16. The slave is no longer addressed.
to handle a slave bus collision.
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
CKP
When R/W is set CKP is not
SCLx is always held for not
held low after 9th SCLx Set by software ACK
falling edge
ACKSTAT
Indicates an address
has been received
DS40001414E-page 255
PIC16(L)F1946/47
PIC16(L)F1946/47
24.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF inter-
rupt is set.
Figure 24-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCLx line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads the ACKTIM bit of the
SSPxCON3 register, and R/W and D/A of the
SSPxSTAT register to determine the source of
the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCLx.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCLx
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
R/W
D/A
DS40001414E-page 257
PIC16(L)F1946/47
PIC16(L)F1946/47
24.5.4 SLAVE MODE 10-BIT ADDRESS 24.5.5 10-BIT ADDRESSING WITH ADDRESS
RECEPTION OR DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSPx module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 24-19 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCLx line is held low are the
same. Figure 24-20 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 24-21 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCLx.
8. Master sends matching low address byte to the
Slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDAx
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCLx is held low and releases SCLx
CKP
DS40001414E-page 259
PIC16(L)F1946/47
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 24-21:
DS40001414E-page 260
SCLx S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
SSPxIF
Set by hardware Cleared by software Cleared by software
PIC16(L)F1946/47
BF
UA
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SSPxIF
BF
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001414E-page 261
PIC16(L)F1946/47
PIC16(L)F1946/47
24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCLx line low effectively, pausing clock is always stretched. This is the only time the
communication. The slave may stretch the clock to SCLx is stretched without CKP being cleared. SCLx is
allow more time to handle data or prepare a response released immediately after a write to SSPxADD.
for the master device. A master device is not
Note: Previous versions of the module did not
concerned with stretching as anytime it is active on the
stretch the clock if the second address byte
bus and not transferring data it is stretching. Any
did not match.
stretching done by a slave is invisible to the master
software and by the hardware that generates SCLx.
24.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is When AHEN bit of SSPxCON3 is set, CKP is cleared
cleared, the module will wait for the SCLx line to go by hardware after the eighth falling edge of SCLx for a
low and then hold it. Setting CKP will release SCLx received matching address byte. When the DHEN bit
and allow more communication. of SSPxCON3 is set, CKP is cleared after the eighth
falling edge of SCLx for received data.
24.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCLx allows
Following an ACK, if the R/W bit of SSPxSTAT is set, the slave to look at the received address or data and
the slave hardware will clear CKP. This allows the decide if it wants to ACK the received data.
slave time to update SSPxBUF with data to transfer to
24.5.7 CLOCK SYNCHRONIZATION AND
the master. If the SEN bit of SSPxCON2 is set, the
THE CKP BIT
slave hardware will always stretch the clock after the
ACK sequence. Once the slave is ready, CKP is set by Any time the CKP bit is cleared, the module will wait
software and communication resumes. for the SCLx line to go low and then hold it. However,
Note 1: The BF bit has no effect if the clock will be clearing the CKP bit will not assert the SCLx output
stretched or not. The previous version of low until the SCLx output is already sampled low.
the module did not stretch the clock if Therefore, the CKP bit will not assert the SCLx line
SSPxBUF was read before the 9th falling until an external I2C master device has already
edge of SCLx. asserted the SCLx line. The SCLx output will remain
low until the CKP bit is set and all other devices on the
2: The previous versions of the module did I2C bus have released SCLx. This ensures that a write
not stretch the clock for a transmission if to the CKP bit will not violate the minimum high time
SSPxBUF was loaded before the 9th fall- requirement for SCLx (see Figure 24-23).
ing edge of SCLx. It is now always cleared
for read requests.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx DX DX ‚ – 1
SCLx
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDAx ended with a Stop condition or with a Repeated Start
and SCKx pins must be configured as inputs. The condition. Since the Repeated Start condition is also
MSSP peripheral hardware will override the output the beginning of the next serial transfer, the I2C bus will
driver TRIS controls when necessary to drive the pins not be released.
low. In Master Transmitter mode, serial data is output
Master mode of operation is supported by interrupt through SDAx, while SCLx outputs the serial clock. The
generation on the detection of the Start and Stop first byte transmitted contains the slave address of the
conditions. The Stop (P) and Start (S) bits are cleared receiving device (seven bits) and the Read/Write (R/W)
from a Reset or when the MSSPx module is disabled. bit. In this case, the R/W bit will be logic ‘0’. Serial data
Control of the I 2C bus may be taken when the P bit is is transmitted eight bits at a time. After each byte is
set, or the bus is Idle. transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
In Firmware Controlled Master mode, user code
and the end of a serial transfer.
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition In Master Receive mode, the first byte transmitted
detection is the only active circuitry in this mode. All contains the slave address of the transmitting device
other communication is done by the user software (seven bits) and the R/W bit. In this case, the R/W bit
directly manipulating the SDAx and SCLx lines. will be logic ‘1’. Thus, the first byte transmitted is a 7-bit
slave address followed by a ‘1’ to indicate the receive
The following events will cause the SSPx Interrupt Flag bit. Serial data is received via SDAx, while SCLx
bit, SSPxIF, to be set (SSPx interrupt, if enabled): outputs the serial clock. Serial data is received eight
• Start condition detected bits at a time. After each byte is received, an
Acknowledge bit is transmitted. Start and Stop
• Stop condition detected
conditions indicate the beginning and end of
• Data transfer byte transmitted/received transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated frequency output on SCLx. See Section 24.7 “Baud
Rate Generator” for more details.
Note 1: The MSSPx module, when configured in
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur.
2: Master mode suspends Start/Stop
detection when sending the Start/Stop
condition by means of the SEN/PEN
control bits. The SSPxIF bit is set at the
end of the Start/Stop generation when
hardware clears the control bit.
SDAx DX DX ‚ – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCLx
S
TBRG
BF (SSPxSTAT<0>)
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS40001414E-page 269
PIC16(L)F1946/47
PIC16(L)F1946/47
24.6.7 I2C MASTER MODE RECEPTION 24.6.7.4 Typical Receive Sequence
Master mode reception is enabled by programming the 1. The user generates a Start condition by setting
Receive Enable bit, RCEN bit of the SSPxCON2 the SEN bit of the SSPxCON2 register.
register.
2. SSPxIF is set by hardware on completion of the
Note: The MSSPx module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCLx pin changes 5. Address is shifted out the SDAx pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPxSR. After the falling edge of the eighth clock, the soon as SSPxBUF is written to.
receive enable flag is automatically cleared, the con- 6. The MSSPx module shifts in the ACK bit from
tents of the SSPxSR are loaded into the SSPxBUF, the the slave device and writes its value into the
BF flag bit is set, the SSPxIF flag bit is set and the Baud ACKSTAT bit of the SSPxCON2 register.
Rate Generator is suspended from counting, holding 7. The MSSPx module generates an interrupt at
SCLx low. The MSSPx is now in Idle state awaiting the the end of the ninth clock cycle by setting the
next command. When the buffer is read by the CPU, SSPxIF bit.
the BF flag bit is automatically cleared. The user can
8. User sets the RCEN bit of the SSPxCON2
then send an Acknowledge bit at the end of reception
register and the Master clocks in a byte from the
by setting the Acknowledge Sequence Enable, ACKEN
slave.
bit of the SSPxCON2 register.
9. After the eighth falling edge of SCLx, SSPxIF
24.6.7.1 BF Status Flag and BF are set.
10. Master clears SSPxIF and reads the received
In receive operation, the BF bit is set when an address
byte from SSPxUF, clears BF.
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read. 11. Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
24.6.7.2 SSPOV Status Flag ACK by setting the ACKEN bit.
In receive operation, the SSPOV bit is set when eight 12. Masters ACK is clocked out to the Slave and
bits are received into the SSPxSR and the BF flag bit is SSPxIF is set.
already set from a previous reception. 13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
24.6.7.3 WCOL Status Flag from the slave.
If the user writes the SSPxBUF when a receive is 15. Master sends a not ACK or Stop to end
already in progress (i.e., SSPxSR is still shifting in a communication.
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDAx = 0, SCLx = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDAx = ACKDT = 0 automatically
DS40001414E-page 271
PIC16(L)F1946/47
PIC16(L)F1946/47
24.6.8 ACKNOWLEDGE SEQUENCE 24.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the
generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx
When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 24-30).
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode 24.6.9.1 WCOL Status Flag
(Figure 24-29). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
24.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
SCLx 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDAx ACK
P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
SDAx
BCLxIF
SDAx
SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 SSPx module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared by software
SSPxIF
TBRG TBRG
SDAx
FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCLx S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
BCLxIF ’0’
SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF by software
SDAx
SCLx
RSEN
BCLxIF
Cleared by software
S ’0’
SSPxIF ’0’
TBRG TBRG
SDAx
SCLx
S ’0’
SSPxIF
PEN
BCLxIF
P ’0’
SSPxIF ’0’
SDAx
PEN
BCLxIF
P ’0’
SSPxIF ’0’
SSPM<3:0> SSPxADD<7:0>
Legend:
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)(1)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)(1)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)(1)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable bit(1)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in Idle mode, this bit may not be set
(no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
REGISTER 24-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address byte:
TXEN
TRMT
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCxIF Interrupt
RCxIE
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TXx/CKx pin Start bit Start bit
bit 0 bit 1 bit 7/8 Stop bit bit 0
TXxIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg
Reg. Empty Flag) Transmit Shift Reg
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD FOSC = 32.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 191 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 103 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.14k -0.79 34 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 117.64k 2.12 16 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPxBRGH: SPxBRGH: SPxBRGH: SPxBRGH:
Actual % Actual % Actual % Actual %
SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200.1 0.02 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2401 -0.04 832 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 207 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 191 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 103 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 57.14k -0.79 34 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 117.6k 2.12 16 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPxBRGH: SPxBRGH: SPxBRGH: SPxBRGH:
Actual % Actual % Actual % Actual %
SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPxBRGH: SPxBRGH: SPxBRGH: SPxBRGH:
Actual % Actual % Actual % Actual %
SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.00 26666 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 0.00 6666 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.01 3332 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9604 0.04 832 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 767 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.18k -0.08 416 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 115.9 0.64 68 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPxBRGH: SPxBRGH: SPxBRGH: SPxBRGH:
Actual % Actual % Actual % Actual %
SPxBRGL SPxBRGL SPxBRGL SPxBRGL
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
BRG Clock
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RXx/DTx Line
RCxIF
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
TXx/CKx pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit
RXx/DTx
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCxIF bit
(Interrupt)
Read
RCxREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Timer0 Module
CPSCH<3:0> Set
CPSON(1) TMR0CS TMR0IF
T0XCS
CPS0 FOSC/4 0
Overflow
CPS1 T0CKI 0 TMR0
1
CPS2 1
CPS3 CPSRNG<1:0>
CPS4 CPSON
CPS5
CPS6
Capacitive
CPS7 Sensing Timer1 Module
CPS8 Oscillator
TMR1CS<1:0>
CPS9 CPSOSC
CPS10 FOSC
FOSC/4
CPS11 CPSCLK
0 Int.
CPS12 Ref- Ref. T1OSC/ TMR1H:TMR1L
EN
1 DAC T1CKI
CPS13
Output T1GSEL<1:0>
CPS14 0
Ref+ CPSOUT
CPS15 T1G
1 FVR
CPS16 Timer1 Gate
sync_C1OUT Control Logic
sync_C2OUT
CPSRM
Oscillator Module
VDD
(1)
(2)
+
-
S Q CPSCLK
CPSx
Internal
References
0 0
Ref- Ref+
1 DAC 1 FVR
CPSRM
Note 1: Module Enable and Power mode selections are not shown.
2: Comparators remain active in Noise Detection mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
LCDDATAx SEG<23:0>
Data Bus
MUX To I/O Pads(1)
Registers
Timing Control
LCDCON
COM<3:0>
LCDPS To I/O Pads(1)
LCDSEn
FOSC/256
Clock Source
T1OSC
Select and
Prescaler
LFINTOSC
Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
COM0
COM1
COM2
COM3
FOSC ÷256 To Ladder
Power Control
÷4 Static
T1OSC 32 kHz
Crystal Osc. 4-bit Prog Segment ÷1, 2, 3, 4
÷2 1/2 ÷ 32
Prescaler Counter Clock Ring Counter
1/3,
LFINTOSC 1/4
Nominal = 31 kHz
LP<3:0>
CS<1:0>
LMUX<1:0>
VDD LCDIRE
LCDIRS
LCDA
1.024V from
FVR 3.072V
x3 Power Mode Switching
LCDIRE (LRLAP or LRLBP)
LCDIRS A 2
LCDA
2 B 2
LCDCST<2:0>
VLCD3PE LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0
FIGURE 27-4: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE A
Single Segment Time
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01
Segment Clock
LRLAT<2:0> ‘H3
Segment Data
LRLAT<2:0>
Power Mode Power Mode A Power Mode B Mode A
COM0
V1
V0
V1
SEG0 V0
V1
COM0-SEG0 V0
-V1
PIC16(L)F1946/47
DRIVE)
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F
Segment Clock
Segment Data
Power Mode Power Mode A Power Mode B Power Mode A Power Mode B
V1
COM0-SEG0 V0
-V1
-V2
2010-2016 Microchip Technology Inc.
FIGURE 27-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS
2010-2016 Microchip Technology Inc.
DRIVE)
Single Segment Time Single Segment Time Single Segment Time Single Segment Time
32 kHz Clock
Ladder Power
Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F
Segment Clock
Segment Data
Power Mode Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B
V2
V1
COM0-SEG0 V0
PIC16(L)F1946/47
-V1
-V2
DS40001414E-page 336
PIC16(L)F1946/47
27.6 Register Definitions: LCD Ladder Control
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time interval A (Refer to Figure 27-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time interval B (Refer to Figure 27-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time interval control bits
Sets the number of 32 kHz clocks that the A Time interval power mode is active
R R R R
3.072V
7
To top of
Reference Ladder
0
LCDCST<2:0>
3
Internal Reference Contrast control
V1
COM0 pin
V0
COM0
V1
SEG0 pin
V0
V1
SEG1 pin
V0
V1
COM0-SEG0 V0
segment voltage
(active) -V1
COM0-SEG1 V0
segment voltage
1 Frame
(inactive)
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
V2
COM0 pin V1
COM1
V0
V2
COM1 pin V1
COM0
V0
V2
SEG0 pin V1
V0
V2
SEG1 pin V1
V0
SEG3
SEG2
SEG1
V2
SEG0
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
1 Frame
1 Segment Time
V2
COM1
COM0 pin V1
V0
COM0
V2
COM1 pin V1
V0
V2
SEG0 pin
V1
V0
V2
SEG1 pin
SEG1
SEG0
SEG2
SEG3
V1
V0
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
2 Frames
1 Segment Time
V3
V2
COM1 COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
V3
V2
SEG1 pin
SEG1
SEG0
SEG3
SEG2
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
-V2
1 Frame
-V3
1 Segment Time
V3
V2
COM1 COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
V3
V2
SEG1 pin
SEG1
SEG0
SEG3
SEG2
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(active) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(inactive) -V1
2 Frames -V2
-V3
1 Segment Time
V2
COM0 pin
V1
V0
V2
COM2 COM1 pin V1
V0
COM1 V2
COM0 COM2 pin V1
V0
V2
SEG0 and
SEG2 pins V1
V0
V2
SEG1 pin V1
V0
SEG2
SEG1
SEG0
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
1 Frame
1 Segment Time
V2
COM0 pin
V1
V0
COM2
V2
COM1 pin
V1
COM1
V0
COM0
V2
COM2 pin
V1
V0
V2
SEG0 pin
V1
V0
SEG2
SEG1
SEG0
V2
SEG1 pin
V1
V0
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
2 Frames
1 Segment Time
V3
V2
COM0 pin
V1
V0
COM2 V3
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
SEG0 and
SEG2 pins V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
-V3
1 Frame
1 Segment Time
COM2 V3
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage
(inactive) -V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
segment voltage
(active) -V1
-V2
-V3
2 Frames
1 Segment Time
Note: 1 Frame = 2 single-segment times.
COM3 V3
V2
COM0 pin V1
COM2 V0
V3
V2
COM1 pin V1
COM1
V0
COM0
V3
V2
COM2 pin V1
V0
V3
V2
COM3 pin V1
V0
V3
V2
SEG0 pin V1
V0
V3
SEG1
SEG0
V2
SEG1 pin V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage -V1
-V2
(active) -V3
V3
V2
V1
COM0-SEG1 V0
segment voltage -V1
-V2
(inactive) -V3
1 Frame
1 Segment Time
COM3 V3
V2
COM0 pin V1
COM2 V0
V3
V2
COM1 pin V1
COM1
V0
COM0
V3
V2
COM2 pin V1
V0
V3
V2
COM3 pin V1
V0
V3
V2
SEG0 pin V1
V0
V3
SEG1
SEG0
V2
SEG1 pin V1
V0
V3
V2
V1
COM0-SEG0 V0
segment voltage -V1
-V2
(active) -V3
V3
V2
V1
COM0-SEG1 V0
segment voltage -V1
-V2
(inactive) -V3
2 Frames
1 Segment Time
V3
V2
COM1 V1
V0
V3
V2
COM2 V1
V0
COM3 V3
V2
V1
V0
2 Frames
TFINT
TFWR Frame
Frame Frame
Boundary Boundary Boundary
V3
V2
V1
COM0 V0
V3
V2
V1
COM1 V0
V3
V2
V1
COM2 V0
V3
V2
V1
SEG0 V0
2 Frames
RJ11-6PIN
R1
To MPLAB® ICD 2 To Target Board
270 Ohm
LM431BCMX
2 A 1
K
3 A U1
6 A NC 4
7 A NC 5
VREF
8
R2 R3
10k 1% 24k 1%
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C
Before Instruction
W = 0x07
After Instruction
W = value of k8
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.
125
± 5%
85
± 3%
Temperature (°C)
60
25 ± 2%
0
-20 ± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
VPOR
VPORR
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2) TPOR(3)
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2 REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RF0).
6: 8 MHz crystal oscillator with 4x PLL enabled.
— 27 60 88 A 5.0
D024 — 0.5 6.0 9.0 A 1.8 LPWDT Current (Note 1)
— 0.8 7.0 10 A 3.0
D024 — 23 57 65 A 1.8 LPWDT Current (Note 1)
— 26 59 80 A 3.0
— 28 61 90 A 5.0
D025 — 15 28 30 A 1.8 FVR current
— 15 30 33 A 3.0
D025 — 38 96 100 A 1.8 FVR current (Note 4)
— 45 110 120 A 3.0
— 90 140 155 A 5.0
D026 — 13 16 20 A 3.0 BOR Current (Note 1)
D026 — 40 110 120 A 3.0 BOR Current (Note 1, Note 4)
— 87 140 155 A 5.0
D027 — 0.6 6.0 9.0 A 1.8 T1OSC Current (Note 1)
— 1.8 10 12 A 3.0
D027 — 22 57 60 A 1.8 T1OSC Current (Note 1)
— 29 62 70 A 3.0
— 35 66 85 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
4: 0.1 F capacitor on VCAP (RF0).
— 27 61 88 A 5.0
D029 — 250 — — A 1.8 A/D Current (Note 1, Note 3),
— 250 — — A 3.0 conversion in progress
— 280 — — A 5.0
D030 — 1 — — A 3.0 LCD Bias Ladder, Low-power
— 10 — — A 3.0 LCD Bias Ladder, Medium-power
— 75 — — A 3.0 LCD Bias Ladder, High-power
D030 — 1 — — A 5.0 LCD Bias Ladder, Low-power
— 10 — — A 5.0 LCD Bias Ladder, Medium-power
— 75 — — A 5.0 LCD Bias Ladder, High-power
D031 — 7.6 22 25 A 1.8 Comparator, Low-Power mode
— 8.0 23 27 A 3.0
D031 — 24 55 65 A 1.8 Comparator, Low-Power mode
— 26 58 80 A 3.0
— 28 60 90 A 5.0
D032A* — 2.0 — — A 1.8 Cap Sense, Low-Power mode,
— 3.0 — — A 3.0 CPSRM=0
— 30 — — A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
4: 0.1 F capacitor on VCAP (RF0).
— 62 — — A 5.0
D032F* — 120 — — A 1.8 Cap Sense, High-Power mode,
— 160 — — A 3.0 CPSRM = 1, includes FVR and
DAC current
D032F* — 150 — — A 1.8 Cap Sense, High-Power mode,
— 180 — — A 3.0 CPSRM = 1, includes FVR and
DAC current
— 190 — — A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
4: 0.1 F capacitor on VCAP (RF0).
TH01 JA Thermal Resistance Junction to Ambient 48.3 C/W 64-pin TQFP package
28 C/W 64-pin QFN package
TH02 JC Thermal Resistance Junction to Case 26.1 C/W 64-pin TQFP package
0.24 C/W 64-pin QFN package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2),(3)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low)
DC — 4 MHz EC Oscillator mode (medium)
DC — 20 MHz EC Oscillator mode (high)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 4 MHz HS Oscillator mode
1 — 20 MHz HS Oscillator mode, VDD > 2.7V
DC — 4 MHz RC Oscillator mode, VDD > 2.0V
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode
250 — ns XT Oscillator mode
50 — ns HS Oscillator mode
50 — ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High, 2 — — s LP oscillator
TosL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Para
m Sym. Characteristic Min. Typ† Max. Units Conditions
No.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage(1) — ±7.5 ±60 mV High-Power mode
VICM = VDD/2
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio — 50 — dB
CM04A Response Time Rising Edge — 400 800 ns High-Power mode
CM04B Response Time Falling Edge — 200 400 ns High-Power mode
TRESP
CM04C Response Time Rising Edge — 1200 — ns Low-Power mode
CM04D Response Time Falling Edge — 550 — ns Low-Power mode
CM05 TMC2OV Comparator Mode Change to Output — — 10 s
Valid*
CM06 CHYSTER Comparator Hysteresis(2) — 45 — mV CxHYS = 1
* These parameters are characterized but not tested.
Note 1: High power only.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CK
US121 US121
DT
US120 US122
CK
US125
DT
US126
SS
SP70
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — — Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
VCTH
VCTL
ISRC ISNK
Enabled Enabled
14
Max: 85°C + 3ı Max.
12 Typical: 25°C
10
8
IDD (μA)
Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
60
Max: 85°C + 3ı
Typical: 25°C
50 Max.
40
Typical
IDD (μA)
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
450
Typical: 25°C 4 MHz XT
400
250
200
150
1 MHz XT
100
50
1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
550
500 Max: 85°C + 3ı
4 MHz XT
450
400
4 MHz EXTRC
350
IDD (μA)
300
250
200
150 1 MHz XT
100
50 1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
500
Typical: 25°C 4 MHz XT
4 MHz EXTRC
400
300
IDD (μA)
200 1 MHz XT
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
600
Max: 85°C + 3ı 4 MHz XT
500
4 MHz EXTRC
400
IDD (μA)
300
1 MHz XT
200
1 MHz EXTRC
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
12
10 Max: 85°C + 3ı
Typical: 25°C
Max.
8
IDD (μA)
Typical
4
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-8: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16F1946/47 ONLY
50
45 Max: 85°C + 3ı
Max.
Typical: 25°C
40
35
Typical
30
IDD (μA)
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
60
40
IDD (μA)
30
20 Typical
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-10: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16F1946/47 ONLY
90
Max: 85°C + 3ı Max.
80 Typical: 25°C
70
60
Typical
IDD (μA)
50
40
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
450
Typical: 25°C
400
4 MHz
350
300
250
IDD (μA)
200
150
100
1 MHz
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
500
Max: 85°C + 3ı
450
4 MHz
400
350
300
IDD (μA)
250
200
150
100 1 MHz
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
450
Typical: 25°C
400 4 MHz
350
300
IDD (μA)
250
200
1 MHz
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
500
350
300
IDD (μA)
250
200 1 MHz
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
3.5
Typical: 25°C
3.0
2.0
1.5 16 MHz
IDD (μA)
1.0
8 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
4.0
3.0
32 MHz (PLL)
2.5
2.0
16 MHz
IDD (μA)
1.5
1.0
8 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
3.5
Typical: 25°C
3.0
32 MHz (PLL)
2.5
2.0
IDD (μA)
16 MHz
1.5
1.0 8 MHz
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
3.5
Max: 85°C + 3ı
3.0 32 MHz (PLL)
2.5
2.0
IDD (μA)
16 MHz
1.5
8 MHz
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
12
Max: 85°C + 3ı
10 Typical: 25°C
Max.
8
IDD (μA)
6
Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
50
Max: 85°C + 3ı Max.
45
Typical: 25°C
40
35
Typical
IDD (μA)
30
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
180
Max: 85°C + 3ı
160 Typical: 25°C Max.
140
120 Typical
IDD (μA)
100
80
60
40
20
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 31-22: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1946/47 ONLY
300
Max: 85°C + 3ı
Typical: 25°C Max.
250
200 Typical
IDD (μA)
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
4000
Typical: 25°C 32 MHz (PLL)
3500
3000
2500
IDD (μA)
2000
16 MHz
1500
1000 8 MHz
500
4 MHz
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
4500
Max: 85°C + 3ı
4000
32 MHz (PLL)
3500
3000
IDD (μA)
2500
2000 16 MHz
1500
1000 8 MHz
500
4 MHz
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
3500
2500
2000
IDD (μA)
16 MHz
1500
8 MHz
1000 4 MHz
500
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
4000
Max: 85°C + 3ı 32 MHz (PLL)
3500
3000
2500
IDD (μA)
2000 16 MHz
1500 8 MHz
1000 4 MHz
500
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
4500
Max: 85°C + 3ı
4000 32 MHz (PLL)
Typical: 25°C
3500
3000
2500
IDD (μA)
20 MHz
2000
1500
1000 8 MHz
500
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
5000
Max: 85°C + 3ı
4500 32 MHz (PLL)
Typical: 25°C
4000
3500
3000
IDD (μA)
2500 20 MHz
2000
1500
1000 8 MHz
500
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
3500
1500
1000 8 MHz
500
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
3500
Max: 85°C + 3ı
3000 32 MHz (PLL)
2500 20 MHz
2000
IDD (μA)
1500
8 MHz
1000
500
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
1200
Max.
1000 Max: 85°C + 3ı
Typical: 25°C
800
(nA)
IPD (nA
600
400
200
Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
45
30
Typical
μA)
IPD (μA)
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
2500
Max: 85°C + 3ı
Typical: 25°C
2000
1500 Max.
D (nA)
IPD
1000
Typical
500
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
45
Max: 85°C + 3ı
40
Typical: 25°C Max.
35
30
Typical
(μA)
IPD (μA
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
14
Max: 85°C + 3ı
13
Typical: 25°C
12 Max.
11
10
Typical
IPD (μA)
4
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
120
80 Typical
(μA)
IPD (μA
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
12
Max: 85°C + 3ı M
Max.
11 Typical: 25°C
10
9
(μA)
IPD (μ
8 Typical
4
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
50
Max: 85°C + 3ı
45 Max.
Typical: 25°C
40
35
Typical
30
IPD (μA)
25
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
14
Max: 85°C + 3ı
12 Typical: 25°C
10
Max.
8
(μA)
IPD (μA
4 Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
60
Max: 85°C + 3ı
50 Max.
Typical: 25°C
40
(μA)
Typical
IPD (μA
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Max: 85°C + 3ı M
Max.
7
Typical: 25°C
6
5
(μA)
IPD (μA
4
Typical
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
45
Max: 85°C + 3ı
40 Max.
Typical: 25°C
35
30
Typical
(μA)
25
IPD (μA
20
15
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
14
Max: 85°C + 3
M 3ı
12 Typical: 25°C Max.
10
8
IPD (μA)
Typical
6
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
60
Max: 85°C + 3
M 3ı
50 Typical: 25°C Max.
40
Typical
yp
(μA)
IPD (μA
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
70
Max: 85°C + 3ı
60 Typical: 25°C
Max.
50
40
IPD (μA)
Typical
30
20
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
140
100
80
IPD (μA)
Typical
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
30
Max: 85°C + 3ı
Typical: 25°C Max
Max.
25
20
Typical
(μA)
IPD (μ
15
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
60
Max: 85°C + 3ı
50 Typical: 25°C Max.
40
Typical
(μA)
IPD (μA
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
60
Max: 85°C + 3
M 3ı
50 Typical: 25°C Max.
40
(μA)
Typical
IPD (μA
30
20
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
80
Max: 85°C + 3ı
70 Typical: 25°C Max.
60
50 Typical
IPD (μA)
40
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Graph represents
5
3ı Limits
4
VOH (V)
-40°C
3
125°C
2 Typical
0
-30 -25 -20 -15 -10 -5 0
IOH (mA)
FIGURE 31-52: VOL VS. IOL OVER TEMPERATURE, VDD = 5.0V, PIC16F1946/47 ONLY
Graph represents
4 3ı Limits
3
VOL (V)
-40°C
2 Typical
125°C
0
0 10 20 30 40 50 60 70 80
IOL (mA)
3.5
2.5
2.0
VOH (V)
1.5 125°C
Typical
1.0
-40°C
0.5
0.0
-14 -12 -10 -8 -6 -4 -2 0
IOH (mA)
3.0
Graph represents
2.5
3ı Limits
2.0
VOL (V)
-40°C
1.5 Typical
125°C
1.0
0.5
0.0
0 5 10 15 20 25 30
IOL (mA)
2.0
1.4
1.2
VOH (V)
1.0 125°C
0.8
Typical
0.6 -40°C
0.4
0.2
0.0
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
IOH (mA)
1.8
1.2
Vol (V)
1
125°C Typical
0.8
-40°C
0.6
0.4
0.2
0
0 1 2 3 4 5 6 7 8 9 10
IOL (mA)
2.10
1.90
1.85 Min.
1.80
1.75
1.70
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
70
Max.
60
50
Typical
Voltage (mV)
40
30
Min.
20
Max: Typical + 3ı
10 Typical: 25°C
Min: Typical - 3ı
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
2.90
2.70
Voltage (V)
2.65
Min.
2.60
2.55
2.50
2.45
2.40
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
90
80
Max.
70
60
Voltage (mV)
50 Typical
40
30
20 Max: Typical + 3ı
Min. Typical: 25°C
10 Min: Typical - 3ı
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
120
Max: Typical + 3ı
Typical: 25°C
100
Min: Typical - 3ı
Max.
Hysteresis (mV)
80
60 Typical
40
Min.
20
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)
25
Max: Typical + 3ı
Typical: 25°C
20 Min: Typical - 3ı
Max.
Hysteresis (mV)
15
Typical
10
Min.
5
0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)
390
Max: Typical + 3ı
340 Typical: 25°C
290
Time (nS)
240
Max.
190
Typical
140
90
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)
260
Graph represents
240
3ı Limits
220
Time (nS)
200
180
125°C
160
Typical
-40°C
140
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)
60
40
Max.
20
Offset Voltage (V)
Typical
0
Min.
-20
Max: Typical + 3ı
-40 Typical: 25°C
Min: Typical - 3ı
-60
0 1 2 3 4 5
Common Mode Voltage (V)
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
PIN 1 PIN 1
XXXXXXXXXXX PIC16F1947
XXXXXXXXXXX -I/MR e3
XXXXXXXXXXX 1110017
YYWWNNN
XXXXXXXXXX PIC16F1947
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 1110017
YYWWNNN
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
E1/2
A B
E1 E
A A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C 0.08 C A-B D
e
SIDE VIEW
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
L T
(L1) X=A—B OR D
SECTION A-A X
e/2
DETAIL 1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
C2
Y1
X1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Contact Pad Spacing C1 11.40
Contact Pad Spacing C2 11.40
Contact Pad Width (X28) X1 0.30
Contact Pad Length (X28) Y1 1.50
Distance Between Pads G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.