About Wrapper Chains

The ATPG process on very large, complex designs can often be unpredictable. This problem is
especially true for large sequential or partial scan designs. To reduce this unpredictability, a
number of hierarchical techniques for test structure insertion and test generation are beginning
to emerge. Creating wrapper chains is one of these techniques. Large designs that are split into a
number of design blocks benefit most from wrapper chains.
Wrapper chains add controllability and observability to the design via a hierarchical wrapper
scan chain. A wrapper chain is a series of scan cells connected around the boundary of a design
partition that is accessible at the design level. The wrapper chain improves both test coverage
and run time by converting sequential elements to scan cells at inputs (outputs) that have low
controllability (observability) from outside the block.
Scan chains – the backbone of DFT
A scan insertion tool should provide testability analysis, design rule check (DRC) debugging,
test logic insertion, scan cell insertion, and scan chain stitching. ... With hierarchical DFT, the
pattern generation is performed concurrently on the blocks early in the design phase,
taking DFT out of the critical path

What are scan chains: Scan chains are the elements in scan-based designs that are used to shift-
in and shift-out test data. A scan chain is formed by a number of flops connected back to back in a
chain with the output of one flop connected to another. The input of first flop is connected to the input
pin of the chip (called scan-in) from where scan data is fed. The output of the last flop is connected
to the output pin of the chip (called scan-out) which is used to take the shifted data out. The figure
below shows a scan chain.

A scan chain

Purpose of scan chains: As said above, scan chains are inserted into designs to shift the test data
into the chip and out of the chip. This is done in order to make every point in the chip controllable
and observable as discussed below.

How normal flop is transformed into a scan flop: The flops in the design have to be modified in
order to be put in the scan chains. To do so, the normal input (D) of the flip-flop has to be
multiplexed with the scan input. A signal called scan-enable is used to control which input will
propagate to the output.

Figure showing transition of a normal flop to scan flop

   
If scan-enable = 0, data at D pin of the flop will propagate to Q at the next active edge
If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge

Scan terminology: Before we talk further, it will be useful to know some signals used in scan chains
which are as follows:
 Scan-in: Input to the flop/scan-chain that is used to provide scan data into it 
 Scan-out: Output from flop/scan-chain that provides the scanned data to the next
flop/output 
 Scan-enable: Input to the flop that controls whether scan_in data or functional data will
propagate to output

Purpose of testing using scan: Scan testing is carried out for various reasons, two most prominent of
them are: 
  To test stuck-at faults in manufactured devices 
  To test the paths in the manufactured devices for delay; i.e. to test whether each path is
working at functional frequency or not
How a scan chain functions: The fundamental goal of scan chains is to make each node in the
circuit controllable and observable through limited number of patterns by providing a bypass path to
each flip-flop. Basically, it follows these steps: 
1.  Assert scan_enable (make it high) so as to enable (SI -> Q) path for each flop 

2.  Keep shifting in the scan data until the intended values at intended nodes are reached 

3.  De-assert scan_enable (for one pulse of clock in case of stuck-at testing and two or more
cycles in case of transition testing) to enable D->Q path so that the combinational cloud output can
be captured at the next clock edge. 
4.  Again assert scan_enable and shift out the data through scan_out

How Chain length is decided: By chain length, we mean the number of flip-flops in a single scan
chain. Larger the chain length, more the number of cycles required to shift the data in and out.
However, considering the number of flops remains same, smaller chain length means more number
of input/output ports is needed as scan_in and scan_out ports. As 

                Number of ports required = 2 X Number of scan chains

Since for each scan chain, scan_in and scan_out port is needed. Also,

               Number of cycles required to run a pattern = Length of largest scan chain in design

Suppose, there are 10000 flops in the design and there are 6 ports available as input/output. This
means we can make (6/2=) 3 chains. If we make scan chains of 9000, 100 and 900 flops, it will be
inefficient as 9000 cycles will be required to shift the data in and out. We need to distribute flops in
scan chains almost equally. If we make chain lengths as 3300, 3400 and 3300, the number of cycles
required is 3400.
Keeping almost equal number of flops in each scan chain is referred to as chain balancing.

Definition of clock skew: Clock skew between two flip-flops represents the difference in arrival
times of clock signal at the respective clock pins. If there is a timing path being formed between the
two flip-flops, then we can attribute a sign to the clock skew. In that case, clock skew is given as:
Clock skew = (Arrival time at capture clock pin) - (Arrival time at launch clock pin)
Thus, based upon the sign of clock skew, we get two types of clock skew labelled as positive skew
and negative skew.

Positive clock skew: If the clock arrival time at capture flip-flop is greater than that at launch flip-
flop, clock skew is said to be positive. Assuming all buffers take the same delay, figure 1 shows a
scenario of positive clock skew.

As shown in figure 1 above for the case of positive clock skew, flip-flop capturing data is getting
delayed clock signal. So, the data that is launched gets additional time before it is captured at the
next edge. So, setup check gets relaxed by the amount equivalent to clock skew. On the other hand,
for hold check, the data has to be kept stable for an extra amount of time equal to the clock skew.
So, hold check gets relaxed in case clock skew is positive. The same is shown in figure 2 below.

Negative clock skew: Contrary to positive clock skew, if the clock arrival time at capture flip-flop is
less than the launch flip-flop, clock skew is said to be negative. Figure 3 shows a scenario of
negative clock skew as the launch flip-flop getting a delayed version of clock signal.
Since, the launching flip-flop is getting a delayed version of clock, the data launched gets less than
one clock period to travel to the capturing flip-flop. So, negative clock skew makes setup check
tighter by the magnitude of clock skew. On the other hand, for hold check, data has to be stable for
less time after the arrival of clock edge. In other words, hold check gets relaxed by the same
amount. Figure 4 below shows the scenario of negative clock skew.

5.2.1.6 False Paths

False paths are not normal functional paths. They do no harm to the chip during
normal operation; however, for delay fault testing, a pseudo-random pattern might
adversely attempt to test a selected false path. Because false paths are not exercised
during normal circuit operation, they typically do not meet timing specifications,
which can result in a mismatch during logic BIST delay fault testing. To avoid this
potential problem, we recommend adding a 0-control point or 1-control point to
each false path.
5.2.1.7 Critical Paths
Critical paths are timing-sensitive functional paths. Because the timing of these
paths is critical, no additional gates are allowed to be added to the path, to prevent
increasing the delay of the critical path. In order to remove an unknown (X)
value from a critical path, we recommend adding an extra input pin to a selected
combinational gate, such as an inverter, NAND gate, or NOR gate, on the critical
path to minimize the added delay. The combinational gate is then converted to
an embedded 0-control point or embedded 1-control point as shown in Figure 5.7,
where an inverter is selected for adding the extra input.
5.2.1.8 Multiple-Cycle Paths
Multiple-cycle paths are normal functional paths but data are expected to arrive
after two or more cycles. Similar to false paths, they can cause mismatches if
exercised during delay fault testing, as they are intended to be tested in one cycle. To
avoid this potential problem, we recommend adding a 0-control point or 1-control
point to each multiple-cycle path or holding certain scan cell output states to avoid
those multiple-cycle paths.

sequential depth
The sequential depth of a circuit is equal to the maximum number of clock cycles
that must be applied in order to control and observe values to and from all nonscan
storage elements. In a full-scan design, because all scan cells can be controlled
and observed directly in shift mode, the sequential depth of a full-scan circuit is
0. Similarly, the sequential depth of a combinational logic block is also 0. In a
partial-scan design, replacing a storage element with a scan cell is equivalent to
removing its corresponding vertex from the structure graph.