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constant maxint: integer := 16#ffff#; Relational: = , /= , < , <= , > , >=
VHDL Cheatsheet type arith_mode_type is (signed, unsigned);
function minimum(constant a, b : in integer) return integer;
Arithmetic: + , - , * , / , mod , rem , ** (exponential), abs
end ee530; Concatenate: &
Based on https://www.ics.uci.edu/~jmoorkan/vhdlref/vhdl.html
Package body format VHDL DATA TYPES
PRIMARY DESIGN UNIT MODEL package body <name> is Predefined Scalar Data Types (single objects)
STRUCTURE ... exported subprogram bodies
... other internally-used declarations
end <name>; VHDL Standard
Entity Example
bit : 0 , 1
boolean : TRUE , FALSE
integer : -(231) to +(231 - 1) (SUN Limit)
entity <name> is package body ee530 is natural : 0 to integer'high (subtype of integer)
port( <port definition list> ); -- input/output signal ports function minimum (constant a,b : integer) return integer is positive : 1 to integer'high (subtype of integer)
generic( <generic list> ); -- optional generic list variable c : integer; -- local variable
end <name>; character : ASCII characters (eg. A )
begin
if a < b then time : (include units; eg. 10ns, 20us)
c := a; -- a is min
Port declaration format: <port name>: <mode> <data type>; else
c := b; -- b is min IEEE Standard 1164 (package ieee.std_logic_1164.all )
end if;
return c; -- return min value
in : can be read but not updated within the module
end; std_ulogic : U , X , 1 , 0 , Z , W , H , L , -
out : can be updated but not read within the module end ee530; std_logic : resolved std_ulogic values
buffer : likewise carries information out of a module, but can be both updated and read within the
X01 : subtype { X , 0 , 1 } of std_ulogic
module.
X01Z : subtype { X , 0 , 1 , Z } of std_ulogic
inout : is bidirectional and can be both read and updated, with multiple update sources possible. Package Visibility UX01 : subtype { U , X , 0 , 1 } of std_ulogic
UX01Z : subtype { U , X , 0 , 1 , Z } of std_ulogic
16#9fba# (hexadecimal)
2#1111_1101_1011# (binary)
package <name> is 16#f.1f#E+2 (floating-point, exponent is decimal) Other user-defined types
... exported constant declarations
... exported type declarations
... exported subprogram declarations Constrained array: Upper and lower indexes are specified:
end <name>; Bit String Literals type aWord is array (0 to 15) of bit;
constant cWord1 : word := (0 => '0', 1 => '1', 7 => '1', others => '0');
constant cWord2 : word := ('0', '0', '0', '0', '0', '0', '0', ...);
Example x"ffe" (12-bit hexadecimal value)
o"777" (9-bit octal value)
b"1111_1101_1101" (12-bit binary value)
Unconstrained array:
if <condition> then
The port list may be in either of two formats:
CONCURRENT STATEMENTS <sequence of statements>
elsif <condition> then
<sequence of statements>
(1) Positional association: signals are connected to ports in the order listed in the component else
Concurrent Signal Assignment declaration. Example: A1: adder port map (v,w,x,y,z) (v,w, and y must be of type <sequence of statements>
bit_vector , y and z of type bit ) end if;
(2) Named association: each signal-to-port connection is listed explicitly as signal => port .
1. A <= B;
case <expression> is Function Calls S'LAST_EVENT : time at which S last changed
when <choice(s)> => <sequence of statements> S'LAST_ACTIVE : time at which S last active
when <choice range> => <sequence of statements> S'EVENT : true if an event has occurred on S in current cycle
... signal databus : vector4(15 downto 0);
when others => <sequence of statements> S'ACTIVE : true if signal S is active in the current cycle
signal internal : bit_vector(15 downto 0);
end case; variable x : integer; S'TRANSACTION : bit value which toggles each time signal S changes
...
databus <= bv2slv(internal);
x := b2n(internal); Examples
Loop statements
Data conversion between ieee types and bit / bit_vector (functions in ieee.std_logic_1164 ) if (clock'STABLE(0ns)) then -- change in clock?
[<label>:] while <condition> loop ... -- action if no clock edge
<sequence of statements> else
end loop <label>; ... -- action on edge of clock
function from to end if;
[<label>:] for <loop variable> in range loop
<sequence of statements> if clock'EVENT and clock = '1' then
end loop <label>; To_bit(sul) std_ulogic bit Q <= D after 5ns; -- set Q to D on rising edge of clock
end if;
std_ulogic_vector ,
Loop termination statements: allow termination of one iteration, loop, or procedure. To_bitvector(sulv) bit_vector
std_logic_vector
next [when condition]; : end current loop iteration Data Type Bounds (Attributes of data type T)
exit [when condition]; : exit innermost loop entirely
To_StdULogic(b) bit std_ulogic
return expression; : exit from subprogram
T'BASE : base type of T
rising_edge(s) - true if rising edge on signal s ( std_ulogic ) A'RIGHT(N) : right bound of index
FUNCTIONS falling_edge(s) - true if falling edge on signal s ( std_ulogic ) A'HIGH(N) : upper bound of index
A'LOW(N) : lower bound of index
A'LENGTH(N) : number of values in range of index
-- Convert bit_vector to IEEE std_logic_vector format
-- (attributes LENGTH and RANGE are described below)
OBJECT ATTRIBUTES A'RANGE(N) : range: A'LEFT to A'RIGHT
function bv2slv (b : bit_vector) return std_logic_vector is A'REVERSE_RANGE(N) : range A'LEFT downto A'RIGHT
variable result : std_logic_vector(b'LENGTH-1 downto 0);
begin An object attribute returns information about a signal or data type.
for i in result'RANGE loop Examples
case b(i) is
when '0' => result(i) := '0'; Signal Condition Attributes (for a signal S)
when '1' => result(i) := '1'; for i in (<data bus>'RANGE) loop
end case; ...
end loop; S'DELAYED(T) : value of S delayed by T time units for i in (d'LEFT(1) to d'RIGHT(1)) loop
return result; ...
S'STABLE(T) : true if no event on S over last T time units
end;
S'QUIET(T) : true if S quiet for T time units
S'LAST_VALUE : value of S prior to latest change