package ee530 is Logical:  and ,  or ,  nand ,  nor ,  xor ,  not  (for boolean or bit ops)

constant maxint: integer := 16#ffff#; Relational:  = ,  /= ,  < ,  <= ,  > ,  >= 
VHDL Cheatsheet type arith_mode_type is (signed, unsigned);
function minimum(constant a, b : in integer) return integer;
Arithmetic:  + ,  - ,  * ,  / ,  mod ,  rem ,  **  (exponential),  abs 
end ee530; Concatenate:  & 

Based on https://www.ics.uci.edu/~jmoorkan/vhdlref/vhdl.html
Package body format VHDL DATA TYPES

PRIMARY DESIGN UNIT MODEL package body <name> is Predefined Scalar Data Types (single objects)
STRUCTURE ... exported subprogram bodies
... other internally-used declarations
end <name>; VHDL Standard

Entity Example
 bit :  0 ,  1 
 boolean :  TRUE ,  FALSE 
 integer :  -(231) to +(231 - 1)  (SUN Limit)
entity <name> is package body ee530 is  natural :  0 to integer'high  (subtype of integer)
port( <port definition list> ); -- input/output signal ports function minimum (constant a,b : integer) return integer is  positive :  1 to integer'high  (subtype of integer)
generic( <generic list> ); -- optional generic list variable c : integer; -- local variable
end <name>;  character : ASCII characters (eg.  A )
begin
if a < b then  time : (include units; eg. 10ns, 20us)
c := a; -- a is min
Port declaration format:  <port name>: <mode> <data type>;  else
c := b; -- b is min IEEE Standard 1164 (package  ieee.std_logic_1164.all )
end if;
return c; -- return min value
 in : can be read but not updated within the module
end;  std_ulogic :  U , X , 1 , 0 , Z , W , H , L , - 
 out : can be updated but not read within the module end ee530;  std_logic : resolved  std_ulogic  values
 buffer : likewise carries information out of a module, but can be both updated and read within the
 X01 : subtype { X , 0 , 1 } of  std_ulogic 
module.
 X01Z : subtype { X , 0 , 1 , Z } of  std_ulogic 
 inout : is bidirectional and can be both read and updated, with multiple update sources possible. Package Visibility  UX01 : subtype { U , X , 0 , 1 } of  std_ulogic 
 UX01Z : subtype { U , X , 0 , 1 , Z } of  std_ulogic 

entity and_gate is use <library name>.<package name>.all

port(
a,b : in std_ulogic; Predefined VHDL Aggregate Data Types
c : out std_ulogic);
generic (gate_delay: time := 5ns); Example
end and_gate;  bit_vector :  array (natural range <>) of bit 
 string :  array (natural range <>) of char 
library <lib name>; -- make library visible  text : file of  string 
use <lib name>.<pkg name>.all; -- make package visible
Architecture
IEEE Standard 1164 Aggregate Data Types
architecture <name> of <entity> is
VHDL IDENTIFIERS, NUMBERS, STRINGS, AND
<declarations> EXPRESSIONS (From package: ieee.std_logic_1164.all)
begin
<concurrent statements>
end;  std_ulogic_vector :  array (natural range <>) of std_ulogic 
Numeric Constants  std_logic_vector :  array (natural range <>) of std_logic 

VHDL PACKAGES Format:  base#digits#  (base must be a decimal number)

User-Defined Enumeration Types
Examples
Package declaration format type opcodes is (add, sub, jump, call); -- Type with 4 values

16#9fba# (hexadecimal)
2#1111_1101_1011# (binary)
package <name> is 16#f.1f#E+2 (floating-point, exponent is decimal) Other user-defined types
... exported constant declarations
... exported type declarations
... exported subprogram declarations Constrained array: Upper and lower indexes are specified:
end <name>; Bit String Literals type aWord is array (0 to 15) of bit;
constant cWord1 : word := (0 => '0', 1 => '1', 7 => '1', others => '0');
constant cWord2 : word := ('0', '0', '0', '0', '0', '0', '0', ...);
Example x"ffe" (12-bit hexadecimal value)
o"777" (9-bit octal value)
b"1111_1101_1101" (12-bit binary value)
Unconstrained array:

Arithmetic and Logical Expressions

 type memory is array (integer range <>) of bit_vector(0 to 7); 2. A <= B when <condition1> else Example
-- a type which is an arbitrary-sized array of 8-bit vectors C when <condition2> else
constant cMem : memory(0 to 1) := ("00001111", "11110000"); D when <condition3> else E;
A1: adder port map(a => v, b => w, s => y, cin => x, cout => z);

Subtype: 3. with <expression> select A <=

subtype byte_signed is integer range -128 to 127; B when choice1, Concurrent assertion
subtype byte_unsigned is integer range 0 to 255; C when choice2,
constant cValue : byte_unsigned := 73; D when choice3,
E when others;
assert (clear /= '1') or (preset /= '1')
report "Both preset and clear are set!"
severity warning;
Record:
Examples
type aReg is record
state : aState;
data : std_ulogic_vector(7 downto 0);
A <= B after 10ns when condition1 else
Generate statement
end record
C after 12ns when condition2 else
D after 11ns;
constant cReg : aReg := ( add_label: for i in 4 downto 1 generate
state => Init, FA: full_adder port map(C(i-1), A(i), B(i), C(i), Sum(i));
-- 4-input multiplexer (Choice is a 2-bit vector)
data => (others => '0')); end generate;
with Choice select Out <=
In0 after 2ns when "00",
In1 after 2ns when "01", LOWER_BIT: if I=0 generate
U0: HALFADD port map
Aliases In2 after 2ns when "10",
In3 after 2ns when "11"; (A(I),B(I),S(I),C(I));
end generate LOWER_BIT;
-- A is a 16-bit vector
signal instruction : bit_vector(31 downto 0); A <= (others => '0'); -- set all bits of A to '0'
alias opcode : bit_vector(6 downto 0) is instruction(31 downto 25);
... SEQUENTIAL STATEMENTS
opcode <= "1010101"; -- Set the opcode part of an instruction code
Process Statement
Wait statement
VHDL OBJECTS: CONSTANTS, VARIABLES, AND Syntax
SIGNALS wait [on <signal> {, <signal>}]
[until condition]
label: process (sensitivity list)
[for time expression]
<local declarations>
Constants begin
<sequential statements>
end process label; Example
constant Vcc : signal := '1'; -- logic 1 constant
constant zero4 : bit_vector(0 to 3) := ('0','0','0','0');
Example wait until clock = '1' or enable /= '1' for 25ns;

Variables DFF: process (clock)

begin
Signal assignment statement
if clock = '1' then
process Q <= D after 5ns;
variable count : integer := 0; QN <= not D after 5ns; A <= B after 10ns;
variable rega : bit_vector(7 downto 0); end if; C <= A after 10ns; -- value of C is current A value
begin end process DFF;
...
count := 7; -- assign values to variables
rega := x"01"; Variable assignment statement
... Concurrent Procedure Call
end;
A := B and C;
ReadMemory (DataIn, DataOut, RW, Clk); -- (where the ReadMemory procedure is defined else D := A; -- value of D is new A value
Signals
Component instantiation Conditional Statements
signal clock : bit;
signal GND : bit := '0';
signal databus : std_ulogic_vector(15 downto 0); Standard  if...then  and  case  constructs can be used for selective operations.
<instance name>: <component name> port map (port list);
signal addrbus : std_logic_vector(0 to 31);

if <condition> then
The port list may be in either of two formats:
CONCURRENT STATEMENTS <sequence of statements>
elsif <condition> then
<sequence of statements>
(1) Positional association: signals are connected to ports in the order listed in the component else
Concurrent Signal Assignment declaration. Example:  A1: adder port map (v,w,x,y,z)  (v,w, and y must be of type <sequence of statements>
 bit_vector , y and z of type  bit ) end if;

(2) Named association: each signal-to-port connection is listed explicitly as  signal => port .
1. A <= B;
 case <expression> is Function Calls  S'LAST_EVENT : time at which S last changed
when <choice(s)> => <sequence of statements>  S'LAST_ACTIVE : time at which S last active
when <choice range> => <sequence of statements>  S'EVENT : true if an event has occurred on S in current cycle
... signal databus : vector4(15 downto 0);
when others => <sequence of statements>  S'ACTIVE : true if signal S is active in the current cycle
signal internal : bit_vector(15 downto 0);
end case; variable x : integer;  S'TRANSACTION : bit value which toggles each time signal S changes
...
databus <= bv2slv(internal);
x := b2n(internal); Examples
Loop statements

Data conversion between ieee types and  bit / bit_vector  (functions in  ieee.std_logic_1164 ) if (clock'STABLE(0ns)) then -- change in clock?
[<label>:] while <condition> loop ... -- action if no clock edge
<sequence of statements> else
end loop <label>; ... -- action on edge of clock
function from to end if;
[<label>:] for <loop variable> in range loop
<sequence of statements> if clock'EVENT and clock = '1' then
end loop <label>;  To_bit(sul)   std_ulogic   bit  Q <= D after 5ns; -- set Q to D on rising edge of clock
end if;

 std_ulogic_vector ,
Loop termination statements: allow termination of one iteration, loop, or procedure.  To_bitvector(sulv)   bit_vector 
 std_logic_vector 
 next [when condition]; : end current loop iteration Data Type Bounds (Attributes of data type T)
 exit [when condition]; : exit innermost loop entirely
 To_StdULogic(b)   bit   std_ulogic 
 return expression; : exit from subprogram
 T'BASE : base type of T

 bit_vector  or  T'LEFT : left bound of data type T

NOTES:  To_StdLogicVector(bv)   std_logic_vector 
 std_ulogic_vector   T'RIGHT : right bound
 T'HIGH : upper bound (may differ from left bound)

1. The next/exit condition clause is optional.  bit_vector  or  T'LOW : lower bound

 To_StdULogicVector(bv)   std_ulogic_vector 
2. The return expression is used for functions.  std_logic_vector 

Enumeration Data Types (Variable/signal x of data type T)

 bit ,  std_ulogic , or
PROCEDURES  To_X01(v) 
 std_logic 
 X01 
 T'POS(x) : position number of value of x of type T
 T'VAL(x) : value of type T whose position number is x
procedure <name> (  bit ,  std_ulogic , or
signal clk : in vlbit;  To_X01Z(v)   X01Z   T'SUCC(x) : value of type T whose position is x+1
 std_logic 
constant d : in vlbit;  T'PRED(x) : value of type T whose position is x-1
signal data : out vlbit) is  T'LEFTOF(x) : value of type T whose position is left of x
<local variable declarations>  bit ,  std_ulogic , or
begin  To_UX01(v)   UX01   T'RIGHTOF(x) : value of type T whose position is right of x
 std_logic 
<sequence of statements>
end <proc name>;
Array Indexes for an Array A (Nth index of array A)
Other  ieee.std_logic_1164  functions
Procedure call:  <name>(clk1, d1, dout); 
 A'LEFT(N) : left bound of index

 rising_edge(s)  -  true  if rising edge on signal s ( std_ulogic )  A'RIGHT(N) : right bound of index

FUNCTIONS  falling_edge(s)  -  true  if falling edge on signal s ( std_ulogic )  A'HIGH(N) : upper bound of index
 A'LOW(N) : lower bound of index
 A'LENGTH(N) : number of values in range of index
-- Convert bit_vector to IEEE std_logic_vector format
-- (attributes LENGTH and RANGE are described below)
OBJECT ATTRIBUTES  A'RANGE(N) : range:  A'LEFT to A'RIGHT 

function bv2slv (b : bit_vector) return std_logic_vector is  A'REVERSE_RANGE(N) : range  A'LEFT downto A'RIGHT 
variable result : std_logic_vector(b'LENGTH-1 downto 0);
begin An object attribute returns information about a signal or data type.
for i in result'RANGE loop Examples
case b(i) is
when '0' => result(i) := '0'; Signal Condition Attributes (for a signal S)
when '1' => result(i) := '1'; for i in (<data bus>'RANGE) loop
end case; ...
end loop;  S'DELAYED(T) : value of S delayed by T time units for i in (d'LEFT(1) to d'RIGHT(1)) loop
return result; ...
 S'STABLE(T) : true if no event on S over last T time units
end;
 S'QUIET(T) : true if S quiet for T time units
 S'LAST_VALUE : value of S prior to latest change